arch/x86/kvm/svm/svm.c

   1 #define pr_fmt(fmt) "SVM: " fmt
   2
   3 #include <linux/kvm_host.h>
   4
   5 #include "irq.h"
   6 #include "mmu.h"
   7 #include "kvm_cache_regs.h"
   8 #include "x86.h"
   9 #include "cpuid.h"
  10 #include "pmu.h"
  11
  12 #include <linux/module.h>
  13 #include <linux/mod_devicetable.h>
  14 #include <linux/kernel.h>
  15 #include <linux/vmalloc.h>
  16 #include <linux/highmem.h>
  17 #include <linux/amd-iommu.h>
  18 #include <linux/sched.h>
  19 #include <linux/trace_events.h>
  20 #include <linux/slab.h>
  21 #include <linux/hashtable.h>
  22 #include <linux/frame.h>
  23 #include <linux/psp-sev.h>
  24 #include <linux/file.h>
  25 #include <linux/pagemap.h>
  26 #include <linux/swap.h>
  27 #include <linux/rwsem.h>
  28
  29 #include <asm/apic.h>
  30 #include <asm/perf_event.h>
  31 #include <asm/tlbflush.h>
  32 #include <asm/desc.h>
  33 #include <asm/debugreg.h>
  34 #include <asm/kvm_para.h>
  35 #include <asm/irq_remapping.h>
  36 #include <asm/mce.h>
  37 #include <asm/spec-ctrl.h>
  38 #include <asm/cpu_device_id.h>
  39
  40 #include <asm/virtext.h>
  41 #include "trace.h"
  42
  43 #include "svm.h"
  44
  45 #define __ex(x) __kvm_handle_fault_on_reboot(x)
  46
  47 MODULE_AUTHOR("Qumranet");
  48 MODULE_LICENSE("GPL");
  49
  50 #ifdef MODULE
  51 static const struct x86_cpu_id svm_cpu_id[] = {
  52         X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
  53         {}
  54 };
  55 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
  56 #endif
  57
  58 #define IOPM_ALLOC_ORDER 2
  59 #define MSRPM_ALLOC_ORDER 1
  60
  61 #define SEG_TYPE_LDT 2
  62 #define SEG_TYPE_BUSY_TSS16 3
  63
  64 #define SVM_FEATURE_LBRV           (1 <<  1)
  65 #define SVM_FEATURE_SVML           (1 <<  2)
  66 #define SVM_FEATURE_TSC_RATE       (1 <<  4)
  67 #define SVM_FEATURE_VMCB_CLEAN     (1 <<  5)
  68 #define SVM_FEATURE_FLUSH_ASID     (1 <<  6)
  69 #define SVM_FEATURE_DECODE_ASSIST  (1 <<  7)
  70 #define SVM_FEATURE_PAUSE_FILTER   (1 << 10)
  71
  72 #define DEBUGCTL_RESERVED_BITS (~(0x3fULL))
  73
  74 #define TSC_RATIO_RSVD          0xffffff0000000000ULL
  75 #define TSC_RATIO_MIN           0x0000000000000001ULL
  76 #define TSC_RATIO_MAX           0x000000ffffffffffULL
  77
  78 static bool erratum_383_found __read_mostly;
  79
  80 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
  81
  82 /*
  83  * Set osvw_len to higher value when updated Revision Guides
  84  * are published and we know what the new status bits are
  85  */
  86 static uint64_t osvw_len = 4, osvw_status;
  87
  88 static DEFINE_PER_CPU(u64, current_tsc_ratio);
  89 #define TSC_RATIO_DEFAULT       0x0100000000ULL
  90
  91 static const struct svm_direct_access_msrs {
  92         u32 index;   /* Index of the MSR */
  93         bool always; /* True if intercept is always on */
  94 } direct_access_msrs[] = {
  95         { .index = MSR_STAR,                            .always = true  },
  96         { .index = MSR_IA32_SYSENTER_CS,                .always = true  },
  97 #ifdef CONFIG_X86_64
  98         { .index = MSR_GS_BASE,                         .always = true  },
  99         { .index = MSR_FS_BASE,                         .always = true  },
 100         { .index = MSR_KERNEL_GS_BASE,                  .always = true  },
 101         { .index = MSR_LSTAR,                           .always = true  },
 102         { .index = MSR_CSTAR,                           .always = true  },
 103         { .index = MSR_SYSCALL_MASK,                    .always = true  },
 104 #endif
 105         { .index = MSR_IA32_SPEC_CTRL,                  .always = false },
 106         { .index = MSR_IA32_PRED_CMD,                   .always = false },
 107         { .index = MSR_IA32_LASTBRANCHFROMIP,           .always = false },
 108         { .index = MSR_IA32_LASTBRANCHTOIP,             .always = false },
 109         { .index = MSR_IA32_LASTINTFROMIP,              .always = false },
 110         { .index = MSR_IA32_LASTINTTOIP,                .always = false },
 111         { .index = MSR_INVALID,                         .always = false },
 112 };
 113
 114 /* enable NPT for AMD64 and X86 with PAE */
 115 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
 116 bool npt_enabled = true;
 117 #else
 118 bool npt_enabled;
 119 #endif
 120
 121 /*
 122  * These 2 parameters are used to config the controls for Pause-Loop Exiting:
 123  * pause_filter_count: On processors that support Pause filtering(indicated
 124  *      by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
 125  *      count value. On VMRUN this value is loaded into an internal counter.
 126  *      Each time a pause instruction is executed, this counter is decremented
 127  *      until it reaches zero at which time a #VMEXIT is generated if pause
 128  *      intercept is enabled. Refer to  AMD APM Vol 2 Section 15.14.4 Pause
 129  *      Intercept Filtering for more details.
 130  *      This also indicate if ple logic enabled.
 131  *
 132  * pause_filter_thresh: In addition, some processor families support advanced
 133  *      pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
 134  *      the amount of time a guest is allowed to execute in a pause loop.
 135  *      In this mode, a 16-bit pause filter threshold field is added in the
 136  *      VMCB. The threshold value is a cycle count that is used to reset the
 137  *      pause counter. As with simple pause filtering, VMRUN loads the pause
 138  *      count value from VMCB into an internal counter. Then, on each pause
 139  *      instruction the hardware checks the elapsed number of cycles since
 140  *      the most recent pause instruction against the pause filter threshold.
 141  *      If the elapsed cycle count is greater than the pause filter threshold,
 142  *      then the internal pause count is reloaded from the VMCB and execution
 143  *      continues. If the elapsed cycle count is less than the pause filter
 144  *      threshold, then the internal pause count is decremented. If the count
 145  *      value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
 146  *      triggered. If advanced pause filtering is supported and pause filter
 147  *      threshold field is set to zero, the filter will operate in the simpler,
 148  *      count only mode.
 149  */
 150
 151 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
 152 module_param(pause_filter_thresh, ushort, 0444);
 153
 154 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
 155 module_param(pause_filter_count, ushort, 0444);
 156
 157 /* Default doubles per-vcpu window every exit. */
 158 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
 159 module_param(pause_filter_count_grow, ushort, 0444);
 160
 161 /* Default resets per-vcpu window every exit to pause_filter_count. */
 162 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
 163 module_param(pause_filter_count_shrink, ushort, 0444);
 164
 165 /* Default is to compute the maximum so we can never overflow. */
 166 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
 167 module_param(pause_filter_count_max, ushort, 0444);
 168
 169 /* allow nested paging (virtualized MMU) for all guests */
 170 static int npt = true;
 171 module_param(npt, int, S_IRUGO);
 172
 173 /* allow nested virtualization in KVM/SVM */
 174 static int nested = true;
 175 module_param(nested, int, S_IRUGO);
 176
 177 /* enable/disable Next RIP Save */
 178 static int nrips = true;
 179 module_param(nrips, int, 0444);
 180
 181 /* enable/disable Virtual VMLOAD VMSAVE */
 182 static int vls = true;
 183 module_param(vls, int, 0444);
 184
 185 /* enable/disable Virtual GIF */
 186 static int vgif = true;
 187 module_param(vgif, int, 0444);
 188
 189 /* enable/disable SEV support */
 190 static int sev = IS_ENABLED(CONFIG_AMD_MEM_ENCRYPT_ACTIVE_BY_DEFAULT);
 191 module_param(sev, int, 0444);
 192
 193 static bool __read_mostly dump_invalid_vmcb = 0;
 194 module_param(dump_invalid_vmcb, bool, 0644);
 195
 196 static u8 rsm_ins_bytes[] = "\x0f\xaa";
 197
 198 static void svm_complete_interrupts(struct vcpu_svm *svm);
 199
 200 static unsigned long iopm_base;
 201
 202 struct kvm_ldttss_desc {
 203         u16 limit0;
 204         u16 base0;
 205         unsigned base1:8, type:5, dpl:2, p:1;
 206         unsigned limit1:4, zero0:3, g:1, base2:8;
 207         u32 base3;
 208         u32 zero1;
 209 } __attribute__((packed));
 210
 211 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
 212
 213 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
 214
 215 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
 216 #define MSRS_RANGE_SIZE 2048
 217 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
 218
 219 u32 svm_msrpm_offset(u32 msr)
 220 {
 221         u32 offset;
 222         int i;
 223
 224         for (i = 0; i < NUM_MSR_MAPS; i++) {
 225                 if (msr < msrpm_ranges[i] ||
 226                     msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
 227                         continue;
 228
 229                 offset  = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
 230                 offset += (i * MSRS_RANGE_SIZE);       /* add range offset */
 231
 232                 /* Now we have the u8 offset - but need the u32 offset */
 233                 return offset / 4;
 234         }
 235
 236         /* MSR not in any range */
 237         return MSR_INVALID;
 238 }
 239
 240 #define MAX_INST_SIZE 15
 241
 242 static inline void clgi(void)
 243 {
 244         asm volatile (__ex("clgi"));
 245 }
 246
 247 static inline void stgi(void)
 248 {
 249         asm volatile (__ex("stgi"));
 250 }
 251
 252 static inline void invlpga(unsigned long addr, u32 asid)
 253 {
 254         asm volatile (__ex("invlpga %1, %0") : : "c"(asid), "a"(addr));
 255 }
 256
 257 static int get_npt_level(struct kvm_vcpu *vcpu)
 258 {
 259 #ifdef CONFIG_X86_64
 260         return PT64_ROOT_4LEVEL;
 261 #else
 262         return PT32E_ROOT_LEVEL;
 263 #endif
 264 }
 265
 266 void svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
 267 {
 268         vcpu->arch.efer = efer;
 269
 270         if (!npt_enabled) {
 271                 /* Shadow paging assumes NX to be available.  */
 272                 efer |= EFER_NX;
 273
 274                 if (!(efer & EFER_LMA))
 275                         efer &= ~EFER_LME;
 276         }
 277
 278         to_svm(vcpu)->vmcb->save.efer = efer | EFER_SVME;
 279         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
 280 }
 281
 282 static int is_external_interrupt(u32 info)
 283 {
 284         info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
 285         return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
 286 }
 287
 288 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
 289 {
 290         struct vcpu_svm *svm = to_svm(vcpu);
 291         u32 ret = 0;
 292
 293         if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
 294                 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
 295         return ret;
 296 }
 297
 298 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
 299 {
 300         struct vcpu_svm *svm = to_svm(vcpu);
 301
 302         if (mask == 0)
 303                 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
 304         else
 305                 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
 306
 307 }
 308
 309 static int skip_emulated_instruction(struct kvm_vcpu *vcpu)
 310 {
 311         struct vcpu_svm *svm = to_svm(vcpu);
 312
 313         if (nrips && svm->vmcb->control.next_rip != 0) {
 314                 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
 315                 svm->next_rip = svm->vmcb->control.next_rip;
 316         }
 317
 318         if (!svm->next_rip) {
 319                 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
 320                         return 0;
 321         } else {
 322                 kvm_rip_write(vcpu, svm->next_rip);
 323         }
 324         svm_set_interrupt_shadow(vcpu, 0);
 325
 326         return 1;
 327 }
 328
 329 static void svm_queue_exception(struct kvm_vcpu *vcpu)
 330 {
 331         struct vcpu_svm *svm = to_svm(vcpu);
 332         unsigned nr = vcpu->arch.exception.nr;
 333         bool has_error_code = vcpu->arch.exception.has_error_code;
 334         u32 error_code = vcpu->arch.exception.error_code;
 335
 336         kvm_deliver_exception_payload(&svm->vcpu);
 337
 338         if (nr == BP_VECTOR && !nrips) {
 339                 unsigned long rip, old_rip = kvm_rip_read(&svm->vcpu);
 340
 341                 /*
 342                  * For guest debugging where we have to reinject #BP if some
 343                  * INT3 is guest-owned:
 344                  * Emulate nRIP by moving RIP forward. Will fail if injection
 345                  * raises a fault that is not intercepted. Still better than
 346                  * failing in all cases.
 347                  */
 348                 (void)skip_emulated_instruction(&svm->vcpu);
 349                 rip = kvm_rip_read(&svm->vcpu);
 350                 svm->int3_rip = rip + svm->vmcb->save.cs.base;
 351                 svm->int3_injected = rip - old_rip;
 352         }
 353
 354         svm->vmcb->control.event_inj = nr
 355                 | SVM_EVTINJ_VALID
 356                 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
 357                 | SVM_EVTINJ_TYPE_EXEPT;
 358         svm->vmcb->control.event_inj_err = error_code;
 359 }
 360
 361 static void svm_init_erratum_383(void)
 362 {
 363         u32 low, high;
 364         int err;
 365         u64 val;
 366
 367         if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
 368                 return;
 369
 370         /* Use _safe variants to not break nested virtualization */
 371         val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
 372         if (err)
 373                 return;
 374
 375         val |= (1ULL << 47);
 376
 377         low  = lower_32_bits(val);
 378         high = upper_32_bits(val);
 379
 380         native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
 381
 382         erratum_383_found = true;
 383 }
 384
 385 static void svm_init_osvw(struct kvm_vcpu *vcpu)
 386 {
 387         /*
 388          * Guests should see errata 400 and 415 as fixed (assuming that
 389          * HLT and IO instructions are intercepted).
 390          */
 391         vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
 392         vcpu->arch.osvw.status = osvw_status & ~(6ULL);
 393
 394         /*
 395          * By increasing VCPU's osvw.length to 3 we are telling the guest that
 396          * all osvw.status bits inside that length, including bit 0 (which is
 397          * reserved for erratum 298), are valid. However, if host processor's
 398          * osvw_len is 0 then osvw_status[0] carries no information. We need to
 399          * be conservative here and therefore we tell the guest that erratum 298
 400          * is present (because we really don't know).
 401          */
 402         if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
 403                 vcpu->arch.osvw.status |= 1;
 404 }
 405
 406 static int has_svm(void)
 407 {
 408         const char *msg;
 409
 410         if (!cpu_has_svm(&msg)) {
 411                 printk(KERN_INFO "has_svm: %s\n", msg);
 412                 return 0;
 413         }
 414
 415         return 1;
 416 }
 417
 418 static void svm_hardware_disable(void)
 419 {
 420         /* Make sure we clean up behind us */
 421         if (static_cpu_has(X86_FEATURE_TSCRATEMSR))
 422                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 423
 424         cpu_svm_disable();
 425
 426         amd_pmu_disable_virt();
 427 }
 428
 429 static int svm_hardware_enable(void)
 430 {
 431
 432         struct svm_cpu_data *sd;
 433         uint64_t efer;
 434         struct desc_struct *gdt;
 435         int me = raw_smp_processor_id();
 436
 437         rdmsrl(MSR_EFER, efer);
 438         if (efer & EFER_SVME)
 439                 return -EBUSY;
 440
 441         if (!has_svm()) {
 442                 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
 443                 return -EINVAL;
 444         }
 445         sd = per_cpu(svm_data, me);
 446         if (!sd) {
 447                 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
 448                 return -EINVAL;
 449         }
 450
 451         sd->asid_generation = 1;
 452         sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
 453         sd->next_asid = sd->max_asid + 1;
 454         sd->min_asid = max_sev_asid + 1;
 455
 456         gdt = get_current_gdt_rw();
 457         sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
 458
 459         wrmsrl(MSR_EFER, efer | EFER_SVME);
 460
 461         wrmsrl(MSR_VM_HSAVE_PA, page_to_pfn(sd->save_area) << PAGE_SHIFT);
 462
 463         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 464                 wrmsrl(MSR_AMD64_TSC_RATIO, TSC_RATIO_DEFAULT);
 465                 __this_cpu_write(current_tsc_ratio, TSC_RATIO_DEFAULT);
 466         }
 467
 468
 469         /*
 470          * Get OSVW bits.
 471          *
 472          * Note that it is possible to have a system with mixed processor
 473          * revisions and therefore different OSVW bits. If bits are not the same
 474          * on different processors then choose the worst case (i.e. if erratum
 475          * is present on one processor and not on another then assume that the
 476          * erratum is present everywhere).
 477          */
 478         if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
 479                 uint64_t len, status = 0;
 480                 int err;
 481
 482                 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
 483                 if (!err)
 484                         status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
 485                                                       &err);
 486
 487                 if (err)
 488                         osvw_status = osvw_len = 0;
 489                 else {
 490                         if (len < osvw_len)
 491                                 osvw_len = len;
 492                         osvw_status |= status;
 493                         osvw_status &= (1ULL << osvw_len) - 1;
 494                 }
 495         } else
 496                 osvw_status = osvw_len = 0;
 497
 498         svm_init_erratum_383();
 499
 500         amd_pmu_enable_virt();
 501
 502         return 0;
 503 }
 504
 505 static void svm_cpu_uninit(int cpu)
 506 {
 507         struct svm_cpu_data *sd = per_cpu(svm_data, raw_smp_processor_id());
 508
 509         if (!sd)
 510                 return;
 511
 512         per_cpu(svm_data, raw_smp_processor_id()) = NULL;
 513         kfree(sd->sev_vmcbs);
 514         __free_page(sd->save_area);
 515         kfree(sd);
 516 }
 517
 518 static int svm_cpu_init(int cpu)
 519 {
 520         struct svm_cpu_data *sd;
 521
 522         sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
 523         if (!sd)
 524                 return -ENOMEM;
 525         sd->cpu = cpu;
 526         sd->save_area = alloc_page(GFP_KERNEL);
 527         if (!sd->save_area)
 528                 goto free_cpu_data;
 529
 530         if (svm_sev_enabled()) {
 531                 sd->sev_vmcbs = kmalloc_array(max_sev_asid + 1,
 532                                               sizeof(void *),
 533                                               GFP_KERNEL);
 534                 if (!sd->sev_vmcbs)
 535                         goto free_save_area;
 536         }
 537
 538         per_cpu(svm_data, cpu) = sd;
 539
 540         return 0;
 541
 542 free_save_area:
 543         __free_page(sd->save_area);
 544 free_cpu_data:
 545         kfree(sd);
 546         return -ENOMEM;
 547
 548 }
 549
 550 static bool valid_msr_intercept(u32 index)
 551 {
 552         int i;
 553
 554         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
 555                 if (direct_access_msrs[i].index == index)
 556                         return true;
 557
 558         return false;
 559 }
 560
 561 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, unsigned msr)
 562 {
 563         u8 bit_write;
 564         unsigned long tmp;
 565         u32 offset;
 566         u32 *msrpm;
 567
 568         msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
 569                                       to_svm(vcpu)->msrpm;
 570
 571         offset    = svm_msrpm_offset(msr);
 572         bit_write = 2 * (msr & 0x0f) + 1;
 573         tmp       = msrpm[offset];
 574
 575         BUG_ON(offset == MSR_INVALID);
 576
 577         return !!test_bit(bit_write,  &tmp);
 578 }
 579
 580 static void set_msr_interception(u32 *msrpm, unsigned msr,
 581                                  int read, int write)
 582 {
 583         u8 bit_read, bit_write;
 584         unsigned long tmp;
 585         u32 offset;
 586
 587         /*
 588          * If this warning triggers extend the direct_access_msrs list at the
 589          * beginning of the file
 590          */
 591         WARN_ON(!valid_msr_intercept(msr));
 592
 593         offset    = svm_msrpm_offset(msr);
 594         bit_read  = 2 * (msr & 0x0f);
 595         bit_write = 2 * (msr & 0x0f) + 1;
 596         tmp       = msrpm[offset];
 597
 598         BUG_ON(offset == MSR_INVALID);
 599
 600         read  ? clear_bit(bit_read,  &tmp) : set_bit(bit_read,  &tmp);
 601         write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
 602
 603         msrpm[offset] = tmp;
 604 }
 605
 606 static void svm_vcpu_init_msrpm(u32 *msrpm)
 607 {
 608         int i;
 609
 610         memset(msrpm, 0xff, PAGE_SIZE * (1 << MSRPM_ALLOC_ORDER));
 611
 612         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 613                 if (!direct_access_msrs[i].always)
 614                         continue;
 615
 616                 set_msr_interception(msrpm, direct_access_msrs[i].index, 1, 1);
 617         }
 618 }
 619
 620 static void add_msr_offset(u32 offset)
 621 {
 622         int i;
 623
 624         for (i = 0; i < MSRPM_OFFSETS; ++i) {
 625
 626                 /* Offset already in list? */
 627                 if (msrpm_offsets[i] == offset)
 628                         return;
 629
 630                 /* Slot used by another offset? */
 631                 if (msrpm_offsets[i] != MSR_INVALID)
 632                         continue;
 633
 634                 /* Add offset to list */
 635                 msrpm_offsets[i] = offset;
 636
 637                 return;
 638         }
 639
 640         /*
 641          * If this BUG triggers the msrpm_offsets table has an overflow. Just
 642          * increase MSRPM_OFFSETS in this case.
 643          */
 644         BUG();
 645 }
 646
 647 static void init_msrpm_offsets(void)
 648 {
 649         int i;
 650
 651         memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
 652
 653         for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
 654                 u32 offset;
 655
 656                 offset = svm_msrpm_offset(direct_access_msrs[i].index);
 657                 BUG_ON(offset == MSR_INVALID);
 658
 659                 add_msr_offset(offset);
 660         }
 661 }
 662
 663 static void svm_enable_lbrv(struct vcpu_svm *svm)
 664 {
 665         u32 *msrpm = svm->msrpm;
 666
 667         svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
 668         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
 669         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
 670         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
 671         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
 672 }
 673
 674 static void svm_disable_lbrv(struct vcpu_svm *svm)
 675 {
 676         u32 *msrpm = svm->msrpm;
 677
 678         svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
 679         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
 680         set_msr_interception(msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
 681         set_msr_interception(msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
 682         set_msr_interception(msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
 683 }
 684
 685 void disable_nmi_singlestep(struct vcpu_svm *svm)
 686 {
 687         svm->nmi_singlestep = false;
 688
 689         if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
 690                 /* Clear our flags if they were not set by the guest */
 691                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
 692                         svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
 693                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
 694                         svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
 695         }
 696 }
 697
 698 static void grow_ple_window(struct kvm_vcpu *vcpu)
 699 {
 700         struct vcpu_svm *svm = to_svm(vcpu);
 701         struct vmcb_control_area *control = &svm->vmcb->control;
 702         int old = control->pause_filter_count;
 703
 704         control->pause_filter_count = __grow_ple_window(old,
 705                                                         pause_filter_count,
 706                                                         pause_filter_count_grow,
 707                                                         pause_filter_count_max);
 708
 709         if (control->pause_filter_count != old) {
 710                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 711                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 712                                             control->pause_filter_count, old);
 713         }
 714 }
 715
 716 static void shrink_ple_window(struct kvm_vcpu *vcpu)
 717 {
 718         struct vcpu_svm *svm = to_svm(vcpu);
 719         struct vmcb_control_area *control = &svm->vmcb->control;
 720         int old = control->pause_filter_count;
 721
 722         control->pause_filter_count =
 723                                 __shrink_ple_window(old,
 724                                                     pause_filter_count,
 725                                                     pause_filter_count_shrink,
 726                                                     pause_filter_count);
 727         if (control->pause_filter_count != old) {
 728                 mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 729                 trace_kvm_ple_window_update(vcpu->vcpu_id,
 730                                             control->pause_filter_count, old);
 731         }
 732 }
 733
 734 /*
 735  * The default MMIO mask is a single bit (excluding the present bit),
 736  * which could conflict with the memory encryption bit. Check for
 737  * memory encryption support and override the default MMIO mask if
 738  * memory encryption is enabled.
 739  */
 740 static __init void svm_adjust_mmio_mask(void)
 741 {
 742         unsigned int enc_bit, mask_bit;
 743         u64 msr, mask;
 744
 745         /* If there is no memory encryption support, use existing mask */
 746         if (cpuid_eax(0x80000000) < 0x8000001f)
 747                 return;
 748
 749         /* If memory encryption is not enabled, use existing mask */
 750         rdmsrl(MSR_K8_SYSCFG, msr);
 751         if (!(msr & MSR_K8_SYSCFG_MEM_ENCRYPT))
 752                 return;
 753
 754         enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
 755         mask_bit = boot_cpu_data.x86_phys_bits;
 756
 757         /* Increment the mask bit if it is the same as the encryption bit */
 758         if (enc_bit == mask_bit)
 759                 mask_bit++;
 760
 761         /*
 762          * If the mask bit location is below 52, then some bits above the
 763          * physical addressing limit will always be reserved, so use the
 764          * rsvd_bits() function to generate the mask. This mask, along with
 765          * the present bit, will be used to generate a page fault with
 766          * PFER.RSV = 1.
 767          *
 768          * If the mask bit location is 52 (or above), then clear the mask.
 769          */
 770         mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
 771
 772         kvm_mmu_set_mmio_spte_mask(mask, PT_WRITABLE_MASK | PT_USER_MASK);
 773 }
 774
 775 static void svm_hardware_teardown(void)
 776 {
 777         int cpu;
 778
 779         if (svm_sev_enabled())
 780                 sev_hardware_teardown();
 781
 782         for_each_possible_cpu(cpu)
 783                 svm_cpu_uninit(cpu);
 784
 785         __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT), IOPM_ALLOC_ORDER);
 786         iopm_base = 0;
 787 }
 788
 789 static __init void svm_set_cpu_caps(void)
 790 {
 791         kvm_set_cpu_caps();
 792
 793         supported_xss = 0;
 794
 795         /* CPUID 0x80000001 and 0x8000000A (SVM features) */
 796         if (nested) {
 797                 kvm_cpu_cap_set(X86_FEATURE_SVM);
 798
 799                 if (nrips)
 800                         kvm_cpu_cap_set(X86_FEATURE_NRIPS);
 801
 802                 if (npt_enabled)
 803                         kvm_cpu_cap_set(X86_FEATURE_NPT);
 804         }
 805
 806         /* CPUID 0x80000008 */
 807         if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
 808             boot_cpu_has(X86_FEATURE_AMD_SSBD))
 809                 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
 810 }
 811
 812 static __init int svm_hardware_setup(void)
 813 {
 814         int cpu;
 815         struct page *iopm_pages;
 816         void *iopm_va;
 817         int r;
 818
 819         iopm_pages = alloc_pages(GFP_KERNEL, IOPM_ALLOC_ORDER);
 820
 821         if (!iopm_pages)
 822                 return -ENOMEM;
 823
 824         iopm_va = page_address(iopm_pages);
 825         memset(iopm_va, 0xff, PAGE_SIZE * (1 << IOPM_ALLOC_ORDER));
 826         iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
 827
 828         init_msrpm_offsets();
 829
 830         supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS | XFEATURE_MASK_BNDCSR);
 831
 832         if (boot_cpu_has(X86_FEATURE_NX))
 833                 kvm_enable_efer_bits(EFER_NX);
 834
 835         if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
 836                 kvm_enable_efer_bits(EFER_FFXSR);
 837
 838         if (boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
 839                 kvm_has_tsc_control = true;
 840                 kvm_max_tsc_scaling_ratio = TSC_RATIO_MAX;
 841                 kvm_tsc_scaling_ratio_frac_bits = 32;
 842         }
 843
 844         /* Check for pause filtering support */
 845         if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
 846                 pause_filter_count = 0;
 847                 pause_filter_thresh = 0;
 848         } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
 849                 pause_filter_thresh = 0;
 850         }
 851
 852         if (nested) {
 853                 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
 854                 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
 855         }
 856
 857         if (sev) {
 858                 if (boot_cpu_has(X86_FEATURE_SEV) &&
 859                     IS_ENABLED(CONFIG_KVM_AMD_SEV)) {
 860                         r = sev_hardware_setup();
 861                         if (r)
 862                                 sev = false;
 863                 } else {
 864                         sev = false;
 865                 }
 866         }
 867
 868         svm_adjust_mmio_mask();
 869
 870         for_each_possible_cpu(cpu) {
 871                 r = svm_cpu_init(cpu);
 872                 if (r)
 873                         goto err;
 874         }
 875
 876         if (!boot_cpu_has(X86_FEATURE_NPT))
 877                 npt_enabled = false;
 878
 879         if (npt_enabled && !npt)
 880                 npt_enabled = false;
 881
 882         kvm_configure_mmu(npt_enabled, PG_LEVEL_1G);
 883         pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
 884
 885         if (nrips) {
 886                 if (!boot_cpu_has(X86_FEATURE_NRIPS))
 887                         nrips = false;
 888         }
 889
 890         if (avic) {
 891                 if (!npt_enabled ||
 892                     !boot_cpu_has(X86_FEATURE_AVIC) ||
 893                     !IS_ENABLED(CONFIG_X86_LOCAL_APIC)) {
 894                         avic = false;
 895                 } else {
 896                         pr_info("AVIC enabled\n");
 897
 898                         amd_iommu_register_ga_log_notifier(&avic_ga_log_notifier);
 899                 }
 900         }
 901
 902         if (vls) {
 903                 if (!npt_enabled ||
 904                     !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
 905                     !IS_ENABLED(CONFIG_X86_64)) {
 906                         vls = false;
 907                 } else {
 908                         pr_info("Virtual VMLOAD VMSAVE supported\n");
 909                 }
 910         }
 911
 912         if (vgif) {
 913                 if (!boot_cpu_has(X86_FEATURE_VGIF))
 914                         vgif = false;
 915                 else
 916                         pr_info("Virtual GIF supported\n");
 917         }
 918
 919         svm_set_cpu_caps();
 920
 921         return 0;
 922
 923 err:
 924         svm_hardware_teardown();
 925         return r;
 926 }
 927
 928 static void init_seg(struct vmcb_seg *seg)
 929 {
 930         seg->selector = 0;
 931         seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
 932                       SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
 933         seg->limit = 0xffff;
 934         seg->base = 0;
 935 }
 936
 937 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
 938 {
 939         seg->selector = 0;
 940         seg->attrib = SVM_SELECTOR_P_MASK | type;
 941         seg->limit = 0xffff;
 942         seg->base = 0;
 943 }
 944
 945 static u64 svm_write_l1_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
 946 {
 947         struct vcpu_svm *svm = to_svm(vcpu);
 948         u64 g_tsc_offset = 0;
 949
 950         if (is_guest_mode(vcpu)) {
 951                 /* Write L1's TSC offset.  */
 952                 g_tsc_offset = svm->vmcb->control.tsc_offset -
 953                                svm->nested.hsave->control.tsc_offset;
 954                 svm->nested.hsave->control.tsc_offset = offset;
 955         }
 956
 957         trace_kvm_write_tsc_offset(vcpu->vcpu_id,
 958                                    svm->vmcb->control.tsc_offset - g_tsc_offset,
 959                                    offset);
 960
 961         svm->vmcb->control.tsc_offset = offset + g_tsc_offset;
 962
 963         mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
 964         return svm->vmcb->control.tsc_offset;
 965 }
 966
 967 static void init_vmcb(struct vcpu_svm *svm)
 968 {
 969         struct vmcb_control_area *control = &svm->vmcb->control;
 970         struct vmcb_save_area *save = &svm->vmcb->save;
 971
 972         svm->vcpu.arch.hflags = 0;
 973
 974         set_cr_intercept(svm, INTERCEPT_CR0_READ);
 975         set_cr_intercept(svm, INTERCEPT_CR3_READ);
 976         set_cr_intercept(svm, INTERCEPT_CR4_READ);
 977         set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
 978         set_cr_intercept(svm, INTERCEPT_CR3_WRITE);
 979         set_cr_intercept(svm, INTERCEPT_CR4_WRITE);
 980         if (!kvm_vcpu_apicv_active(&svm->vcpu))
 981                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
 982
 983         set_dr_intercepts(svm);
 984
 985         set_exception_intercept(svm, PF_VECTOR);
 986         set_exception_intercept(svm, UD_VECTOR);
 987         set_exception_intercept(svm, MC_VECTOR);
 988         set_exception_intercept(svm, AC_VECTOR);
 989         set_exception_intercept(svm, DB_VECTOR);
 990         /*
 991          * Guest access to VMware backdoor ports could legitimately
 992          * trigger #GP because of TSS I/O permission bitmap.
 993          * We intercept those #GP and allow access to them anyway
 994          * as VMware does.
 995          */
 996         if (enable_vmware_backdoor)
 997                 set_exception_intercept(svm, GP_VECTOR);
 998
 999         set_intercept(svm, INTERCEPT_INTR);
1000         set_intercept(svm, INTERCEPT_NMI);
1001         set_intercept(svm, INTERCEPT_SMI);
1002         set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1003         set_intercept(svm, INTERCEPT_RDPMC);
1004         set_intercept(svm, INTERCEPT_CPUID);
1005         set_intercept(svm, INTERCEPT_INVD);
1006         set_intercept(svm, INTERCEPT_INVLPG);
1007         set_intercept(svm, INTERCEPT_INVLPGA);
1008         set_intercept(svm, INTERCEPT_IOIO_PROT);
1009         set_intercept(svm, INTERCEPT_MSR_PROT);
1010         set_intercept(svm, INTERCEPT_TASK_SWITCH);
1011         set_intercept(svm, INTERCEPT_SHUTDOWN);
1012         set_intercept(svm, INTERCEPT_VMRUN);
1013         set_intercept(svm, INTERCEPT_VMMCALL);
1014         set_intercept(svm, INTERCEPT_VMLOAD);
1015         set_intercept(svm, INTERCEPT_VMSAVE);
1016         set_intercept(svm, INTERCEPT_STGI);
1017         set_intercept(svm, INTERCEPT_CLGI);
1018         set_intercept(svm, INTERCEPT_SKINIT);
1019         set_intercept(svm, INTERCEPT_WBINVD);
1020         set_intercept(svm, INTERCEPT_XSETBV);
1021         set_intercept(svm, INTERCEPT_RDPRU);
1022         set_intercept(svm, INTERCEPT_RSM);
1023
1024         if (!kvm_mwait_in_guest(svm->vcpu.kvm)) {
1025                 set_intercept(svm, INTERCEPT_MONITOR);
1026                 set_intercept(svm, INTERCEPT_MWAIT);
1027         }
1028
1029         if (!kvm_hlt_in_guest(svm->vcpu.kvm))
1030                 set_intercept(svm, INTERCEPT_HLT);
1031
1032         control->iopm_base_pa = __sme_set(iopm_base);
1033         control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1034         control->int_ctl = V_INTR_MASKING_MASK;
1035
1036         init_seg(&save->es);
1037         init_seg(&save->ss);
1038         init_seg(&save->ds);
1039         init_seg(&save->fs);
1040         init_seg(&save->gs);
1041
1042         save->cs.selector = 0xf000;
1043         save->cs.base = 0xffff0000;
1044         /* Executable/Readable Code Segment */
1045         save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1046                 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1047         save->cs.limit = 0xffff;
1048
1049         save->gdtr.limit = 0xffff;
1050         save->idtr.limit = 0xffff;
1051
1052         init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1053         init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1054
1055         svm_set_efer(&svm->vcpu, 0);
1056         save->dr6 = 0xffff0ff0;
1057         kvm_set_rflags(&svm->vcpu, 2);
1058         save->rip = 0x0000fff0;
1059         svm->vcpu.arch.regs[VCPU_REGS_RIP] = save->rip;
1060
1061         /*
1062          * svm_set_cr0() sets PG and WP and clears NW and CD on save->cr0.
1063          * It also updates the guest-visible cr0 value.
1064          */
1065         svm_set_cr0(&svm->vcpu, X86_CR0_NW | X86_CR0_CD | X86_CR0_ET);
1066         kvm_mmu_reset_context(&svm->vcpu);
1067
1068         save->cr4 = X86_CR4_PAE;
1069         /* rdx = ?? */
1070
1071         if (npt_enabled) {
1072                 /* Setup VMCB for Nested Paging */
1073                 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1074                 clr_intercept(svm, INTERCEPT_INVLPG);
1075                 clr_exception_intercept(svm, PF_VECTOR);
1076                 clr_cr_intercept(svm, INTERCEPT_CR3_READ);
1077                 clr_cr_intercept(svm, INTERCEPT_CR3_WRITE);
1078                 save->g_pat = svm->vcpu.arch.pat;
1079                 save->cr3 = 0;
1080                 save->cr4 = 0;
1081         }
1082         svm->asid_generation = 0;
1083
1084         svm->nested.vmcb = 0;
1085         svm->vcpu.arch.hflags = 0;
1086
1087         if (pause_filter_count) {
1088                 control->pause_filter_count = pause_filter_count;
1089                 if (pause_filter_thresh)
1090                         control->pause_filter_thresh = pause_filter_thresh;
1091                 set_intercept(svm, INTERCEPT_PAUSE);
1092         } else {
1093                 clr_intercept(svm, INTERCEPT_PAUSE);
1094         }
1095
1096         if (kvm_vcpu_apicv_active(&svm->vcpu))
1097                 avic_init_vmcb(svm);
1098
1099         /*
1100          * If hardware supports Virtual VMLOAD VMSAVE then enable it
1101          * in VMCB and clear intercepts to avoid #VMEXIT.
1102          */
1103         if (vls) {
1104                 clr_intercept(svm, INTERCEPT_VMLOAD);
1105                 clr_intercept(svm, INTERCEPT_VMSAVE);
1106                 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1107         }
1108
1109         if (vgif) {
1110                 clr_intercept(svm, INTERCEPT_STGI);
1111                 clr_intercept(svm, INTERCEPT_CLGI);
1112                 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1113         }
1114
1115         if (sev_guest(svm->vcpu.kvm)) {
1116                 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1117                 clr_exception_intercept(svm, UD_VECTOR);
1118         }
1119
1120         mark_all_dirty(svm->vmcb);
1121
1122         enable_gif(svm);
1123
1124 }
1125
1126 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1127 {
1128         struct vcpu_svm *svm = to_svm(vcpu);
1129         u32 dummy;
1130         u32 eax = 1;
1131
1132         svm->spec_ctrl = 0;
1133         svm->virt_spec_ctrl = 0;
1134
1135         if (!init_event) {
1136                 svm->vcpu.arch.apic_base = APIC_DEFAULT_PHYS_BASE |
1137                                            MSR_IA32_APICBASE_ENABLE;
1138                 if (kvm_vcpu_is_reset_bsp(&svm->vcpu))
1139                         svm->vcpu.arch.apic_base |= MSR_IA32_APICBASE_BSP;
1140         }
1141         init_vmcb(svm);
1142
1143         kvm_cpuid(vcpu, &eax, &dummy, &dummy, &dummy, false);
1144         kvm_rdx_write(vcpu, eax);
1145
1146         if (kvm_vcpu_apicv_active(vcpu) && !init_event)
1147                 avic_update_vapic_bar(svm, APIC_DEFAULT_PHYS_BASE);
1148 }
1149
1150 static int svm_create_vcpu(struct kvm_vcpu *vcpu)
1151 {
1152         struct vcpu_svm *svm;
1153         struct page *page;
1154         struct page *msrpm_pages;
1155         struct page *hsave_page;
1156         struct page *nested_msrpm_pages;
1157         int err;
1158
1159         BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1160         svm = to_svm(vcpu);
1161
1162         err = -ENOMEM;
1163         page = alloc_page(GFP_KERNEL_ACCOUNT);
1164         if (!page)
1165                 goto out;
1166
1167         msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1168         if (!msrpm_pages)
1169                 goto free_page1;
1170
1171         nested_msrpm_pages = alloc_pages(GFP_KERNEL_ACCOUNT, MSRPM_ALLOC_ORDER);
1172         if (!nested_msrpm_pages)
1173                 goto free_page2;
1174
1175         hsave_page = alloc_page(GFP_KERNEL_ACCOUNT);
1176         if (!hsave_page)
1177                 goto free_page3;
1178
1179         err = avic_init_vcpu(svm);
1180         if (err)
1181                 goto free_page4;
1182
1183         /* We initialize this flag to true to make sure that the is_running
1184          * bit would be set the first time the vcpu is loaded.
1185          */
1186         if (irqchip_in_kernel(vcpu->kvm) && kvm_apicv_activated(vcpu->kvm))
1187                 svm->avic_is_running = true;
1188
1189         svm->nested.hsave = page_address(hsave_page);
1190
1191         svm->msrpm = page_address(msrpm_pages);
1192         svm_vcpu_init_msrpm(svm->msrpm);
1193
1194         svm->nested.msrpm = page_address(nested_msrpm_pages);
1195         svm_vcpu_init_msrpm(svm->nested.msrpm);
1196
1197         svm->vmcb = page_address(page);
1198         clear_page(svm->vmcb);
1199         svm->vmcb_pa = __sme_set(page_to_pfn(page) << PAGE_SHIFT);
1200         svm->asid_generation = 0;
1201         init_vmcb(svm);
1202
1203         svm_init_osvw(vcpu);
1204         vcpu->arch.microcode_version = 0x01000065;
1205
1206         return 0;
1207
1208 free_page4:
1209         __free_page(hsave_page);
1210 free_page3:
1211         __free_pages(nested_msrpm_pages, MSRPM_ALLOC_ORDER);
1212 free_page2:
1213         __free_pages(msrpm_pages, MSRPM_ALLOC_ORDER);
1214 free_page1:
1215         __free_page(page);
1216 out:
1217         return err;
1218 }
1219
1220 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1221 {
1222         int i;
1223
1224         for_each_online_cpu(i)
1225                 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1226 }
1227
1228 static void svm_free_vcpu(struct kvm_vcpu *vcpu)
1229 {
1230         struct vcpu_svm *svm = to_svm(vcpu);
1231
1232         /*
1233          * The vmcb page can be recycled, causing a false negative in
1234          * svm_vcpu_load(). So, ensure that no logical CPU has this
1235          * vmcb page recorded as its current vmcb.
1236          */
1237         svm_clear_current_vmcb(svm->vmcb);
1238
1239         __free_page(pfn_to_page(__sme_clr(svm->vmcb_pa) >> PAGE_SHIFT));
1240         __free_pages(virt_to_page(svm->msrpm), MSRPM_ALLOC_ORDER);
1241         __free_page(virt_to_page(svm->nested.hsave));
1242         __free_pages(virt_to_page(svm->nested.msrpm), MSRPM_ALLOC_ORDER);
1243 }
1244
1245 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1246 {
1247         struct vcpu_svm *svm = to_svm(vcpu);
1248         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1249         int i;
1250
1251         if (unlikely(cpu != vcpu->cpu)) {
1252                 svm->asid_generation = 0;
1253                 mark_all_dirty(svm->vmcb);
1254         }
1255
1256 #ifdef CONFIG_X86_64
1257         rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host.gs_base);
1258 #endif
1259         savesegment(fs, svm->host.fs);
1260         savesegment(gs, svm->host.gs);
1261         svm->host.ldt = kvm_read_ldt();
1262
1263         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1264                 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1265
1266         if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
1267                 u64 tsc_ratio = vcpu->arch.tsc_scaling_ratio;
1268                 if (tsc_ratio != __this_cpu_read(current_tsc_ratio)) {
1269                         __this_cpu_write(current_tsc_ratio, tsc_ratio);
1270                         wrmsrl(MSR_AMD64_TSC_RATIO, tsc_ratio);
1271                 }
1272         }
1273         /* This assumes that the kernel never uses MSR_TSC_AUX */
1274         if (static_cpu_has(X86_FEATURE_RDTSCP))
1275                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
1276
1277         if (sd->current_vmcb != svm->vmcb) {
1278                 sd->current_vmcb = svm->vmcb;
1279                 indirect_branch_prediction_barrier();
1280         }
1281         avic_vcpu_load(vcpu, cpu);
1282 }
1283
1284 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1285 {
1286         struct vcpu_svm *svm = to_svm(vcpu);
1287         int i;
1288
1289         avic_vcpu_put(vcpu);
1290
1291         ++vcpu->stat.host_state_reload;
1292         kvm_load_ldt(svm->host.ldt);
1293 #ifdef CONFIG_X86_64
1294         loadsegment(fs, svm->host.fs);
1295         wrmsrl(MSR_KERNEL_GS_BASE, current->thread.gsbase);
1296         load_gs_index(svm->host.gs);
1297 #else
1298 #ifdef CONFIG_X86_32_LAZY_GS
1299         loadsegment(gs, svm->host.gs);
1300 #endif
1301 #endif
1302         for (i = 0; i < NR_HOST_SAVE_USER_MSRS; i++)
1303                 wrmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]);
1304 }
1305
1306 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1307 {
1308         struct vcpu_svm *svm = to_svm(vcpu);
1309         unsigned long rflags = svm->vmcb->save.rflags;
1310
1311         if (svm->nmi_singlestep) {
1312                 /* Hide our flags if they were not set by the guest */
1313                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1314                         rflags &= ~X86_EFLAGS_TF;
1315                 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1316                         rflags &= ~X86_EFLAGS_RF;
1317         }
1318         return rflags;
1319 }
1320
1321 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1322 {
1323         if (to_svm(vcpu)->nmi_singlestep)
1324                 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1325
1326        /*
1327         * Any change of EFLAGS.VM is accompanied by a reload of SS
1328         * (caused by either a task switch or an inter-privilege IRET),
1329         * so we do not need to update the CPL here.
1330         */
1331         to_svm(vcpu)->vmcb->save.rflags = rflags;
1332 }
1333
1334 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1335 {
1336         switch (reg) {
1337         case VCPU_EXREG_PDPTR:
1338                 BUG_ON(!npt_enabled);
1339                 load_pdptrs(vcpu, vcpu->arch.walk_mmu, kvm_read_cr3(vcpu));
1340                 break;
1341         default:
1342                 WARN_ON_ONCE(1);
1343         }
1344 }
1345
1346 static void svm_set_vintr(struct vcpu_svm *svm)
1347 {
1348         struct vmcb_control_area *control;
1349
1350         /* The following fields are ignored when AVIC is enabled */
1351         WARN_ON(kvm_vcpu_apicv_active(&svm->vcpu));
1352         set_intercept(svm, INTERCEPT_VINTR);
1353
1354         /*
1355          * This is just a dummy VINTR to actually cause a vmexit to happen.
1356          * Actual injection of virtual interrupts happens through EVENTINJ.
1357          */
1358         control = &svm->vmcb->control;
1359         control->int_vector = 0x0;
1360         control->int_ctl &= ~V_INTR_PRIO_MASK;
1361         control->int_ctl |= V_IRQ_MASK |
1362                 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1363         mark_dirty(svm->vmcb, VMCB_INTR);
1364 }
1365
1366 static void svm_clear_vintr(struct vcpu_svm *svm)
1367 {
1368         const u32 mask = V_TPR_MASK | V_GIF_ENABLE_MASK | V_GIF_MASK | V_INTR_MASKING_MASK;
1369         clr_intercept(svm, INTERCEPT_VINTR);
1370
1371         /* Drop int_ctl fields related to VINTR injection.  */
1372         svm->vmcb->control.int_ctl &= mask;
1373         if (is_guest_mode(&svm->vcpu)) {
1374                 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1375                         (svm->nested.ctl.int_ctl & V_TPR_MASK));
1376                 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl & ~mask;
1377         }
1378
1379         mark_dirty(svm->vmcb, VMCB_INTR);
1380 }
1381
1382 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1383 {
1384         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1385
1386         switch (seg) {
1387         case VCPU_SREG_CS: return &save->cs;
1388         case VCPU_SREG_DS: return &save->ds;
1389         case VCPU_SREG_ES: return &save->es;
1390         case VCPU_SREG_FS: return &save->fs;
1391         case VCPU_SREG_GS: return &save->gs;
1392         case VCPU_SREG_SS: return &save->ss;
1393         case VCPU_SREG_TR: return &save->tr;
1394         case VCPU_SREG_LDTR: return &save->ldtr;
1395         }
1396         BUG();
1397         return NULL;
1398 }
1399
1400 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1401 {
1402         struct vmcb_seg *s = svm_seg(vcpu, seg);
1403
1404         return s->base;
1405 }
1406
1407 static void svm_get_segment(struct kvm_vcpu *vcpu,
1408                             struct kvm_segment *var, int seg)
1409 {
1410         struct vmcb_seg *s = svm_seg(vcpu, seg);
1411
1412         var->base = s->base;
1413         var->limit = s->limit;
1414         var->selector = s->selector;
1415         var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1416         var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1417         var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1418         var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1419         var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1420         var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1421         var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1422
1423         /*
1424          * AMD CPUs circa 2014 track the G bit for all segments except CS.
1425          * However, the SVM spec states that the G bit is not observed by the
1426          * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1427          * So let's synthesize a legal G bit for all segments, this helps
1428          * running KVM nested. It also helps cross-vendor migration, because
1429          * Intel's vmentry has a check on the 'G' bit.
1430          */
1431         var->g = s->limit > 0xfffff;
1432
1433         /*
1434          * AMD's VMCB does not have an explicit unusable field, so emulate it
1435          * for cross vendor migration purposes by "not present"
1436          */
1437         var->unusable = !var->present;
1438
1439         switch (seg) {
1440         case VCPU_SREG_TR:
1441                 /*
1442                  * Work around a bug where the busy flag in the tr selector
1443                  * isn't exposed
1444                  */
1445                 var->type |= 0x2;
1446                 break;
1447         case VCPU_SREG_DS:
1448         case VCPU_SREG_ES:
1449         case VCPU_SREG_FS:
1450         case VCPU_SREG_GS:
1451                 /*
1452                  * The accessed bit must always be set in the segment
1453                  * descriptor cache, although it can be cleared in the
1454                  * descriptor, the cached bit always remains at 1. Since
1455                  * Intel has a check on this, set it here to support
1456                  * cross-vendor migration.
1457                  */
1458                 if (!var->unusable)
1459                         var->type |= 0x1;
1460                 break;
1461         case VCPU_SREG_SS:
1462                 /*
1463                  * On AMD CPUs sometimes the DB bit in the segment
1464                  * descriptor is left as 1, although the whole segment has
1465                  * been made unusable. Clear it here to pass an Intel VMX
1466                  * entry check when cross vendor migrating.
1467                  */
1468                 if (var->unusable)
1469                         var->db = 0;
1470                 /* This is symmetric with svm_set_segment() */
1471                 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1472                 break;
1473         }
1474 }
1475
1476 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1477 {
1478         struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1479
1480         return save->cpl;
1481 }
1482
1483 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1484 {
1485         struct vcpu_svm *svm = to_svm(vcpu);
1486
1487         dt->size = svm->vmcb->save.idtr.limit;
1488         dt->address = svm->vmcb->save.idtr.base;
1489 }
1490
1491 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1492 {
1493         struct vcpu_svm *svm = to_svm(vcpu);
1494
1495         svm->vmcb->save.idtr.limit = dt->size;
1496         svm->vmcb->save.idtr.base = dt->address ;
1497         mark_dirty(svm->vmcb, VMCB_DT);
1498 }
1499
1500 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1501 {
1502         struct vcpu_svm *svm = to_svm(vcpu);
1503
1504         dt->size = svm->vmcb->save.gdtr.limit;
1505         dt->address = svm->vmcb->save.gdtr.base;
1506 }
1507
1508 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1509 {
1510         struct vcpu_svm *svm = to_svm(vcpu);
1511
1512         svm->vmcb->save.gdtr.limit = dt->size;
1513         svm->vmcb->save.gdtr.base = dt->address ;
1514         mark_dirty(svm->vmcb, VMCB_DT);
1515 }
1516
1517 static void update_cr0_intercept(struct vcpu_svm *svm)
1518 {
1519         ulong gcr0 = svm->vcpu.arch.cr0;
1520         u64 *hcr0 = &svm->vmcb->save.cr0;
1521
1522         *hcr0 = (*hcr0 & ~SVM_CR0_SELECTIVE_MASK)
1523                 | (gcr0 & SVM_CR0_SELECTIVE_MASK);
1524
1525         mark_dirty(svm->vmcb, VMCB_CR);
1526
1527         if (gcr0 == *hcr0) {
1528                 clr_cr_intercept(svm, INTERCEPT_CR0_READ);
1529                 clr_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1530         } else {
1531                 set_cr_intercept(svm, INTERCEPT_CR0_READ);
1532                 set_cr_intercept(svm, INTERCEPT_CR0_WRITE);
1533         }
1534 }
1535
1536 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1537 {
1538         struct vcpu_svm *svm = to_svm(vcpu);
1539
1540 #ifdef CONFIG_X86_64
1541         if (vcpu->arch.efer & EFER_LME) {
1542                 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1543                         vcpu->arch.efer |= EFER_LMA;
1544                         svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1545                 }
1546
1547                 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1548                         vcpu->arch.efer &= ~EFER_LMA;
1549                         svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1550                 }
1551         }
1552 #endif
1553         vcpu->arch.cr0 = cr0;
1554
1555         if (!npt_enabled)
1556                 cr0 |= X86_CR0_PG | X86_CR0_WP;
1557
1558         /*
1559          * re-enable caching here because the QEMU bios
1560          * does not do it - this results in some delay at
1561          * reboot
1562          */
1563         if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1564                 cr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1565         svm->vmcb->save.cr0 = cr0;
1566         mark_dirty(svm->vmcb, VMCB_CR);
1567         update_cr0_intercept(svm);
1568 }
1569
1570 int svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1571 {
1572         unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1573         unsigned long old_cr4 = to_svm(vcpu)->vmcb->save.cr4;
1574
1575         if (cr4 & X86_CR4_VMXE)
1576                 return 1;
1577
1578         if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1579                 svm_flush_tlb(vcpu);
1580
1581         vcpu->arch.cr4 = cr4;
1582         if (!npt_enabled)
1583                 cr4 |= X86_CR4_PAE;
1584         cr4 |= host_cr4_mce;
1585         to_svm(vcpu)->vmcb->save.cr4 = cr4;
1586         mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1587         return 0;
1588 }
1589
1590 static void svm_set_segment(struct kvm_vcpu *vcpu,
1591                             struct kvm_segment *var, int seg)
1592 {
1593         struct vcpu_svm *svm = to_svm(vcpu);
1594         struct vmcb_seg *s = svm_seg(vcpu, seg);
1595
1596         s->base = var->base;
1597         s->limit = var->limit;
1598         s->selector = var->selector;
1599         s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1600         s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1601         s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1602         s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1603         s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1604         s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1605         s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1606         s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1607
1608         /*
1609          * This is always accurate, except if SYSRET returned to a segment
1610          * with SS.DPL != 3.  Intel does not have this quirk, and always
1611          * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1612          * would entail passing the CPL to userspace and back.
1613          */
1614         if (seg == VCPU_SREG_SS)
1615                 /* This is symmetric with svm_get_segment() */
1616                 svm->vmcb->save.cpl = (var->dpl & 3);
1617
1618         mark_dirty(svm->vmcb, VMCB_SEG);
1619 }
1620
1621 static void update_bp_intercept(struct kvm_vcpu *vcpu)
1622 {
1623         struct vcpu_svm *svm = to_svm(vcpu);
1624
1625         clr_exception_intercept(svm, BP_VECTOR);
1626
1627         if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1628                 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1629                         set_exception_intercept(svm, BP_VECTOR);
1630         } else
1631                 vcpu->guest_debug = 0;
1632 }
1633
1634 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1635 {
1636         if (sd->next_asid > sd->max_asid) {
1637                 ++sd->asid_generation;
1638                 sd->next_asid = sd->min_asid;
1639                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1640         }
1641
1642         svm->asid_generation = sd->asid_generation;
1643         svm->vmcb->control.asid = sd->next_asid++;
1644
1645         mark_dirty(svm->vmcb, VMCB_ASID);
1646 }
1647
1648 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1649 {
1650         struct vmcb *vmcb = svm->vmcb;
1651
1652         if (unlikely(value != vmcb->save.dr6)) {
1653                 vmcb->save.dr6 = value;
1654                 mark_dirty(vmcb, VMCB_DR);
1655         }
1656 }
1657
1658 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1659 {
1660         struct vcpu_svm *svm = to_svm(vcpu);
1661
1662         get_debugreg(vcpu->arch.db[0], 0);
1663         get_debugreg(vcpu->arch.db[1], 1);
1664         get_debugreg(vcpu->arch.db[2], 2);
1665         get_debugreg(vcpu->arch.db[3], 3);
1666         /*
1667          * We cannot reset svm->vmcb->save.dr6 to DR6_FIXED_1|DR6_RTM here,
1668          * because db_interception might need it.  We can do it before vmentry.
1669          */
1670         vcpu->arch.dr6 = svm->vmcb->save.dr6;
1671         vcpu->arch.dr7 = svm->vmcb->save.dr7;
1672         vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1673         set_dr_intercepts(svm);
1674 }
1675
1676 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1677 {
1678         struct vcpu_svm *svm = to_svm(vcpu);
1679
1680         svm->vmcb->save.dr7 = value;
1681         mark_dirty(svm->vmcb, VMCB_DR);
1682 }
1683
1684 static int pf_interception(struct vcpu_svm *svm)
1685 {
1686         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1687         u64 error_code = svm->vmcb->control.exit_info_1;
1688
1689         return kvm_handle_page_fault(&svm->vcpu, error_code, fault_address,
1690                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1691                         svm->vmcb->control.insn_bytes : NULL,
1692                         svm->vmcb->control.insn_len);
1693 }
1694
1695 static int npf_interception(struct vcpu_svm *svm)
1696 {
1697         u64 fault_address = __sme_clr(svm->vmcb->control.exit_info_2);
1698         u64 error_code = svm->vmcb->control.exit_info_1;
1699
1700         trace_kvm_page_fault(fault_address, error_code);
1701         return kvm_mmu_page_fault(&svm->vcpu, fault_address, error_code,
1702                         static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1703                         svm->vmcb->control.insn_bytes : NULL,
1704                         svm->vmcb->control.insn_len);
1705 }
1706
1707 static int db_interception(struct vcpu_svm *svm)
1708 {
1709         struct kvm_run *kvm_run = svm->vcpu.run;
1710         struct kvm_vcpu *vcpu = &svm->vcpu;
1711
1712         if (!(svm->vcpu.guest_debug &
1713               (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1714                 !svm->nmi_singlestep) {
1715                 u32 payload = (svm->vmcb->save.dr6 ^ DR6_RTM) & ~DR6_FIXED_1;
1716                 kvm_queue_exception_p(&svm->vcpu, DB_VECTOR, payload);
1717                 return 1;
1718         }
1719
1720         if (svm->nmi_singlestep) {
1721                 disable_nmi_singlestep(svm);
1722                 /* Make sure we check for pending NMIs upon entry */
1723                 kvm_make_request(KVM_REQ_EVENT, vcpu);
1724         }
1725
1726         if (svm->vcpu.guest_debug &
1727             (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
1728                 kvm_run->exit_reason = KVM_EXIT_DEBUG;
1729                 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
1730                 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
1731                 kvm_run->debug.arch.pc =
1732                         svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1733                 kvm_run->debug.arch.exception = DB_VECTOR;
1734                 return 0;
1735         }
1736
1737         return 1;
1738 }
1739
1740 static int bp_interception(struct vcpu_svm *svm)
1741 {
1742         struct kvm_run *kvm_run = svm->vcpu.run;
1743
1744         kvm_run->exit_reason = KVM_EXIT_DEBUG;
1745         kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
1746         kvm_run->debug.arch.exception = BP_VECTOR;
1747         return 0;
1748 }
1749
1750 static int ud_interception(struct vcpu_svm *svm)
1751 {
1752         return handle_ud(&svm->vcpu);
1753 }
1754
1755 static int ac_interception(struct vcpu_svm *svm)
1756 {
1757         kvm_queue_exception_e(&svm->vcpu, AC_VECTOR, 0);
1758         return 1;
1759 }
1760
1761 static int gp_interception(struct vcpu_svm *svm)
1762 {
1763         struct kvm_vcpu *vcpu = &svm->vcpu;
1764         u32 error_code = svm->vmcb->control.exit_info_1;
1765
1766         WARN_ON_ONCE(!enable_vmware_backdoor);
1767
1768         /*
1769          * VMware backdoor emulation on #GP interception only handles IN{S},
1770          * OUT{S}, and RDPMC, none of which generate a non-zero error code.
1771          */
1772         if (error_code) {
1773                 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
1774                 return 1;
1775         }
1776         return kvm_emulate_instruction(vcpu, EMULTYPE_VMWARE_GP);
1777 }
1778
1779 static bool is_erratum_383(void)
1780 {
1781         int err, i;
1782         u64 value;
1783
1784         if (!erratum_383_found)
1785                 return false;
1786
1787         value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
1788         if (err)
1789                 return false;
1790
1791         /* Bit 62 may or may not be set for this mce */
1792         value &= ~(1ULL << 62);
1793
1794         if (value != 0xb600000000010015ULL)
1795                 return false;
1796
1797         /* Clear MCi_STATUS registers */
1798         for (i = 0; i < 6; ++i)
1799                 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
1800
1801         value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
1802         if (!err) {
1803                 u32 low, high;
1804
1805                 value &= ~(1ULL << 2);
1806                 low    = lower_32_bits(value);
1807                 high   = upper_32_bits(value);
1808
1809                 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
1810         }
1811
1812         /* Flush tlb to evict multi-match entries */
1813         __flush_tlb_all();
1814
1815         return true;
1816 }
1817
1818 /*
1819  * Trigger machine check on the host. We assume all the MSRs are already set up
1820  * by the CPU and that we still run on the same CPU as the MCE occurred on.
1821  * We pass a fake environment to the machine check handler because we want
1822  * the guest to be always treated like user space, no matter what context
1823  * it used internally.
1824  */
1825 static void kvm_machine_check(void)
1826 {
1827 #if defined(CONFIG_X86_MCE)
1828         struct pt_regs regs = {
1829                 .cs = 3, /* Fake ring 3 no matter what the guest ran on */
1830                 .flags = X86_EFLAGS_IF,
1831         };
1832
1833         do_machine_check(&regs, 0);
1834 #endif
1835 }
1836
1837 static void svm_handle_mce(struct vcpu_svm *svm)
1838 {
1839         if (is_erratum_383()) {
1840                 /*
1841                  * Erratum 383 triggered. Guest state is corrupt so kill the
1842                  * guest.
1843                  */
1844                 pr_err("KVM: Guest triggered AMD Erratum 383\n");
1845
1846                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, &svm->vcpu);
1847
1848                 return;
1849         }
1850
1851         /*
1852          * On an #MC intercept the MCE handler is not called automatically in
1853          * the host. So do it by hand here.
1854          */
1855         kvm_machine_check();
1856 }
1857
1858 static int mc_interception(struct vcpu_svm *svm)
1859 {
1860         return 1;
1861 }
1862
1863 static int shutdown_interception(struct vcpu_svm *svm)
1864 {
1865         struct kvm_run *kvm_run = svm->vcpu.run;
1866
1867         /*
1868          * VMCB is undefined after a SHUTDOWN intercept
1869          * so reinitialize it.
1870          */
1871         clear_page(svm->vmcb);
1872         init_vmcb(svm);
1873
1874         kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
1875         return 0;
1876 }
1877
1878 static int io_interception(struct vcpu_svm *svm)
1879 {
1880         struct kvm_vcpu *vcpu = &svm->vcpu;
1881         u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
1882         int size, in, string;
1883         unsigned port;
1884
1885         ++svm->vcpu.stat.io_exits;
1886         string = (io_info & SVM_IOIO_STR_MASK) != 0;
1887         in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
1888         if (string)
1889                 return kvm_emulate_instruction(vcpu, 0);
1890
1891         port = io_info >> 16;
1892         size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
1893         svm->next_rip = svm->vmcb->control.exit_info_2;
1894
1895         return kvm_fast_pio(&svm->vcpu, size, port, in);
1896 }
1897
1898 static int nmi_interception(struct vcpu_svm *svm)
1899 {
1900         return 1;
1901 }
1902
1903 static int intr_interception(struct vcpu_svm *svm)
1904 {
1905         ++svm->vcpu.stat.irq_exits;
1906         return 1;
1907 }
1908
1909 static int nop_on_interception(struct vcpu_svm *svm)
1910 {
1911         return 1;
1912 }
1913
1914 static int halt_interception(struct vcpu_svm *svm)
1915 {
1916         return kvm_emulate_halt(&svm->vcpu);
1917 }
1918
1919 static int vmmcall_interception(struct vcpu_svm *svm)
1920 {
1921         return kvm_emulate_hypercall(&svm->vcpu);
1922 }
1923
1924 static int vmload_interception(struct vcpu_svm *svm)
1925 {
1926         struct vmcb *nested_vmcb;
1927         struct kvm_host_map map;
1928         int ret;
1929
1930         if (nested_svm_check_permissions(svm))
1931                 return 1;
1932
1933         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1934         if (ret) {
1935                 if (ret == -EINVAL)
1936                         kvm_inject_gp(&svm->vcpu, 0);
1937                 return 1;
1938         }
1939
1940         nested_vmcb = map.hva;
1941
1942         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1943
1944         nested_svm_vmloadsave(nested_vmcb, svm->vmcb);
1945         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1946
1947         return ret;
1948 }
1949
1950 static int vmsave_interception(struct vcpu_svm *svm)
1951 {
1952         struct vmcb *nested_vmcb;
1953         struct kvm_host_map map;
1954         int ret;
1955
1956         if (nested_svm_check_permissions(svm))
1957                 return 1;
1958
1959         ret = kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
1960         if (ret) {
1961                 if (ret == -EINVAL)
1962                         kvm_inject_gp(&svm->vcpu, 0);
1963                 return 1;
1964         }
1965
1966         nested_vmcb = map.hva;
1967
1968         ret = kvm_skip_emulated_instruction(&svm->vcpu);
1969
1970         nested_svm_vmloadsave(svm->vmcb, nested_vmcb);
1971         kvm_vcpu_unmap(&svm->vcpu, &map, true);
1972
1973         return ret;
1974 }
1975
1976 static int vmrun_interception(struct vcpu_svm *svm)
1977 {
1978         if (nested_svm_check_permissions(svm))
1979                 return 1;
1980
1981         return nested_svm_vmrun(svm);
1982 }
1983
1984 void svm_set_gif(struct vcpu_svm *svm, bool value)
1985 {
1986         if (value) {
1987                 /*
1988                  * If VGIF is enabled, the STGI intercept is only added to
1989                  * detect the opening of the SMI/NMI window; remove it now.
1990                  * Likewise, clear the VINTR intercept, we will set it
1991                  * again while processing KVM_REQ_EVENT if needed.
1992                  */
1993                 if (vgif_enabled(svm))
1994                         clr_intercept(svm, INTERCEPT_STGI);
1995                 if (is_intercept(svm, SVM_EXIT_VINTR))
1996                         svm_clear_vintr(svm);
1997
1998                 enable_gif(svm);
1999                 if (svm->vcpu.arch.smi_pending ||
2000                     svm->vcpu.arch.nmi_pending ||
2001                     kvm_cpu_has_injectable_intr(&svm->vcpu))
2002                         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2003         } else {
2004                 disable_gif(svm);
2005
2006                 /*
2007                  * After a CLGI no interrupts should come.  But if vGIF is
2008                  * in use, we still rely on the VINTR intercept (rather than
2009                  * STGI) to detect an open interrupt window.
2010                 */
2011                 if (!vgif_enabled(svm))
2012                         svm_clear_vintr(svm);
2013         }
2014 }
2015
2016 static int stgi_interception(struct vcpu_svm *svm)
2017 {
2018         int ret;
2019
2020         if (nested_svm_check_permissions(svm))
2021                 return 1;
2022
2023         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2024         svm_set_gif(svm, true);
2025         return ret;
2026 }
2027
2028 static int clgi_interception(struct vcpu_svm *svm)
2029 {
2030         int ret;
2031
2032         if (nested_svm_check_permissions(svm))
2033                 return 1;
2034
2035         ret = kvm_skip_emulated_instruction(&svm->vcpu);
2036         svm_set_gif(svm, false);
2037         return ret;
2038 }
2039
2040 static int invlpga_interception(struct vcpu_svm *svm)
2041 {
2042         struct kvm_vcpu *vcpu = &svm->vcpu;
2043
2044         trace_kvm_invlpga(svm->vmcb->save.rip, kvm_rcx_read(&svm->vcpu),
2045                           kvm_rax_read(&svm->vcpu));
2046
2047         /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2048         kvm_mmu_invlpg(vcpu, kvm_rax_read(&svm->vcpu));
2049
2050         return kvm_skip_emulated_instruction(&svm->vcpu);
2051 }
2052
2053 static int skinit_interception(struct vcpu_svm *svm)
2054 {
2055         trace_kvm_skinit(svm->vmcb->save.rip, kvm_rax_read(&svm->vcpu));
2056
2057         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2058         return 1;
2059 }
2060
2061 static int wbinvd_interception(struct vcpu_svm *svm)
2062 {
2063         return kvm_emulate_wbinvd(&svm->vcpu);
2064 }
2065
2066 static int xsetbv_interception(struct vcpu_svm *svm)
2067 {
2068         u64 new_bv = kvm_read_edx_eax(&svm->vcpu);
2069         u32 index = kvm_rcx_read(&svm->vcpu);
2070
2071         if (kvm_set_xcr(&svm->vcpu, index, new_bv) == 0) {
2072                 return kvm_skip_emulated_instruction(&svm->vcpu);
2073         }
2074
2075         return 1;
2076 }
2077
2078 static int rdpru_interception(struct vcpu_svm *svm)
2079 {
2080         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2081         return 1;
2082 }
2083
2084 static int task_switch_interception(struct vcpu_svm *svm)
2085 {
2086         u16 tss_selector;
2087         int reason;
2088         int int_type = svm->vmcb->control.exit_int_info &
2089                 SVM_EXITINTINFO_TYPE_MASK;
2090         int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2091         uint32_t type =
2092                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2093         uint32_t idt_v =
2094                 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2095         bool has_error_code = false;
2096         u32 error_code = 0;
2097
2098         tss_selector = (u16)svm->vmcb->control.exit_info_1;
2099
2100         if (svm->vmcb->control.exit_info_2 &
2101             (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2102                 reason = TASK_SWITCH_IRET;
2103         else if (svm->vmcb->control.exit_info_2 &
2104                  (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2105                 reason = TASK_SWITCH_JMP;
2106         else if (idt_v)
2107                 reason = TASK_SWITCH_GATE;
2108         else
2109                 reason = TASK_SWITCH_CALL;
2110
2111         if (reason == TASK_SWITCH_GATE) {
2112                 switch (type) {
2113                 case SVM_EXITINTINFO_TYPE_NMI:
2114                         svm->vcpu.arch.nmi_injected = false;
2115                         break;
2116                 case SVM_EXITINTINFO_TYPE_EXEPT:
2117                         if (svm->vmcb->control.exit_info_2 &
2118                             (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2119                                 has_error_code = true;
2120                                 error_code =
2121                                         (u32)svm->vmcb->control.exit_info_2;
2122                         }
2123                         kvm_clear_exception_queue(&svm->vcpu);
2124                         break;
2125                 case SVM_EXITINTINFO_TYPE_INTR:
2126                         kvm_clear_interrupt_queue(&svm->vcpu);
2127                         break;
2128                 default:
2129                         break;
2130                 }
2131         }
2132
2133         if (reason != TASK_SWITCH_GATE ||
2134             int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2135             (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2136              (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2137                 if (!skip_emulated_instruction(&svm->vcpu))
2138                         return 0;
2139         }
2140
2141         if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2142                 int_vec = -1;
2143
2144         return kvm_task_switch(&svm->vcpu, tss_selector, int_vec, reason,
2145                                has_error_code, error_code);
2146 }
2147
2148 static int cpuid_interception(struct vcpu_svm *svm)
2149 {
2150         return kvm_emulate_cpuid(&svm->vcpu);
2151 }
2152
2153 static int iret_interception(struct vcpu_svm *svm)
2154 {
2155         ++svm->vcpu.stat.nmi_window_exits;
2156         clr_intercept(svm, INTERCEPT_IRET);
2157         svm->vcpu.arch.hflags |= HF_IRET_MASK;
2158         svm->nmi_iret_rip = kvm_rip_read(&svm->vcpu);
2159         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2160         return 1;
2161 }
2162
2163 static int invlpg_interception(struct vcpu_svm *svm)
2164 {
2165         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2166                 return kvm_emulate_instruction(&svm->vcpu, 0);
2167
2168         kvm_mmu_invlpg(&svm->vcpu, svm->vmcb->control.exit_info_1);
2169         return kvm_skip_emulated_instruction(&svm->vcpu);
2170 }
2171
2172 static int emulate_on_interception(struct vcpu_svm *svm)
2173 {
2174         return kvm_emulate_instruction(&svm->vcpu, 0);
2175 }
2176
2177 static int rsm_interception(struct vcpu_svm *svm)
2178 {
2179         return kvm_emulate_instruction_from_buffer(&svm->vcpu, rsm_ins_bytes, 2);
2180 }
2181
2182 static int rdpmc_interception(struct vcpu_svm *svm)
2183 {
2184         int err;
2185
2186         if (!nrips)
2187                 return emulate_on_interception(svm);
2188
2189         err = kvm_rdpmc(&svm->vcpu);
2190         return kvm_complete_insn_gp(&svm->vcpu, err);
2191 }
2192
2193 static bool check_selective_cr0_intercepted(struct vcpu_svm *svm,
2194                                             unsigned long val)
2195 {
2196         unsigned long cr0 = svm->vcpu.arch.cr0;
2197         bool ret = false;
2198         u64 intercept;
2199
2200         intercept = svm->nested.ctl.intercept;
2201
2202         if (!is_guest_mode(&svm->vcpu) ||
2203             (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0))))
2204                 return false;
2205
2206         cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2207         val &= ~SVM_CR0_SELECTIVE_MASK;
2208
2209         if (cr0 ^ val) {
2210                 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2211                 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2212         }
2213
2214         return ret;
2215 }
2216
2217 #define CR_VALID (1ULL << 63)
2218
2219 static int cr_interception(struct vcpu_svm *svm)
2220 {
2221         int reg, cr;
2222         unsigned long val;
2223         int err;
2224
2225         if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2226                 return emulate_on_interception(svm);
2227
2228         if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2229                 return emulate_on_interception(svm);
2230
2231         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2232         if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2233                 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2234         else
2235                 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2236
2237         err = 0;
2238         if (cr >= 16) { /* mov to cr */
2239                 cr -= 16;
2240                 val = kvm_register_read(&svm->vcpu, reg);
2241                 switch (cr) {
2242                 case 0:
2243                         if (!check_selective_cr0_intercepted(svm, val))
2244                                 err = kvm_set_cr0(&svm->vcpu, val);
2245                         else
2246                                 return 1;
2247
2248                         break;
2249                 case 3:
2250                         err = kvm_set_cr3(&svm->vcpu, val);
2251                         break;
2252                 case 4:
2253                         err = kvm_set_cr4(&svm->vcpu, val);
2254                         break;
2255                 case 8:
2256                         err = kvm_set_cr8(&svm->vcpu, val);
2257                         break;
2258                 default:
2259                         WARN(1, "unhandled write to CR%d", cr);
2260                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2261                         return 1;
2262                 }
2263         } else { /* mov from cr */
2264                 switch (cr) {
2265                 case 0:
2266                         val = kvm_read_cr0(&svm->vcpu);
2267                         break;
2268                 case 2:
2269                         val = svm->vcpu.arch.cr2;
2270                         break;
2271                 case 3:
2272                         val = kvm_read_cr3(&svm->vcpu);
2273                         break;
2274                 case 4:
2275                         val = kvm_read_cr4(&svm->vcpu);
2276                         break;
2277                 case 8:
2278                         val = kvm_get_cr8(&svm->vcpu);
2279                         break;
2280                 default:
2281                         WARN(1, "unhandled read from CR%d", cr);
2282                         kvm_queue_exception(&svm->vcpu, UD_VECTOR);
2283                         return 1;
2284                 }
2285                 kvm_register_write(&svm->vcpu, reg, val);
2286         }
2287         return kvm_complete_insn_gp(&svm->vcpu, err);
2288 }
2289
2290 static int dr_interception(struct vcpu_svm *svm)
2291 {
2292         int reg, dr;
2293         unsigned long val;
2294
2295         if (svm->vcpu.guest_debug == 0) {
2296                 /*
2297                  * No more DR vmexits; force a reload of the debug registers
2298                  * and reenter on this instruction.  The next vmexit will
2299                  * retrieve the full state of the debug registers.
2300                  */
2301                 clr_dr_intercepts(svm);
2302                 svm->vcpu.arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2303                 return 1;
2304         }
2305
2306         if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2307                 return emulate_on_interception(svm);
2308
2309         reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2310         dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2311
2312         if (dr >= 16) { /* mov to DRn */
2313                 if (!kvm_require_dr(&svm->vcpu, dr - 16))
2314                         return 1;
2315                 val = kvm_register_read(&svm->vcpu, reg);
2316                 kvm_set_dr(&svm->vcpu, dr - 16, val);
2317         } else {
2318                 if (!kvm_require_dr(&svm->vcpu, dr))
2319                         return 1;
2320                 kvm_get_dr(&svm->vcpu, dr, &val);
2321                 kvm_register_write(&svm->vcpu, reg, val);
2322         }
2323
2324         return kvm_skip_emulated_instruction(&svm->vcpu);
2325 }
2326
2327 static int cr8_write_interception(struct vcpu_svm *svm)
2328 {
2329         struct kvm_run *kvm_run = svm->vcpu.run;
2330         int r;
2331
2332         u8 cr8_prev = kvm_get_cr8(&svm->vcpu);
2333         /* instruction emulation calls kvm_set_cr8() */
2334         r = cr_interception(svm);
2335         if (lapic_in_kernel(&svm->vcpu))
2336                 return r;
2337         if (cr8_prev <= kvm_get_cr8(&svm->vcpu))
2338                 return r;
2339         kvm_run->exit_reason = KVM_EXIT_SET_TPR;
2340         return 0;
2341 }
2342
2343 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2344 {
2345         msr->data = 0;
2346
2347         switch (msr->index) {
2348         case MSR_F10H_DECFG:
2349                 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2350                         msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2351                 break;
2352         default:
2353                 return 1;
2354         }
2355
2356         return 0;
2357 }
2358
2359 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2360 {
2361         struct vcpu_svm *svm = to_svm(vcpu);
2362
2363         switch (msr_info->index) {
2364         case MSR_STAR:
2365                 msr_info->data = svm->vmcb->save.star;
2366                 break;
2367 #ifdef CONFIG_X86_64
2368         case MSR_LSTAR:
2369                 msr_info->data = svm->vmcb->save.lstar;
2370                 break;
2371         case MSR_CSTAR:
2372                 msr_info->data = svm->vmcb->save.cstar;
2373                 break;
2374         case MSR_KERNEL_GS_BASE:
2375                 msr_info->data = svm->vmcb->save.kernel_gs_base;
2376                 break;
2377         case MSR_SYSCALL_MASK:
2378                 msr_info->data = svm->vmcb->save.sfmask;
2379                 break;
2380 #endif
2381         case MSR_IA32_SYSENTER_CS:
2382                 msr_info->data = svm->vmcb->save.sysenter_cs;
2383                 break;
2384         case MSR_IA32_SYSENTER_EIP:
2385                 msr_info->data = svm->sysenter_eip;
2386                 break;
2387         case MSR_IA32_SYSENTER_ESP:
2388                 msr_info->data = svm->sysenter_esp;
2389                 break;
2390         case MSR_TSC_AUX:
2391                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2392                         return 1;
2393                 msr_info->data = svm->tsc_aux;
2394                 break;
2395         /*
2396          * Nobody will change the following 5 values in the VMCB so we can
2397          * safely return them on rdmsr. They will always be 0 until LBRV is
2398          * implemented.
2399          */
2400         case MSR_IA32_DEBUGCTLMSR:
2401                 msr_info->data = svm->vmcb->save.dbgctl;
2402                 break;
2403         case MSR_IA32_LASTBRANCHFROMIP:
2404                 msr_info->data = svm->vmcb->save.br_from;
2405                 break;
2406         case MSR_IA32_LASTBRANCHTOIP:
2407                 msr_info->data = svm->vmcb->save.br_to;
2408                 break;
2409         case MSR_IA32_LASTINTFROMIP:
2410                 msr_info->data = svm->vmcb->save.last_excp_from;
2411                 break;
2412         case MSR_IA32_LASTINTTOIP:
2413                 msr_info->data = svm->vmcb->save.last_excp_to;
2414                 break;
2415         case MSR_VM_HSAVE_PA:
2416                 msr_info->data = svm->nested.hsave_msr;
2417                 break;
2418         case MSR_VM_CR:
2419                 msr_info->data = svm->nested.vm_cr_msr;
2420                 break;
2421         case MSR_IA32_SPEC_CTRL:
2422                 if (!msr_info->host_initiated &&
2423                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2424                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2425                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2426                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2427                         return 1;
2428
2429                 msr_info->data = svm->spec_ctrl;
2430                 break;
2431         case MSR_AMD64_VIRT_SPEC_CTRL:
2432                 if (!msr_info->host_initiated &&
2433                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2434                         return 1;
2435
2436                 msr_info->data = svm->virt_spec_ctrl;
2437                 break;
2438         case MSR_F15H_IC_CFG: {
2439
2440                 int family, model;
2441
2442                 family = guest_cpuid_family(vcpu);
2443                 model  = guest_cpuid_model(vcpu);
2444
2445                 if (family < 0 || model < 0)
2446                         return kvm_get_msr_common(vcpu, msr_info);
2447
2448                 msr_info->data = 0;
2449
2450                 if (family == 0x15 &&
2451                     (model >= 0x2 && model < 0x20))
2452                         msr_info->data = 0x1E;
2453                 }
2454                 break;
2455         case MSR_F10H_DECFG:
2456                 msr_info->data = svm->msr_decfg;
2457                 break;
2458         default:
2459                 return kvm_get_msr_common(vcpu, msr_info);
2460         }
2461         return 0;
2462 }
2463
2464 static int rdmsr_interception(struct vcpu_svm *svm)
2465 {
2466         return kvm_emulate_rdmsr(&svm->vcpu);
2467 }
2468
2469 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2470 {
2471         struct vcpu_svm *svm = to_svm(vcpu);
2472         int svm_dis, chg_mask;
2473
2474         if (data & ~SVM_VM_CR_VALID_MASK)
2475                 return 1;
2476
2477         chg_mask = SVM_VM_CR_VALID_MASK;
2478
2479         if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2480                 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2481
2482         svm->nested.vm_cr_msr &= ~chg_mask;
2483         svm->nested.vm_cr_msr |= (data & chg_mask);
2484
2485         svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2486
2487         /* check for svm_disable while efer.svme is set */
2488         if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2489                 return 1;
2490
2491         return 0;
2492 }
2493
2494 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2495 {
2496         struct vcpu_svm *svm = to_svm(vcpu);
2497
2498         u32 ecx = msr->index;
2499         u64 data = msr->data;
2500         switch (ecx) {
2501         case MSR_IA32_CR_PAT:
2502                 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2503                         return 1;
2504                 vcpu->arch.pat = data;
2505                 svm->vmcb->save.g_pat = data;
2506                 mark_dirty(svm->vmcb, VMCB_NPT);
2507                 break;
2508         case MSR_IA32_SPEC_CTRL:
2509                 if (!msr->host_initiated &&
2510                     !guest_cpuid_has(vcpu, X86_FEATURE_SPEC_CTRL) &&
2511                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_STIBP) &&
2512                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBRS) &&
2513                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_SSBD))
2514                         return 1;
2515
2516                 if (data & ~kvm_spec_ctrl_valid_bits(vcpu))
2517                         return 1;
2518
2519                 svm->spec_ctrl = data;
2520                 if (!data)
2521                         break;
2522
2523                 /*
2524                  * For non-nested:
2525                  * When it's written (to non-zero) for the first time, pass
2526                  * it through.
2527                  *
2528                  * For nested:
2529                  * The handling of the MSR bitmap for L2 guests is done in
2530                  * nested_svm_vmrun_msrpm.
2531                  * We update the L1 MSR bit as well since it will end up
2532                  * touching the MSR anyway now.
2533                  */
2534                 set_msr_interception(svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2535                 break;
2536         case MSR_IA32_PRED_CMD:
2537                 if (!msr->host_initiated &&
2538                     !guest_cpuid_has(vcpu, X86_FEATURE_AMD_IBPB))
2539                         return 1;
2540
2541                 if (data & ~PRED_CMD_IBPB)
2542                         return 1;
2543                 if (!boot_cpu_has(X86_FEATURE_AMD_IBPB))
2544                         return 1;
2545                 if (!data)
2546                         break;
2547
2548                 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2549                 set_msr_interception(svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2550                 break;
2551         case MSR_AMD64_VIRT_SPEC_CTRL:
2552                 if (!msr->host_initiated &&
2553                     !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2554                         return 1;
2555
2556                 if (data & ~SPEC_CTRL_SSBD)
2557                         return 1;
2558
2559                 svm->virt_spec_ctrl = data;
2560                 break;
2561         case MSR_STAR:
2562                 svm->vmcb->save.star = data;
2563                 break;
2564 #ifdef CONFIG_X86_64
2565         case MSR_LSTAR:
2566                 svm->vmcb->save.lstar = data;
2567                 break;
2568         case MSR_CSTAR:
2569                 svm->vmcb->save.cstar = data;
2570                 break;
2571         case MSR_KERNEL_GS_BASE:
2572                 svm->vmcb->save.kernel_gs_base = data;
2573                 break;
2574         case MSR_SYSCALL_MASK:
2575                 svm->vmcb->save.sfmask = data;
2576                 break;
2577 #endif
2578         case MSR_IA32_SYSENTER_CS:
2579                 svm->vmcb->save.sysenter_cs = data;
2580                 break;
2581         case MSR_IA32_SYSENTER_EIP:
2582                 svm->sysenter_eip = data;
2583                 svm->vmcb->save.sysenter_eip = data;
2584                 break;
2585         case MSR_IA32_SYSENTER_ESP:
2586                 svm->sysenter_esp = data;
2587                 svm->vmcb->save.sysenter_esp = data;
2588                 break;
2589         case MSR_TSC_AUX:
2590                 if (!boot_cpu_has(X86_FEATURE_RDTSCP))
2591                         return 1;
2592
2593                 /*
2594                  * This is rare, so we update the MSR here instead of using
2595                  * direct_access_msrs.  Doing that would require a rdmsr in
2596                  * svm_vcpu_put.
2597                  */
2598                 svm->tsc_aux = data;
2599                 wrmsrl(MSR_TSC_AUX, svm->tsc_aux);
2600                 break;
2601         case MSR_IA32_DEBUGCTLMSR:
2602                 if (!boot_cpu_has(X86_FEATURE_LBRV)) {
2603                         vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
2604                                     __func__, data);
2605                         break;
2606                 }
2607                 if (data & DEBUGCTL_RESERVED_BITS)
2608                         return 1;
2609
2610                 svm->vmcb->save.dbgctl = data;
2611                 mark_dirty(svm->vmcb, VMCB_LBR);
2612                 if (data & (1ULL<<0))
2613                         svm_enable_lbrv(svm);
2614                 else
2615                         svm_disable_lbrv(svm);
2616                 break;
2617         case MSR_VM_HSAVE_PA:
2618                 svm->nested.hsave_msr = data;
2619                 break;
2620         case MSR_VM_CR:
2621                 return svm_set_vm_cr(vcpu, data);
2622         case MSR_VM_IGNNE:
2623                 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
2624                 break;
2625         case MSR_F10H_DECFG: {
2626                 struct kvm_msr_entry msr_entry;
2627
2628                 msr_entry.index = msr->index;
2629                 if (svm_get_msr_feature(&msr_entry))
2630                         return 1;
2631
2632                 /* Check the supported bits */
2633                 if (data & ~msr_entry.data)
2634                         return 1;
2635
2636                 /* Don't allow the guest to change a bit, #GP */
2637                 if (!msr->host_initiated && (data ^ msr_entry.data))
2638                         return 1;
2639
2640                 svm->msr_decfg = data;
2641                 break;
2642         }
2643         case MSR_IA32_APICBASE:
2644                 if (kvm_vcpu_apicv_active(vcpu))
2645                         avic_update_vapic_bar(to_svm(vcpu), data);
2646                 /* Fall through */
2647         default:
2648                 return kvm_set_msr_common(vcpu, msr);
2649         }
2650         return 0;
2651 }
2652
2653 static int wrmsr_interception(struct vcpu_svm *svm)
2654 {
2655         return kvm_emulate_wrmsr(&svm->vcpu);
2656 }
2657
2658 static int msr_interception(struct vcpu_svm *svm)
2659 {
2660         if (svm->vmcb->control.exit_info_1)
2661                 return wrmsr_interception(svm);
2662         else
2663                 return rdmsr_interception(svm);
2664 }
2665
2666 static int interrupt_window_interception(struct vcpu_svm *svm)
2667 {
2668         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2669         svm_clear_vintr(svm);
2670
2671         /*
2672          * For AVIC, the only reason to end up here is ExtINTs.
2673          * In this case AVIC was temporarily disabled for
2674          * requesting the IRQ window and we have to re-enable it.
2675          */
2676         svm_toggle_avic_for_irq_window(&svm->vcpu, true);
2677
2678         ++svm->vcpu.stat.irq_window_exits;
2679         return 1;
2680 }
2681
2682 static int pause_interception(struct vcpu_svm *svm)
2683 {
2684         struct kvm_vcpu *vcpu = &svm->vcpu;
2685         bool in_kernel = (svm_get_cpl(vcpu) == 0);
2686
2687         if (pause_filter_thresh)
2688                 grow_ple_window(vcpu);
2689
2690         kvm_vcpu_on_spin(vcpu, in_kernel);
2691         return 1;
2692 }
2693
2694 static int nop_interception(struct vcpu_svm *svm)
2695 {
2696         return kvm_skip_emulated_instruction(&(svm->vcpu));
2697 }
2698
2699 static int monitor_interception(struct vcpu_svm *svm)
2700 {
2701         printk_once(KERN_WARNING "kvm: MONITOR instruction emulated as NOP!\n");
2702         return nop_interception(svm);
2703 }
2704
2705 static int mwait_interception(struct vcpu_svm *svm)
2706 {
2707         printk_once(KERN_WARNING "kvm: MWAIT instruction emulated as NOP!\n");
2708         return nop_interception(svm);
2709 }
2710
2711 static int (*const svm_exit_handlers[])(struct vcpu_svm *svm) = {
2712         [SVM_EXIT_READ_CR0]                     = cr_interception,
2713         [SVM_EXIT_READ_CR3]                     = cr_interception,
2714         [SVM_EXIT_READ_CR4]                     = cr_interception,
2715         [SVM_EXIT_READ_CR8]                     = cr_interception,
2716         [SVM_EXIT_CR0_SEL_WRITE]                = cr_interception,
2717         [SVM_EXIT_WRITE_CR0]                    = cr_interception,
2718         [SVM_EXIT_WRITE_CR3]                    = cr_interception,
2719         [SVM_EXIT_WRITE_CR4]                    = cr_interception,
2720         [SVM_EXIT_WRITE_CR8]                    = cr8_write_interception,
2721         [SVM_EXIT_READ_DR0]                     = dr_interception,
2722         [SVM_EXIT_READ_DR1]                     = dr_interception,
2723         [SVM_EXIT_READ_DR2]                     = dr_interception,
2724         [SVM_EXIT_READ_DR3]                     = dr_interception,
2725         [SVM_EXIT_READ_DR4]                     = dr_interception,
2726         [SVM_EXIT_READ_DR5]                     = dr_interception,
2727         [SVM_EXIT_READ_DR6]                     = dr_interception,
2728         [SVM_EXIT_READ_DR7]                     = dr_interception,
2729         [SVM_EXIT_WRITE_DR0]                    = dr_interception,
2730         [SVM_EXIT_WRITE_DR1]                    = dr_interception,
2731         [SVM_EXIT_WRITE_DR2]                    = dr_interception,
2732         [SVM_EXIT_WRITE_DR3]                    = dr_interception,
2733         [SVM_EXIT_WRITE_DR4]                    = dr_interception,
2734         [SVM_EXIT_WRITE_DR5]                    = dr_interception,
2735         [SVM_EXIT_WRITE_DR6]                    = dr_interception,
2736         [SVM_EXIT_WRITE_DR7]                    = dr_interception,
2737         [SVM_EXIT_EXCP_BASE + DB_VECTOR]        = db_interception,
2738         [SVM_EXIT_EXCP_BASE + BP_VECTOR]        = bp_interception,
2739         [SVM_EXIT_EXCP_BASE + UD_VECTOR]        = ud_interception,
2740         [SVM_EXIT_EXCP_BASE + PF_VECTOR]        = pf_interception,
2741         [SVM_EXIT_EXCP_BASE + MC_VECTOR]        = mc_interception,
2742         [SVM_EXIT_EXCP_BASE + AC_VECTOR]        = ac_interception,
2743         [SVM_EXIT_EXCP_BASE + GP_VECTOR]        = gp_interception,
2744         [SVM_EXIT_INTR]                         = intr_interception,
2745         [SVM_EXIT_NMI]                          = nmi_interception,
2746         [SVM_EXIT_SMI]                          = nop_on_interception,
2747         [SVM_EXIT_INIT]                         = nop_on_interception,
2748         [SVM_EXIT_VINTR]                        = interrupt_window_interception,
2749         [SVM_EXIT_RDPMC]                        = rdpmc_interception,
2750         [SVM_EXIT_CPUID]                        = cpuid_interception,
2751         [SVM_EXIT_IRET]                         = iret_interception,
2752         [SVM_EXIT_INVD]                         = emulate_on_interception,
2753         [SVM_EXIT_PAUSE]                        = pause_interception,
2754         [SVM_EXIT_HLT]                          = halt_interception,
2755         [SVM_EXIT_INVLPG]                       = invlpg_interception,
2756         [SVM_EXIT_INVLPGA]                      = invlpga_interception,
2757         [SVM_EXIT_IOIO]                         = io_interception,
2758         [SVM_EXIT_MSR]                          = msr_interception,
2759         [SVM_EXIT_TASK_SWITCH]                  = task_switch_interception,
2760         [SVM_EXIT_SHUTDOWN]                     = shutdown_interception,
2761         [SVM_EXIT_VMRUN]                        = vmrun_interception,
2762         [SVM_EXIT_VMMCALL]                      = vmmcall_interception,
2763         [SVM_EXIT_VMLOAD]                       = vmload_interception,
2764         [SVM_EXIT_VMSAVE]                       = vmsave_interception,
2765         [SVM_EXIT_STGI]                         = stgi_interception,
2766         [SVM_EXIT_CLGI]                         = clgi_interception,
2767         [SVM_EXIT_SKINIT]                       = skinit_interception,
2768         [SVM_EXIT_WBINVD]                       = wbinvd_interception,
2769         [SVM_EXIT_MONITOR]                      = monitor_interception,
2770         [SVM_EXIT_MWAIT]                        = mwait_interception,
2771         [SVM_EXIT_XSETBV]                       = xsetbv_interception,
2772         [SVM_EXIT_RDPRU]                        = rdpru_interception,
2773         [SVM_EXIT_NPF]                          = npf_interception,
2774         [SVM_EXIT_RSM]                          = rsm_interception,
2775         [SVM_EXIT_AVIC_INCOMPLETE_IPI]          = avic_incomplete_ipi_interception,
2776         [SVM_EXIT_AVIC_UNACCELERATED_ACCESS]    = avic_unaccelerated_access_interception,
2777 };
2778
2779 static void dump_vmcb(struct kvm_vcpu *vcpu)
2780 {
2781         struct vcpu_svm *svm = to_svm(vcpu);
2782         struct vmcb_control_area *control = &svm->vmcb->control;
2783         struct vmcb_save_area *save = &svm->vmcb->save;
2784
2785         if (!dump_invalid_vmcb) {
2786                 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
2787                 return;
2788         }
2789
2790         pr_err("VMCB Control Area:\n");
2791         pr_err("%-20s%04x\n", "cr_read:", control->intercept_cr & 0xffff);
2792         pr_err("%-20s%04x\n", "cr_write:", control->intercept_cr >> 16);
2793         pr_err("%-20s%04x\n", "dr_read:", control->intercept_dr & 0xffff);
2794         pr_err("%-20s%04x\n", "dr_write:", control->intercept_dr >> 16);
2795         pr_err("%-20s%08x\n", "exceptions:", control->intercept_exceptions);
2796         pr_err("%-20s%016llx\n", "intercepts:", control->intercept);
2797         pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
2798         pr_err("%-20s%d\n", "pause filter threshold:",
2799                control->pause_filter_thresh);
2800         pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
2801         pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
2802         pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
2803         pr_err("%-20s%d\n", "asid:", control->asid);
2804         pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
2805         pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
2806         pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
2807         pr_err("%-20s%08x\n", "int_state:", control->int_state);
2808         pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
2809         pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
2810         pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
2811         pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
2812         pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
2813         pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
2814         pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
2815         pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
2816         pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
2817         pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
2818         pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
2819         pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
2820         pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
2821         pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
2822         pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
2823         pr_err("VMCB State Save Area:\n");
2824         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2825                "es:",
2826                save->es.selector, save->es.attrib,
2827                save->es.limit, save->es.base);
2828         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2829                "cs:",
2830                save->cs.selector, save->cs.attrib,
2831                save->cs.limit, save->cs.base);
2832         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2833                "ss:",
2834                save->ss.selector, save->ss.attrib,
2835                save->ss.limit, save->ss.base);
2836         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2837                "ds:",
2838                save->ds.selector, save->ds.attrib,
2839                save->ds.limit, save->ds.base);
2840         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2841                "fs:",
2842                save->fs.selector, save->fs.attrib,
2843                save->fs.limit, save->fs.base);
2844         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2845                "gs:",
2846                save->gs.selector, save->gs.attrib,
2847                save->gs.limit, save->gs.base);
2848         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2849                "gdtr:",
2850                save->gdtr.selector, save->gdtr.attrib,
2851                save->gdtr.limit, save->gdtr.base);
2852         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2853                "ldtr:",
2854                save->ldtr.selector, save->ldtr.attrib,
2855                save->ldtr.limit, save->ldtr.base);
2856         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2857                "idtr:",
2858                save->idtr.selector, save->idtr.attrib,
2859                save->idtr.limit, save->idtr.base);
2860         pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
2861                "tr:",
2862                save->tr.selector, save->tr.attrib,
2863                save->tr.limit, save->tr.base);
2864         pr_err("cpl:            %d                efer:         %016llx\n",
2865                 save->cpl, save->efer);
2866         pr_err("%-15s %016llx %-13s %016llx\n",
2867                "cr0:", save->cr0, "cr2:", save->cr2);
2868         pr_err("%-15s %016llx %-13s %016llx\n",
2869                "cr3:", save->cr3, "cr4:", save->cr4);
2870         pr_err("%-15s %016llx %-13s %016llx\n",
2871                "dr6:", save->dr6, "dr7:", save->dr7);
2872         pr_err("%-15s %016llx %-13s %016llx\n",
2873                "rip:", save->rip, "rflags:", save->rflags);
2874         pr_err("%-15s %016llx %-13s %016llx\n",
2875                "rsp:", save->rsp, "rax:", save->rax);
2876         pr_err("%-15s %016llx %-13s %016llx\n",
2877                "star:", save->star, "lstar:", save->lstar);
2878         pr_err("%-15s %016llx %-13s %016llx\n",
2879                "cstar:", save->cstar, "sfmask:", save->sfmask);
2880         pr_err("%-15s %016llx %-13s %016llx\n",
2881                "kernel_gs_base:", save->kernel_gs_base,
2882                "sysenter_cs:", save->sysenter_cs);
2883         pr_err("%-15s %016llx %-13s %016llx\n",
2884                "sysenter_esp:", save->sysenter_esp,
2885                "sysenter_eip:", save->sysenter_eip);
2886         pr_err("%-15s %016llx %-13s %016llx\n",
2887                "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
2888         pr_err("%-15s %016llx %-13s %016llx\n",
2889                "br_from:", save->br_from, "br_to:", save->br_to);
2890         pr_err("%-15s %016llx %-13s %016llx\n",
2891                "excp_from:", save->last_excp_from,
2892                "excp_to:", save->last_excp_to);
2893 }
2894
2895 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u64 *info1, u64 *info2)
2896 {
2897         struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
2898
2899         *info1 = control->exit_info_1;
2900         *info2 = control->exit_info_2;
2901 }
2902
2903 static int handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
2904 {
2905         struct vcpu_svm *svm = to_svm(vcpu);
2906         struct kvm_run *kvm_run = vcpu->run;
2907         u32 exit_code = svm->vmcb->control.exit_code;
2908
2909         trace_kvm_exit(exit_code, vcpu, KVM_ISA_SVM);
2910
2911         if (!is_cr_intercept(svm, INTERCEPT_CR0_WRITE))
2912                 vcpu->arch.cr0 = svm->vmcb->save.cr0;
2913         if (npt_enabled)
2914                 vcpu->arch.cr3 = svm->vmcb->save.cr3;
2915
2916         svm_complete_interrupts(svm);
2917
2918         if (is_guest_mode(vcpu)) {
2919                 int vmexit;
2920
2921                 trace_kvm_nested_vmexit(svm->vmcb->save.rip, exit_code,
2922                                         svm->vmcb->control.exit_info_1,
2923                                         svm->vmcb->control.exit_info_2,
2924                                         svm->vmcb->control.exit_int_info,
2925                                         svm->vmcb->control.exit_int_info_err,
2926                                         KVM_ISA_SVM);
2927
2928                 vmexit = nested_svm_exit_special(svm);
2929
2930                 if (vmexit == NESTED_EXIT_CONTINUE)
2931                         vmexit = nested_svm_exit_handled(svm);
2932
2933                 if (vmexit == NESTED_EXIT_DONE)
2934                         return 1;
2935         }
2936
2937         if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
2938                 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
2939                 kvm_run->fail_entry.hardware_entry_failure_reason
2940                         = svm->vmcb->control.exit_code;
2941                 dump_vmcb(vcpu);
2942                 return 0;
2943         }
2944
2945         if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
2946             exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
2947             exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
2948             exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
2949                 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
2950                        "exit_code 0x%x\n",
2951                        __func__, svm->vmcb->control.exit_int_info,
2952                        exit_code);
2953
2954         if (exit_fastpath != EXIT_FASTPATH_NONE)
2955                 return 1;
2956
2957         if (exit_code >= ARRAY_SIZE(svm_exit_handlers)
2958             || !svm_exit_handlers[exit_code]) {
2959                 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%x\n", exit_code);
2960                 dump_vmcb(vcpu);
2961                 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
2962                 vcpu->run->internal.suberror =
2963                         KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
2964                 vcpu->run->internal.ndata = 1;
2965                 vcpu->run->internal.data[0] = exit_code;
2966                 return 0;
2967         }
2968
2969 #ifdef CONFIG_RETPOLINE
2970         if (exit_code == SVM_EXIT_MSR)
2971                 return msr_interception(svm);
2972         else if (exit_code == SVM_EXIT_VINTR)
2973                 return interrupt_window_interception(svm);
2974         else if (exit_code == SVM_EXIT_INTR)
2975                 return intr_interception(svm);
2976         else if (exit_code == SVM_EXIT_HLT)
2977                 return halt_interception(svm);
2978         else if (exit_code == SVM_EXIT_NPF)
2979                 return npf_interception(svm);
2980 #endif
2981         return svm_exit_handlers[exit_code](svm);
2982 }
2983
2984 static void reload_tss(struct kvm_vcpu *vcpu)
2985 {
2986         int cpu = raw_smp_processor_id();
2987
2988         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2989         sd->tss_desc->type = 9; /* available 32/64-bit TSS */
2990         load_TR_desc();
2991 }
2992
2993 static void pre_svm_run(struct vcpu_svm *svm)
2994 {
2995         int cpu = raw_smp_processor_id();
2996
2997         struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
2998
2999         if (sev_guest(svm->vcpu.kvm))
3000                 return pre_sev_run(svm, cpu);
3001
3002         /* FIXME: handle wraparound of asid_generation */
3003         if (svm->asid_generation != sd->asid_generation)
3004                 new_asid(svm, sd);
3005 }
3006
3007 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3008 {
3009         struct vcpu_svm *svm = to_svm(vcpu);
3010
3011         svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3012         vcpu->arch.hflags |= HF_NMI_MASK;
3013         set_intercept(svm, INTERCEPT_IRET);
3014         ++vcpu->stat.nmi_injections;
3015 }
3016
3017 static void svm_set_irq(struct kvm_vcpu *vcpu)
3018 {
3019         struct vcpu_svm *svm = to_svm(vcpu);
3020
3021         BUG_ON(!(gif_set(svm)));
3022
3023         trace_kvm_inj_virq(vcpu->arch.interrupt.nr);
3024         ++vcpu->stat.irq_injections;
3025
3026         svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3027                 SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR;
3028 }
3029
3030 static void update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3031 {
3032         struct vcpu_svm *svm = to_svm(vcpu);
3033
3034         if (svm_nested_virtualize_tpr(vcpu))
3035                 return;
3036
3037         clr_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3038
3039         if (irr == -1)
3040                 return;
3041
3042         if (tpr >= irr)
3043                 set_cr_intercept(svm, INTERCEPT_CR8_WRITE);
3044 }
3045
3046 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3047 {
3048         struct vcpu_svm *svm = to_svm(vcpu);
3049         struct vmcb *vmcb = svm->vmcb;
3050         bool ret;
3051
3052         if (!gif_set(svm))
3053                 return true;
3054
3055         if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3056                 return false;
3057
3058         ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3059               (svm->vcpu.arch.hflags & HF_NMI_MASK);
3060
3061         return ret;
3062 }
3063
3064 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3065 {
3066         struct vcpu_svm *svm = to_svm(vcpu);
3067         if (svm->nested.nested_run_pending)
3068                 return -EBUSY;
3069
3070         /* An NMI must not be injected into L2 if it's supposed to VM-Exit.  */
3071         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3072                 return -EBUSY;
3073
3074         return !svm_nmi_blocked(vcpu);
3075 }
3076
3077 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3078 {
3079         struct vcpu_svm *svm = to_svm(vcpu);
3080
3081         return !!(svm->vcpu.arch.hflags & HF_NMI_MASK);
3082 }
3083
3084 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3085 {
3086         struct vcpu_svm *svm = to_svm(vcpu);
3087
3088         if (masked) {
3089                 svm->vcpu.arch.hflags |= HF_NMI_MASK;
3090                 set_intercept(svm, INTERCEPT_IRET);
3091         } else {
3092                 svm->vcpu.arch.hflags &= ~HF_NMI_MASK;
3093                 clr_intercept(svm, INTERCEPT_IRET);
3094         }
3095 }
3096
3097 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3098 {
3099         struct vcpu_svm *svm = to_svm(vcpu);
3100         struct vmcb *vmcb = svm->vmcb;
3101
3102         if (!gif_set(svm))
3103                 return true;
3104
3105         if (is_guest_mode(vcpu)) {
3106                 /* As long as interrupts are being delivered...  */
3107                 if ((svm->vcpu.arch.hflags & HF_VINTR_MASK)
3108                     ? !(svm->vcpu.arch.hflags & HF_HIF_MASK)
3109                     : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3110                         return true;
3111
3112                 /* ... vmexits aren't blocked by the interrupt shadow  */
3113                 if (nested_exit_on_intr(svm))
3114                         return false;
3115         } else {
3116                 if (!(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3117                         return true;
3118         }
3119
3120         return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3121 }
3122
3123 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3124 {
3125         struct vcpu_svm *svm = to_svm(vcpu);
3126         if (svm->nested.nested_run_pending)
3127                 return -EBUSY;
3128
3129         /*
3130          * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3131          * e.g. if the IRQ arrived asynchronously after checking nested events.
3132          */
3133         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3134                 return -EBUSY;
3135
3136         return !svm_interrupt_blocked(vcpu);
3137 }
3138
3139 static void enable_irq_window(struct kvm_vcpu *vcpu)
3140 {
3141         struct vcpu_svm *svm = to_svm(vcpu);
3142
3143         /*
3144          * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3145          * 1, because that's a separate STGI/VMRUN intercept.  The next time we
3146          * get that intercept, this function will be called again though and
3147          * we'll get the vintr intercept. However, if the vGIF feature is
3148          * enabled, the STGI interception will not occur. Enable the irq
3149          * window under the assumption that the hardware will set the GIF.
3150          */
3151         if (vgif_enabled(svm) || gif_set(svm)) {
3152                 /*
3153                  * IRQ window is not needed when AVIC is enabled,
3154                  * unless we have pending ExtINT since it cannot be injected
3155                  * via AVIC. In such case, we need to temporarily disable AVIC,
3156                  * and fallback to injecting IRQ via V_IRQ.
3157                  */
3158                 svm_toggle_avic_for_irq_window(vcpu, false);
3159                 svm_set_vintr(svm);
3160         }
3161 }
3162
3163 static void enable_nmi_window(struct kvm_vcpu *vcpu)
3164 {
3165         struct vcpu_svm *svm = to_svm(vcpu);
3166
3167         if ((svm->vcpu.arch.hflags & (HF_NMI_MASK | HF_IRET_MASK))
3168             == HF_NMI_MASK)
3169                 return; /* IRET will cause a vm exit */
3170
3171         if (!gif_set(svm)) {
3172                 if (vgif_enabled(svm))
3173                         set_intercept(svm, INTERCEPT_STGI);
3174                 return; /* STGI will cause a vm exit */
3175         }
3176
3177         /*
3178          * Something prevents NMI from been injected. Single step over possible
3179          * problem (IRET or exception injection or interrupt shadow)
3180          */
3181         svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3182         svm->nmi_singlestep = true;
3183         svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3184 }
3185
3186 static int svm_set_tss_addr(struct kvm *kvm, unsigned int addr)
3187 {
3188         return 0;
3189 }
3190
3191 static int svm_set_identity_map_addr(struct kvm *kvm, u64 ident_addr)
3192 {
3193         return 0;
3194 }
3195
3196 void svm_flush_tlb(struct kvm_vcpu *vcpu)
3197 {
3198         struct vcpu_svm *svm = to_svm(vcpu);
3199
3200         /*
3201          * Flush only the current ASID even if the TLB flush was invoked via
3202          * kvm_flush_remote_tlbs().  Although flushing remote TLBs requires all
3203          * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3204          * unconditionally does a TLB flush on both nested VM-Enter and nested
3205          * VM-Exit (via kvm_mmu_reset_context()).
3206          */
3207         if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3208                 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3209         else
3210                 svm->asid_generation--;
3211 }
3212
3213 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3214 {
3215         struct vcpu_svm *svm = to_svm(vcpu);
3216
3217         invlpga(gva, svm->vmcb->control.asid);
3218 }
3219
3220 static void svm_prepare_guest_switch(struct kvm_vcpu *vcpu)
3221 {
3222 }
3223
3224 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3225 {
3226         struct vcpu_svm *svm = to_svm(vcpu);
3227
3228         if (svm_nested_virtualize_tpr(vcpu))
3229                 return;
3230
3231         if (!is_cr_intercept(svm, INTERCEPT_CR8_WRITE)) {
3232                 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3233                 kvm_set_cr8(vcpu, cr8);
3234         }
3235 }
3236
3237 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3238 {
3239         struct vcpu_svm *svm = to_svm(vcpu);
3240         u64 cr8;
3241
3242         if (svm_nested_virtualize_tpr(vcpu) ||
3243             kvm_vcpu_apicv_active(vcpu))
3244                 return;
3245
3246         cr8 = kvm_get_cr8(vcpu);
3247         svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3248         svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3249 }
3250
3251 static void svm_complete_interrupts(struct vcpu_svm *svm)
3252 {
3253         u8 vector;
3254         int type;
3255         u32 exitintinfo = svm->vmcb->control.exit_int_info;
3256         unsigned int3_injected = svm->int3_injected;
3257
3258         svm->int3_injected = 0;
3259
3260         /*
3261          * If we've made progress since setting HF_IRET_MASK, we've
3262          * executed an IRET and can allow NMI injection.
3263          */
3264         if ((svm->vcpu.arch.hflags & HF_IRET_MASK)
3265             && kvm_rip_read(&svm->vcpu) != svm->nmi_iret_rip) {
3266                 svm->vcpu.arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3267                 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3268         }
3269
3270         svm->vcpu.arch.nmi_injected = false;
3271         kvm_clear_exception_queue(&svm->vcpu);
3272         kvm_clear_interrupt_queue(&svm->vcpu);
3273
3274         if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3275                 return;
3276
3277         kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
3278
3279         vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3280         type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3281
3282         switch (type) {
3283         case SVM_EXITINTINFO_TYPE_NMI:
3284                 svm->vcpu.arch.nmi_injected = true;
3285                 break;
3286         case SVM_EXITINTINFO_TYPE_EXEPT:
3287                 /*
3288                  * In case of software exceptions, do not reinject the vector,
3289                  * but re-execute the instruction instead. Rewind RIP first
3290                  * if we emulated INT3 before.
3291                  */
3292                 if (kvm_exception_is_soft(vector)) {
3293                         if (vector == BP_VECTOR && int3_injected &&
3294                             kvm_is_linear_rip(&svm->vcpu, svm->int3_rip))
3295                                 kvm_rip_write(&svm->vcpu,
3296                                               kvm_rip_read(&svm->vcpu) -
3297                                               int3_injected);
3298                         break;
3299                 }
3300                 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3301                         u32 err = svm->vmcb->control.exit_int_info_err;
3302                         kvm_requeue_exception_e(&svm->vcpu, vector, err);
3303
3304                 } else
3305                         kvm_requeue_exception(&svm->vcpu, vector);
3306                 break;
3307         case SVM_EXITINTINFO_TYPE_INTR:
3308                 kvm_queue_interrupt(&svm->vcpu, vector, false);
3309                 break;
3310         default:
3311                 break;
3312         }
3313 }
3314
3315 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3316 {
3317         struct vcpu_svm *svm = to_svm(vcpu);
3318         struct vmcb_control_area *control = &svm->vmcb->control;
3319
3320         control->exit_int_info = control->event_inj;
3321         control->exit_int_info_err = control->event_inj_err;
3322         control->event_inj = 0;
3323         svm_complete_interrupts(svm);
3324 }
3325
3326 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3327 {
3328         if (!is_guest_mode(vcpu) &&
3329             to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3330             to_svm(vcpu)->vmcb->control.exit_info_1)
3331                 return handle_fastpath_set_msr_irqoff(vcpu);
3332
3333         return EXIT_FASTPATH_NONE;
3334 }
3335
3336 void __svm_vcpu_run(unsigned long vmcb_pa, unsigned long *regs);
3337
3338 static fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3339 {
3340         fastpath_t exit_fastpath;
3341         struct vcpu_svm *svm = to_svm(vcpu);
3342
3343         svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3344         svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3345         svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3346
3347         /*
3348          * Disable singlestep if we're injecting an interrupt/exception.
3349          * We don't want our modified rflags to be pushed on the stack where
3350          * we might not be able to easily reset them if we disabled NMI
3351          * singlestep later.
3352          */
3353         if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3354                 /*
3355                  * Event injection happens before external interrupts cause a
3356                  * vmexit and interrupts are disabled here, so smp_send_reschedule
3357                  * is enough to force an immediate vmexit.
3358                  */
3359                 disable_nmi_singlestep(svm);
3360                 smp_send_reschedule(vcpu->cpu);
3361         }
3362
3363         pre_svm_run(svm);
3364
3365         sync_lapic_to_cr8(vcpu);
3366
3367         svm->vmcb->save.cr2 = vcpu->arch.cr2;
3368
3369         /*
3370          * Run with all-zero DR6 unless needed, so that we can get the exact cause
3371          * of a #DB.
3372          */
3373         if (unlikely(svm->vcpu.arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3374                 svm_set_dr6(svm, vcpu->arch.dr6);
3375         else
3376                 svm_set_dr6(svm, DR6_FIXED_1 | DR6_RTM);
3377
3378         clgi();
3379         kvm_load_guest_xsave_state(vcpu);
3380
3381         if (lapic_in_kernel(vcpu) &&
3382                 vcpu->arch.apic->lapic_timer.timer_advance_ns)
3383                 kvm_wait_lapic_expire(vcpu);
3384
3385         /*
3386          * If this vCPU has touched SPEC_CTRL, restore the guest's value if
3387          * it's non-zero. Since vmentry is serialising on affected CPUs, there
3388          * is no need to worry about the conditional branch over the wrmsr
3389          * being speculatively taken.
3390          */
3391         x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
3392
3393         __svm_vcpu_run(svm->vmcb_pa, (unsigned long *)&svm->vcpu.arch.regs);
3394
3395 #ifdef CONFIG_X86_64
3396         wrmsrl(MSR_GS_BASE, svm->host.gs_base);
3397 #else
3398         loadsegment(fs, svm->host.fs);
3399 #ifndef CONFIG_X86_32_LAZY_GS
3400         loadsegment(gs, svm->host.gs);
3401 #endif
3402 #endif
3403
3404         /*
3405          * We do not use IBRS in the kernel. If this vCPU has used the
3406          * SPEC_CTRL MSR it may have left it on; save the value and
3407          * turn it off. This is much more efficient than blindly adding
3408          * it to the atomic save/restore list. Especially as the former
3409          * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
3410          *
3411          * For non-nested case:
3412          * If the L01 MSR bitmap does not intercept the MSR, then we need to
3413          * save it.
3414          *
3415          * For nested case:
3416          * If the L02 MSR bitmap does not intercept the MSR, then we need to
3417          * save it.
3418          */
3419         if (unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
3420                 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
3421
3422         reload_tss(vcpu);
3423
3424         x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
3425
3426         vcpu->arch.cr2 = svm->vmcb->save.cr2;
3427         vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
3428         vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
3429         vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
3430
3431         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3432                 kvm_before_interrupt(&svm->vcpu);
3433
3434         kvm_load_host_xsave_state(vcpu);
3435         stgi();
3436
3437         /* Any pending NMI will happen here */
3438         exit_fastpath = svm_exit_handlers_fastpath(vcpu);
3439
3440         if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
3441                 kvm_after_interrupt(&svm->vcpu);
3442
3443         sync_cr8_to_lapic(vcpu);
3444
3445         svm->next_rip = 0;
3446         if (is_guest_mode(&svm->vcpu)) {
3447                 sync_nested_vmcb_control(svm);
3448                 svm->nested.nested_run_pending = 0;
3449         }
3450
3451         svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
3452
3453         /* if exit due to PF check for async PF */
3454         if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
3455                 svm->vcpu.arch.apf.host_apf_reason = kvm_read_and_reset_pf_reason();
3456
3457         if (npt_enabled) {
3458                 vcpu->arch.regs_avail &= ~(1 << VCPU_EXREG_PDPTR);
3459                 vcpu->arch.regs_dirty &= ~(1 << VCPU_EXREG_PDPTR);
3460         }
3461
3462         /*
3463          * We need to handle MC intercepts here before the vcpu has a chance to
3464          * change the physical cpu
3465          */
3466         if (unlikely(svm->vmcb->control.exit_code ==
3467                      SVM_EXIT_EXCP_BASE + MC_VECTOR))
3468                 svm_handle_mce(svm);
3469
3470         mark_all_clean(svm->vmcb);
3471         return exit_fastpath;
3472 }
3473
3474 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, unsigned long root)
3475 {
3476         struct vcpu_svm *svm = to_svm(vcpu);
3477         unsigned long cr3;
3478
3479         cr3 = __sme_set(root);
3480         if (npt_enabled) {
3481                 svm->vmcb->control.nested_cr3 = cr3;
3482                 mark_dirty(svm->vmcb, VMCB_NPT);
3483
3484                 /* Loading L2's CR3 is handled by enter_svm_guest_mode.  */
3485                 if (!test_bit(VCPU_EXREG_CR3, (ulong *)&vcpu->arch.regs_avail))
3486                         return;
3487                 cr3 = vcpu->arch.cr3;
3488         }
3489
3490         svm->vmcb->save.cr3 = cr3;
3491         mark_dirty(svm->vmcb, VMCB_CR);
3492 }
3493
3494 static int is_disabled(void)
3495 {
3496         u64 vm_cr;
3497
3498         rdmsrl(MSR_VM_CR, vm_cr);
3499         if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
3500                 return 1;
3501
3502         return 0;
3503 }
3504
3505 static void
3506 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
3507 {
3508         /*
3509          * Patch in the VMMCALL instruction:
3510          */
3511         hypercall[0] = 0x0f;
3512         hypercall[1] = 0x01;
3513         hypercall[2] = 0xd9;
3514 }
3515
3516 static int __init svm_check_processor_compat(void)
3517 {
3518         return 0;
3519 }
3520
3521 static bool svm_cpu_has_accelerated_tpr(void)
3522 {
3523         return false;
3524 }
3525
3526 static bool svm_has_emulated_msr(u32 index)
3527 {
3528         switch (index) {
3529         case MSR_IA32_MCG_EXT_CTL:
3530         case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
3531                 return false;
3532         default:
3533                 break;
3534         }
3535
3536         return true;
3537 }
3538
3539 static u64 svm_get_mt_mask(struct kvm_vcpu *vcpu, gfn_t gfn, bool is_mmio)
3540 {
3541         return 0;
3542 }
3543
3544 static void svm_cpuid_update(struct kvm_vcpu *vcpu)
3545 {
3546         struct vcpu_svm *svm = to_svm(vcpu);
3547
3548         vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
3549                                     boot_cpu_has(X86_FEATURE_XSAVE) &&
3550                                     boot_cpu_has(X86_FEATURE_XSAVES);
3551
3552         /* Update nrips enabled cache */
3553         svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
3554                              guest_cpuid_has(&svm->vcpu, X86_FEATURE_NRIPS);
3555
3556         if (!kvm_vcpu_apicv_active(vcpu))
3557                 return;
3558
3559         /*
3560          * AVIC does not work with an x2APIC mode guest. If the X2APIC feature
3561          * is exposed to the guest, disable AVIC.
3562          */
3563         if (guest_cpuid_has(vcpu, X86_FEATURE_X2APIC))
3564                 kvm_request_apicv_update(vcpu->kvm, false,
3565                                          APICV_INHIBIT_REASON_X2APIC);
3566
3567         /*
3568          * Currently, AVIC does not work with nested virtualization.
3569          * So, we disable AVIC when cpuid for SVM is set in the L1 guest.
3570          */
3571         if (nested && guest_cpuid_has(vcpu, X86_FEATURE_SVM))
3572                 kvm_request_apicv_update(vcpu->kvm, false,
3573                                          APICV_INHIBIT_REASON_NESTED);
3574 }
3575
3576 static bool svm_has_wbinvd_exit(void)
3577 {
3578         return true;
3579 }
3580
3581 #define PRE_EX(exit)  { .exit_code = (exit), \
3582                         .stage = X86_ICPT_PRE_EXCEPT, }
3583 #define POST_EX(exit) { .exit_code = (exit), \
3584                         .stage = X86_ICPT_POST_EXCEPT, }
3585 #define POST_MEM(exit) { .exit_code = (exit), \
3586                         .stage = X86_ICPT_POST_MEMACCESS, }
3587
3588 static const struct __x86_intercept {
3589         u32 exit_code;
3590         enum x86_intercept_stage stage;
3591 } x86_intercept_map[] = {
3592         [x86_intercept_cr_read]         = POST_EX(SVM_EXIT_READ_CR0),
3593         [x86_intercept_cr_write]        = POST_EX(SVM_EXIT_WRITE_CR0),
3594         [x86_intercept_clts]            = POST_EX(SVM_EXIT_WRITE_CR0),
3595         [x86_intercept_lmsw]            = POST_EX(SVM_EXIT_WRITE_CR0),
3596         [x86_intercept_smsw]            = POST_EX(SVM_EXIT_READ_CR0),
3597         [x86_intercept_dr_read]         = POST_EX(SVM_EXIT_READ_DR0),
3598         [x86_intercept_dr_write]        = POST_EX(SVM_EXIT_WRITE_DR0),
3599         [x86_intercept_sldt]            = POST_EX(SVM_EXIT_LDTR_READ),
3600         [x86_intercept_str]             = POST_EX(SVM_EXIT_TR_READ),
3601         [x86_intercept_lldt]            = POST_EX(SVM_EXIT_LDTR_WRITE),
3602         [x86_intercept_ltr]             = POST_EX(SVM_EXIT_TR_WRITE),
3603         [x86_intercept_sgdt]            = POST_EX(SVM_EXIT_GDTR_READ),
3604         [x86_intercept_sidt]            = POST_EX(SVM_EXIT_IDTR_READ),
3605         [x86_intercept_lgdt]            = POST_EX(SVM_EXIT_GDTR_WRITE),
3606         [x86_intercept_lidt]            = POST_EX(SVM_EXIT_IDTR_WRITE),
3607         [x86_intercept_vmrun]           = POST_EX(SVM_EXIT_VMRUN),
3608         [x86_intercept_vmmcall]         = POST_EX(SVM_EXIT_VMMCALL),
3609         [x86_intercept_vmload]          = POST_EX(SVM_EXIT_VMLOAD),
3610         [x86_intercept_vmsave]          = POST_EX(SVM_EXIT_VMSAVE),
3611         [x86_intercept_stgi]            = POST_EX(SVM_EXIT_STGI),
3612         [x86_intercept_clgi]            = POST_EX(SVM_EXIT_CLGI),
3613         [x86_intercept_skinit]          = POST_EX(SVM_EXIT_SKINIT),
3614         [x86_intercept_invlpga]         = POST_EX(SVM_EXIT_INVLPGA),
3615         [x86_intercept_rdtscp]          = POST_EX(SVM_EXIT_RDTSCP),
3616         [x86_intercept_monitor]         = POST_MEM(SVM_EXIT_MONITOR),
3617         [x86_intercept_mwait]           = POST_EX(SVM_EXIT_MWAIT),
3618         [x86_intercept_invlpg]          = POST_EX(SVM_EXIT_INVLPG),
3619         [x86_intercept_invd]            = POST_EX(SVM_EXIT_INVD),
3620         [x86_intercept_wbinvd]          = POST_EX(SVM_EXIT_WBINVD),
3621         [x86_intercept_wrmsr]           = POST_EX(SVM_EXIT_MSR),
3622         [x86_intercept_rdtsc]           = POST_EX(SVM_EXIT_RDTSC),
3623         [x86_intercept_rdmsr]           = POST_EX(SVM_EXIT_MSR),
3624         [x86_intercept_rdpmc]           = POST_EX(SVM_EXIT_RDPMC),
3625         [x86_intercept_cpuid]           = PRE_EX(SVM_EXIT_CPUID),
3626         [x86_intercept_rsm]             = PRE_EX(SVM_EXIT_RSM),
3627         [x86_intercept_pause]           = PRE_EX(SVM_EXIT_PAUSE),
3628         [x86_intercept_pushf]           = PRE_EX(SVM_EXIT_PUSHF),
3629         [x86_intercept_popf]            = PRE_EX(SVM_EXIT_POPF),
3630         [x86_intercept_intn]            = PRE_EX(SVM_EXIT_SWINT),
3631         [x86_intercept_iret]            = PRE_EX(SVM_EXIT_IRET),
3632         [x86_intercept_icebp]           = PRE_EX(SVM_EXIT_ICEBP),
3633         [x86_intercept_hlt]             = POST_EX(SVM_EXIT_HLT),
3634         [x86_intercept_in]              = POST_EX(SVM_EXIT_IOIO),
3635         [x86_intercept_ins]             = POST_EX(SVM_EXIT_IOIO),
3636         [x86_intercept_out]             = POST_EX(SVM_EXIT_IOIO),
3637         [x86_intercept_outs]            = POST_EX(SVM_EXIT_IOIO),
3638         [x86_intercept_xsetbv]          = PRE_EX(SVM_EXIT_XSETBV),
3639 };
3640
3641 #undef PRE_EX
3642 #undef POST_EX
3643 #undef POST_MEM
3644
3645 static int svm_check_intercept(struct kvm_vcpu *vcpu,
3646                                struct x86_instruction_info *info,
3647                                enum x86_intercept_stage stage,
3648                                struct x86_exception *exception)
3649 {
3650         struct vcpu_svm *svm = to_svm(vcpu);
3651         int vmexit, ret = X86EMUL_CONTINUE;
3652         struct __x86_intercept icpt_info;
3653         struct vmcb *vmcb = svm->vmcb;
3654
3655         if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
3656                 goto out;
3657
3658         icpt_info = x86_intercept_map[info->intercept];
3659
3660         if (stage != icpt_info.stage)
3661                 goto out;
3662
3663         switch (icpt_info.exit_code) {
3664         case SVM_EXIT_READ_CR0:
3665                 if (info->intercept == x86_intercept_cr_read)
3666                         icpt_info.exit_code += info->modrm_reg;
3667                 break;
3668         case SVM_EXIT_WRITE_CR0: {
3669                 unsigned long cr0, val;
3670                 u64 intercept;
3671
3672                 if (info->intercept == x86_intercept_cr_write)
3673                         icpt_info.exit_code += info->modrm_reg;
3674
3675                 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
3676                     info->intercept == x86_intercept_clts)
3677                         break;
3678
3679                 intercept = svm->nested.ctl.intercept;
3680
3681                 if (!(intercept & (1ULL << INTERCEPT_SELECTIVE_CR0)))
3682                         break;
3683
3684                 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
3685                 val = info->src_val  & ~SVM_CR0_SELECTIVE_MASK;
3686
3687                 if (info->intercept == x86_intercept_lmsw) {
3688                         cr0 &= 0xfUL;
3689                         val &= 0xfUL;
3690                         /* lmsw can't clear PE - catch this here */
3691                         if (cr0 & X86_CR0_PE)
3692                                 val |= X86_CR0_PE;
3693                 }
3694
3695                 if (cr0 ^ val)
3696                         icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
3697
3698                 break;
3699         }
3700         case SVM_EXIT_READ_DR0:
3701         case SVM_EXIT_WRITE_DR0:
3702                 icpt_info.exit_code += info->modrm_reg;
3703                 break;
3704         case SVM_EXIT_MSR:
3705                 if (info->intercept == x86_intercept_wrmsr)
3706                         vmcb->control.exit_info_1 = 1;
3707                 else
3708                         vmcb->control.exit_info_1 = 0;
3709                 break;
3710         case SVM_EXIT_PAUSE:
3711                 /*
3712                  * We get this for NOP only, but pause
3713                  * is rep not, check this here
3714                  */
3715                 if (info->rep_prefix != REPE_PREFIX)
3716                         goto out;
3717                 break;
3718         case SVM_EXIT_IOIO: {
3719                 u64 exit_info;
3720                 u32 bytes;
3721
3722                 if (info->intercept == x86_intercept_in ||
3723                     info->intercept == x86_intercept_ins) {
3724                         exit_info = ((info->src_val & 0xffff) << 16) |
3725                                 SVM_IOIO_TYPE_MASK;
3726                         bytes = info->dst_bytes;
3727                 } else {
3728                         exit_info = (info->dst_val & 0xffff) << 16;
3729                         bytes = info->src_bytes;
3730                 }
3731
3732                 if (info->intercept == x86_intercept_outs ||
3733                     info->intercept == x86_intercept_ins)
3734                         exit_info |= SVM_IOIO_STR_MASK;
3735
3736                 if (info->rep_prefix)
3737                         exit_info |= SVM_IOIO_REP_MASK;
3738
3739                 bytes = min(bytes, 4u);
3740
3741                 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
3742
3743                 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
3744
3745                 vmcb->control.exit_info_1 = exit_info;
3746                 vmcb->control.exit_info_2 = info->next_rip;
3747
3748                 break;
3749         }
3750         default:
3751                 break;
3752         }
3753
3754         /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
3755         if (static_cpu_has(X86_FEATURE_NRIPS))
3756                 vmcb->control.next_rip  = info->next_rip;
3757         vmcb->control.exit_code = icpt_info.exit_code;
3758         vmexit = nested_svm_exit_handled(svm);
3759
3760         ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
3761                                            : X86EMUL_CONTINUE;
3762
3763 out:
3764         return ret;
3765 }
3766
3767 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
3768 {
3769 }
3770
3771 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
3772 {
3773         if (pause_filter_thresh)
3774                 shrink_ple_window(vcpu);
3775 }
3776
3777 static void svm_setup_mce(struct kvm_vcpu *vcpu)
3778 {
3779         /* [63:9] are reserved. */
3780         vcpu->arch.mcg_cap &= 0x1ff;
3781 }
3782
3783 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
3784 {
3785         struct vcpu_svm *svm = to_svm(vcpu);
3786
3787         /* Per APM Vol.2 15.22.2 "Response to SMI" */
3788         if (!gif_set(svm))
3789                 return true;
3790
3791         return is_smm(vcpu);
3792 }
3793
3794 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3795 {
3796         struct vcpu_svm *svm = to_svm(vcpu);
3797         if (svm->nested.nested_run_pending)
3798                 return -EBUSY;
3799
3800         /* An SMI must not be injected into L2 if it's supposed to VM-Exit.  */
3801         if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
3802                 return -EBUSY;
3803
3804         return !svm_smi_blocked(vcpu);
3805 }
3806
3807 static int svm_pre_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
3808 {
3809         struct vcpu_svm *svm = to_svm(vcpu);
3810         int ret;
3811
3812         if (is_guest_mode(vcpu)) {
3813                 /* FED8h - SVM Guest */
3814                 put_smstate(u64, smstate, 0x7ed8, 1);
3815                 /* FEE0h - SVM Guest VMCB Physical Address */
3816                 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb);
3817
3818                 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3819                 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3820                 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3821
3822                 ret = nested_svm_vmexit(svm);
3823                 if (ret)
3824                         return ret;
3825         }
3826         return 0;
3827 }
3828
3829 static int svm_pre_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
3830 {
3831         struct vcpu_svm *svm = to_svm(vcpu);
3832         struct vmcb *nested_vmcb;
3833         struct kvm_host_map map;
3834         u64 guest;
3835         u64 vmcb;
3836
3837         guest = GET_SMSTATE(u64, smstate, 0x7ed8);
3838         vmcb = GET_SMSTATE(u64, smstate, 0x7ee0);
3839
3840         if (guest) {
3841                 if (kvm_vcpu_map(&svm->vcpu, gpa_to_gfn(vmcb), &map) == -EINVAL)
3842                         return 1;
3843                 nested_vmcb = map.hva;
3844                 enter_svm_guest_mode(svm, vmcb, nested_vmcb);
3845                 kvm_vcpu_unmap(&svm->vcpu, &map, true);
3846         }
3847         return 0;
3848 }
3849
3850 static void enable_smi_window(struct kvm_vcpu *vcpu)
3851 {
3852         struct vcpu_svm *svm = to_svm(vcpu);
3853
3854         if (!gif_set(svm)) {
3855                 if (vgif_enabled(svm))
3856                         set_intercept(svm, INTERCEPT_STGI);
3857                 /* STGI will cause a vm exit */
3858         } else {
3859                 /* We must be in SMM; RSM will cause a vmexit anyway.  */
3860         }
3861 }
3862
3863 static bool svm_need_emulation_on_page_fault(struct kvm_vcpu *vcpu)
3864 {
3865         unsigned long cr4 = kvm_read_cr4(vcpu);
3866         bool smep = cr4 & X86_CR4_SMEP;
3867         bool smap = cr4 & X86_CR4_SMAP;
3868         bool is_user = svm_get_cpl(vcpu) == 3;
3869
3870         /*
3871          * If RIP is invalid, go ahead with emulation which will cause an
3872          * internal error exit.
3873          */
3874         if (!kvm_vcpu_gfn_to_memslot(vcpu, kvm_rip_read(vcpu) >> PAGE_SHIFT))
3875                 return true;
3876
3877         /*
3878          * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
3879          *
3880          * Errata:
3881          * When CPU raise #NPF on guest data access and vCPU CR4.SMAP=1, it is
3882          * possible that CPU microcode implementing DecodeAssist will fail
3883          * to read bytes of instruction which caused #NPF. In this case,
3884          * GuestIntrBytes field of the VMCB on a VMEXIT will incorrectly
3885          * return 0 instead of the correct guest instruction bytes.
3886          *
3887          * This happens because CPU microcode reading instruction bytes
3888          * uses a special opcode which attempts to read data using CPL=0
3889          * priviledges. The microcode reads CS:RIP and if it hits a SMAP
3890          * fault, it gives up and returns no instruction bytes.
3891          *
3892          * Detection:
3893          * We reach here in case CPU supports DecodeAssist, raised #NPF and
3894          * returned 0 in GuestIntrBytes field of the VMCB.
3895          * First, errata can only be triggered in case vCPU CR4.SMAP=1.
3896          * Second, if vCPU CR4.SMEP=1, errata could only be triggered
3897          * in case vCPU CPL==3 (Because otherwise guest would have triggered
3898          * a SMEP fault instead of #NPF).
3899          * Otherwise, vCPU CR4.SMEP=0, errata could be triggered by any vCPU CPL.
3900          * As most guests enable SMAP if they have also enabled SMEP, use above
3901          * logic in order to attempt minimize false-positive of detecting errata
3902          * while still preserving all cases semantic correctness.
3903          *
3904          * Workaround:
3905          * To determine what instruction the guest was executing, the hypervisor
3906          * will have to decode the instruction at the instruction pointer.
3907          *
3908          * In non SEV guest, hypervisor will be able to read the guest
3909          * memory to decode the instruction pointer when insn_len is zero
3910          * so we return true to indicate that decoding is possible.
3911          *
3912          * But in the SEV guest, the guest memory is encrypted with the
3913          * guest specific key and hypervisor will not be able to decode the
3914          * instruction pointer so we will not able to workaround it. Lets
3915          * print the error and request to kill the guest.
3916          */
3917         if (smap && (!smep || is_user)) {
3918                 if (!sev_guest(vcpu->kvm))
3919                         return true;
3920
3921                 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
3922                 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3923         }
3924
3925         return false;
3926 }
3927
3928 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
3929 {
3930         struct vcpu_svm *svm = to_svm(vcpu);
3931
3932         /*
3933          * TODO: Last condition latch INIT signals on vCPU when
3934          * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
3935          * To properly emulate the INIT intercept,
3936          * svm_check_nested_events() should call nested_svm_vmexit()
3937          * if an INIT signal is pending.
3938          */
3939         return !gif_set(svm) ||
3940                    (svm->vmcb->control.intercept & (1ULL << INTERCEPT_INIT));
3941 }
3942
3943 static void svm_vm_destroy(struct kvm *kvm)
3944 {
3945         avic_vm_destroy(kvm);
3946         sev_vm_destroy(kvm);
3947 }
3948
3949 static int svm_vm_init(struct kvm *kvm)
3950 {
3951         if (avic) {
3952                 int ret = avic_vm_init(kvm);
3953                 if (ret)
3954                         return ret;
3955         }
3956
3957         kvm_apicv_init(kvm, avic);
3958         return 0;
3959 }
3960
3961 static struct kvm_x86_ops svm_x86_ops __initdata = {
3962         .hardware_unsetup = svm_hardware_teardown,
3963         .hardware_enable = svm_hardware_enable,
3964         .hardware_disable = svm_hardware_disable,
3965         .cpu_has_accelerated_tpr = svm_cpu_has_accelerated_tpr,
3966         .has_emulated_msr = svm_has_emulated_msr,
3967
3968         .vcpu_create = svm_create_vcpu,
3969         .vcpu_free = svm_free_vcpu,
3970         .vcpu_reset = svm_vcpu_reset,
3971
3972         .vm_size = sizeof(struct kvm_svm),
3973         .vm_init = svm_vm_init,
3974         .vm_destroy = svm_vm_destroy,
3975
3976         .prepare_guest_switch = svm_prepare_guest_switch,
3977         .vcpu_load = svm_vcpu_load,
3978         .vcpu_put = svm_vcpu_put,
3979         .vcpu_blocking = svm_vcpu_blocking,
3980         .vcpu_unblocking = svm_vcpu_unblocking,
3981
3982         .update_bp_intercept = update_bp_intercept,
3983         .get_msr_feature = svm_get_msr_feature,
3984         .get_msr = svm_get_msr,
3985         .set_msr = svm_set_msr,
3986         .get_segment_base = svm_get_segment_base,
3987         .get_segment = svm_get_segment,
3988         .set_segment = svm_set_segment,
3989         .get_cpl = svm_get_cpl,
3990         .get_cs_db_l_bits = kvm_get_cs_db_l_bits,
3991         .set_cr0 = svm_set_cr0,
3992         .set_cr4 = svm_set_cr4,
3993         .set_efer = svm_set_efer,
3994         .get_idt = svm_get_idt,
3995         .set_idt = svm_set_idt,
3996         .get_gdt = svm_get_gdt,
3997         .set_gdt = svm_set_gdt,
3998         .set_dr7 = svm_set_dr7,
3999         .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4000         .cache_reg = svm_cache_reg,
4001         .get_rflags = svm_get_rflags,
4002         .set_rflags = svm_set_rflags,
4003
4004         .tlb_flush_all = svm_flush_tlb,
4005         .tlb_flush_current = svm_flush_tlb,
4006         .tlb_flush_gva = svm_flush_tlb_gva,
4007         .tlb_flush_guest = svm_flush_tlb,
4008
4009         .run = svm_vcpu_run,
4010         .handle_exit = handle_exit,
4011         .skip_emulated_instruction = skip_emulated_instruction,
4012         .update_emulated_instruction = NULL,
4013         .set_interrupt_shadow = svm_set_interrupt_shadow,
4014         .get_interrupt_shadow = svm_get_interrupt_shadow,
4015         .patch_hypercall = svm_patch_hypercall,
4016         .set_irq = svm_set_irq,
4017         .set_nmi = svm_inject_nmi,
4018         .queue_exception = svm_queue_exception,
4019         .cancel_injection = svm_cancel_injection,
4020         .interrupt_allowed = svm_interrupt_allowed,
4021         .nmi_allowed = svm_nmi_allowed,
4022         .get_nmi_mask = svm_get_nmi_mask,
4023         .set_nmi_mask = svm_set_nmi_mask,
4024         .enable_nmi_window = enable_nmi_window,
4025         .enable_irq_window = enable_irq_window,
4026         .update_cr8_intercept = update_cr8_intercept,
4027         .set_virtual_apic_mode = svm_set_virtual_apic_mode,
4028         .refresh_apicv_exec_ctrl = svm_refresh_apicv_exec_ctrl,
4029         .check_apicv_inhibit_reasons = svm_check_apicv_inhibit_reasons,
4030         .pre_update_apicv_exec_ctrl = svm_pre_update_apicv_exec_ctrl,
4031         .load_eoi_exitmap = svm_load_eoi_exitmap,
4032         .hwapic_irr_update = svm_hwapic_irr_update,
4033         .hwapic_isr_update = svm_hwapic_isr_update,
4034         .sync_pir_to_irr = kvm_lapic_find_highest_irr,
4035         .apicv_post_state_restore = avic_post_state_restore,
4036
4037         .set_tss_addr = svm_set_tss_addr,
4038         .set_identity_map_addr = svm_set_identity_map_addr,
4039         .get_tdp_level = get_npt_level,
4040         .get_mt_mask = svm_get_mt_mask,
4041
4042         .get_exit_info = svm_get_exit_info,
4043
4044         .cpuid_update = svm_cpuid_update,
4045
4046         .has_wbinvd_exit = svm_has_wbinvd_exit,
4047
4048         .write_l1_tsc_offset = svm_write_l1_tsc_offset,
4049
4050         .load_mmu_pgd = svm_load_mmu_pgd,
4051
4052         .check_intercept = svm_check_intercept,
4053         .handle_exit_irqoff = svm_handle_exit_irqoff,
4054
4055         .request_immediate_exit = __kvm_request_immediate_exit,
4056
4057         .sched_in = svm_sched_in,
4058
4059         .pmu_ops = &amd_pmu_ops,
4060         .nested_ops = &svm_nested_ops,
4061
4062         .deliver_posted_interrupt = svm_deliver_avic_intr,
4063         .dy_apicv_has_pending_interrupt = svm_dy_apicv_has_pending_interrupt,
4064         .update_pi_irte = svm_update_pi_irte,
4065         .setup_mce = svm_setup_mce,
4066
4067         .smi_allowed = svm_smi_allowed,
4068         .pre_enter_smm = svm_pre_enter_smm,
4069         .pre_leave_smm = svm_pre_leave_smm,
4070         .enable_smi_window = enable_smi_window,
4071
4072         .mem_enc_op = svm_mem_enc_op,
4073         .mem_enc_reg_region = svm_register_enc_region,
4074         .mem_enc_unreg_region = svm_unregister_enc_region,
4075
4076         .need_emulation_on_page_fault = svm_need_emulation_on_page_fault,
4077
4078         .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4079 };
4080
4081 static struct kvm_x86_init_ops svm_init_ops __initdata = {
4082         .cpu_has_kvm_support = has_svm,
4083         .disabled_by_bios = is_disabled,
4084         .hardware_setup = svm_hardware_setup,
4085         .check_processor_compatibility = svm_check_processor_compat,
4086
4087         .runtime_ops = &svm_x86_ops,
4088 };
4089
4090 static int __init svm_init(void)
4091 {
4092         return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
4093                         __alignof__(struct vcpu_svm), THIS_MODULE);
4094 }
4095
4096 static void __exit svm_exit(void)
4097 {
4098         kvm_exit();
4099 }
4100
4101 module_init(svm_init)
4102 module_exit(svm_exit)