1 #define pr_fmt(fmt) "SVM: " fmt
3 #include <linux/kvm_host.h>
7 #include "kvm_cache_regs.h"
12 #include <linux/module.h>
13 #include <linux/mod_devicetable.h>
14 #include <linux/kernel.h>
15 #include <linux/vmalloc.h>
16 #include <linux/highmem.h>
17 #include <linux/amd-iommu.h>
18 #include <linux/sched.h>
19 #include <linux/trace_events.h>
20 #include <linux/slab.h>
21 #include <linux/hashtable.h>
22 #include <linux/objtool.h>
23 #include <linux/psp-sev.h>
24 #include <linux/file.h>
25 #include <linux/pagemap.h>
26 #include <linux/swap.h>
27 #include <linux/rwsem.h>
28 #include <linux/cc_platform.h>
31 #include <asm/perf_event.h>
32 #include <asm/tlbflush.h>
34 #include <asm/debugreg.h>
35 #include <asm/kvm_para.h>
36 #include <asm/irq_remapping.h>
37 #include <asm/spec-ctrl.h>
38 #include <asm/cpu_device_id.h>
39 #include <asm/traps.h>
40 #include <asm/fpu/api.h>
42 #include <asm/virtext.h>
48 #include "kvm_onhyperv.h"
49 #include "svm_onhyperv.h"
51 MODULE_AUTHOR("Qumranet");
52 MODULE_LICENSE("GPL");
55 static const struct x86_cpu_id svm_cpu_id[] = {
56 X86_MATCH_FEATURE(X86_FEATURE_SVM, NULL),
59 MODULE_DEVICE_TABLE(x86cpu, svm_cpu_id);
62 #define SEG_TYPE_LDT 2
63 #define SEG_TYPE_BUSY_TSS16 3
65 static bool erratum_383_found __read_mostly;
67 u32 msrpm_offsets[MSRPM_OFFSETS] __read_mostly;
70 * Set osvw_len to higher value when updated Revision Guides
71 * are published and we know what the new status bits are
73 static uint64_t osvw_len = 4, osvw_status;
75 static DEFINE_PER_CPU(u64, current_tsc_ratio);
77 #define X2APIC_MSR(x) (APIC_BASE_MSR + (x >> 4))
79 static const struct svm_direct_access_msrs {
80 u32 index; /* Index of the MSR */
81 bool always; /* True if intercept is initially cleared */
82 } direct_access_msrs[MAX_DIRECT_ACCESS_MSRS] = {
83 { .index = MSR_STAR, .always = true },
84 { .index = MSR_IA32_SYSENTER_CS, .always = true },
85 { .index = MSR_IA32_SYSENTER_EIP, .always = false },
86 { .index = MSR_IA32_SYSENTER_ESP, .always = false },
88 { .index = MSR_GS_BASE, .always = true },
89 { .index = MSR_FS_BASE, .always = true },
90 { .index = MSR_KERNEL_GS_BASE, .always = true },
91 { .index = MSR_LSTAR, .always = true },
92 { .index = MSR_CSTAR, .always = true },
93 { .index = MSR_SYSCALL_MASK, .always = true },
95 { .index = MSR_IA32_SPEC_CTRL, .always = false },
96 { .index = MSR_IA32_PRED_CMD, .always = false },
97 { .index = MSR_IA32_LASTBRANCHFROMIP, .always = false },
98 { .index = MSR_IA32_LASTBRANCHTOIP, .always = false },
99 { .index = MSR_IA32_LASTINTFROMIP, .always = false },
100 { .index = MSR_IA32_LASTINTTOIP, .always = false },
101 { .index = MSR_EFER, .always = false },
102 { .index = MSR_IA32_CR_PAT, .always = false },
103 { .index = MSR_AMD64_SEV_ES_GHCB, .always = true },
104 { .index = MSR_TSC_AUX, .always = false },
105 { .index = X2APIC_MSR(APIC_ID), .always = false },
106 { .index = X2APIC_MSR(APIC_LVR), .always = false },
107 { .index = X2APIC_MSR(APIC_TASKPRI), .always = false },
108 { .index = X2APIC_MSR(APIC_ARBPRI), .always = false },
109 { .index = X2APIC_MSR(APIC_PROCPRI), .always = false },
110 { .index = X2APIC_MSR(APIC_EOI), .always = false },
111 { .index = X2APIC_MSR(APIC_RRR), .always = false },
112 { .index = X2APIC_MSR(APIC_LDR), .always = false },
113 { .index = X2APIC_MSR(APIC_DFR), .always = false },
114 { .index = X2APIC_MSR(APIC_SPIV), .always = false },
115 { .index = X2APIC_MSR(APIC_ISR), .always = false },
116 { .index = X2APIC_MSR(APIC_TMR), .always = false },
117 { .index = X2APIC_MSR(APIC_IRR), .always = false },
118 { .index = X2APIC_MSR(APIC_ESR), .always = false },
119 { .index = X2APIC_MSR(APIC_ICR), .always = false },
120 { .index = X2APIC_MSR(APIC_ICR2), .always = false },
124 * AMD does not virtualize APIC TSC-deadline timer mode, but it is
125 * emulated by KVM. When setting APIC LVTT (0x832) register bit 18,
126 * the AVIC hardware would generate GP fault. Therefore, always
127 * intercept the MSR 0x832, and do not setup direct_access_msr.
129 { .index = X2APIC_MSR(APIC_LVTTHMR), .always = false },
130 { .index = X2APIC_MSR(APIC_LVTPC), .always = false },
131 { .index = X2APIC_MSR(APIC_LVT0), .always = false },
132 { .index = X2APIC_MSR(APIC_LVT1), .always = false },
133 { .index = X2APIC_MSR(APIC_LVTERR), .always = false },
134 { .index = X2APIC_MSR(APIC_TMICT), .always = false },
135 { .index = X2APIC_MSR(APIC_TMCCT), .always = false },
136 { .index = X2APIC_MSR(APIC_TDCR), .always = false },
137 { .index = MSR_INVALID, .always = false },
141 * These 2 parameters are used to config the controls for Pause-Loop Exiting:
142 * pause_filter_count: On processors that support Pause filtering(indicated
143 * by CPUID Fn8000_000A_EDX), the VMCB provides a 16 bit pause filter
144 * count value. On VMRUN this value is loaded into an internal counter.
145 * Each time a pause instruction is executed, this counter is decremented
146 * until it reaches zero at which time a #VMEXIT is generated if pause
147 * intercept is enabled. Refer to AMD APM Vol 2 Section 15.14.4 Pause
148 * Intercept Filtering for more details.
149 * This also indicate if ple logic enabled.
151 * pause_filter_thresh: In addition, some processor families support advanced
152 * pause filtering (indicated by CPUID Fn8000_000A_EDX) upper bound on
153 * the amount of time a guest is allowed to execute in a pause loop.
154 * In this mode, a 16-bit pause filter threshold field is added in the
155 * VMCB. The threshold value is a cycle count that is used to reset the
156 * pause counter. As with simple pause filtering, VMRUN loads the pause
157 * count value from VMCB into an internal counter. Then, on each pause
158 * instruction the hardware checks the elapsed number of cycles since
159 * the most recent pause instruction against the pause filter threshold.
160 * If the elapsed cycle count is greater than the pause filter threshold,
161 * then the internal pause count is reloaded from the VMCB and execution
162 * continues. If the elapsed cycle count is less than the pause filter
163 * threshold, then the internal pause count is decremented. If the count
164 * value is less than zero and PAUSE intercept is enabled, a #VMEXIT is
165 * triggered. If advanced pause filtering is supported and pause filter
166 * threshold field is set to zero, the filter will operate in the simpler,
170 static unsigned short pause_filter_thresh = KVM_DEFAULT_PLE_GAP;
171 module_param(pause_filter_thresh, ushort, 0444);
173 static unsigned short pause_filter_count = KVM_SVM_DEFAULT_PLE_WINDOW;
174 module_param(pause_filter_count, ushort, 0444);
176 /* Default doubles per-vcpu window every exit. */
177 static unsigned short pause_filter_count_grow = KVM_DEFAULT_PLE_WINDOW_GROW;
178 module_param(pause_filter_count_grow, ushort, 0444);
180 /* Default resets per-vcpu window every exit to pause_filter_count. */
181 static unsigned short pause_filter_count_shrink = KVM_DEFAULT_PLE_WINDOW_SHRINK;
182 module_param(pause_filter_count_shrink, ushort, 0444);
184 /* Default is to compute the maximum so we can never overflow. */
185 static unsigned short pause_filter_count_max = KVM_SVM_DEFAULT_PLE_WINDOW_MAX;
186 module_param(pause_filter_count_max, ushort, 0444);
189 * Use nested page tables by default. Note, NPT may get forced off by
190 * svm_hardware_setup() if it's unsupported by hardware or the host kernel.
192 bool npt_enabled = true;
193 module_param_named(npt, npt_enabled, bool, 0444);
195 /* allow nested virtualization in KVM/SVM */
196 static int nested = true;
197 module_param(nested, int, S_IRUGO);
199 /* enable/disable Next RIP Save */
200 static int nrips = true;
201 module_param(nrips, int, 0444);
203 /* enable/disable Virtual VMLOAD VMSAVE */
204 static int vls = true;
205 module_param(vls, int, 0444);
207 /* enable/disable Virtual GIF */
209 module_param(vgif, int, 0444);
211 /* enable/disable LBR virtualization */
212 static int lbrv = true;
213 module_param(lbrv, int, 0444);
215 static int tsc_scaling = true;
216 module_param(tsc_scaling, int, 0444);
219 * enable / disable AVIC. Because the defaults differ for APICv
220 * support between VMX and SVM we cannot use module_param_named.
223 module_param(avic, bool, 0444);
225 bool __read_mostly dump_invalid_vmcb;
226 module_param(dump_invalid_vmcb, bool, 0644);
229 bool intercept_smi = true;
230 module_param(intercept_smi, bool, 0444);
233 static bool svm_gp_erratum_intercept = true;
235 static u8 rsm_ins_bytes[] = "\x0f\xaa";
237 static unsigned long iopm_base;
239 struct kvm_ldttss_desc {
242 unsigned base1:8, type:5, dpl:2, p:1;
243 unsigned limit1:4, zero0:3, g:1, base2:8;
246 } __attribute__((packed));
248 DEFINE_PER_CPU(struct svm_cpu_data *, svm_data);
251 * Only MSR_TSC_AUX is switched via the user return hook. EFER is switched via
252 * the VMCB, and the SYSCALL/SYSENTER MSRs are handled by VMLOAD/VMSAVE.
254 * RDTSCP and RDPID are not used in the kernel, specifically to allow KVM to
255 * defer the restoration of TSC_AUX until the CPU returns to userspace.
257 static int tsc_aux_uret_slot __read_mostly = -1;
259 static const u32 msrpm_ranges[] = {0, 0xc0000000, 0xc0010000};
261 #define NUM_MSR_MAPS ARRAY_SIZE(msrpm_ranges)
262 #define MSRS_RANGE_SIZE 2048
263 #define MSRS_IN_RANGE (MSRS_RANGE_SIZE * 8 / 2)
265 u32 svm_msrpm_offset(u32 msr)
270 for (i = 0; i < NUM_MSR_MAPS; i++) {
271 if (msr < msrpm_ranges[i] ||
272 msr >= msrpm_ranges[i] + MSRS_IN_RANGE)
275 offset = (msr - msrpm_ranges[i]) / 4; /* 4 msrs per u8 */
276 offset += (i * MSRS_RANGE_SIZE); /* add range offset */
278 /* Now we have the u8 offset - but need the u32 offset */
282 /* MSR not in any range */
286 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu);
288 static int get_npt_level(void)
291 return pgtable_l5_enabled() ? PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
293 return PT32E_ROOT_LEVEL;
297 int svm_set_efer(struct kvm_vcpu *vcpu, u64 efer)
299 struct vcpu_svm *svm = to_svm(vcpu);
300 u64 old_efer = vcpu->arch.efer;
301 vcpu->arch.efer = efer;
304 /* Shadow paging assumes NX to be available. */
307 if (!(efer & EFER_LMA))
311 if ((old_efer & EFER_SVME) != (efer & EFER_SVME)) {
312 if (!(efer & EFER_SVME)) {
313 svm_leave_nested(vcpu);
314 svm_set_gif(svm, true);
315 /* #GP intercept is still needed for vmware backdoor */
316 if (!enable_vmware_backdoor)
317 clr_exception_intercept(svm, GP_VECTOR);
320 * Free the nested guest state, unless we are in SMM.
321 * In this case we will return to the nested guest
322 * as soon as we leave SMM.
325 svm_free_nested(svm);
328 int ret = svm_allocate_nested(svm);
331 vcpu->arch.efer = old_efer;
336 * Never intercept #GP for SEV guests, KVM can't
337 * decrypt guest memory to workaround the erratum.
339 if (svm_gp_erratum_intercept && !sev_guest(vcpu->kvm))
340 set_exception_intercept(svm, GP_VECTOR);
344 svm->vmcb->save.efer = efer | EFER_SVME;
345 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
349 static int is_external_interrupt(u32 info)
351 info &= SVM_EVTINJ_TYPE_MASK | SVM_EVTINJ_VALID;
352 return info == (SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_INTR);
355 static u32 svm_get_interrupt_shadow(struct kvm_vcpu *vcpu)
357 struct vcpu_svm *svm = to_svm(vcpu);
360 if (svm->vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK)
361 ret = KVM_X86_SHADOW_INT_STI | KVM_X86_SHADOW_INT_MOV_SS;
365 static void svm_set_interrupt_shadow(struct kvm_vcpu *vcpu, int mask)
367 struct vcpu_svm *svm = to_svm(vcpu);
370 svm->vmcb->control.int_state &= ~SVM_INTERRUPT_SHADOW_MASK;
372 svm->vmcb->control.int_state |= SVM_INTERRUPT_SHADOW_MASK;
376 static int __svm_skip_emulated_instruction(struct kvm_vcpu *vcpu,
377 bool commit_side_effects)
379 struct vcpu_svm *svm = to_svm(vcpu);
380 unsigned long old_rflags;
383 * SEV-ES does not expose the next RIP. The RIP update is controlled by
384 * the type of exit and the #VC handler in the guest.
386 if (sev_es_guest(vcpu->kvm))
389 if (nrips && svm->vmcb->control.next_rip != 0) {
390 WARN_ON_ONCE(!static_cpu_has(X86_FEATURE_NRIPS));
391 svm->next_rip = svm->vmcb->control.next_rip;
394 if (!svm->next_rip) {
395 if (unlikely(!commit_side_effects))
396 old_rflags = svm->vmcb->save.rflags;
398 if (!kvm_emulate_instruction(vcpu, EMULTYPE_SKIP))
401 if (unlikely(!commit_side_effects))
402 svm->vmcb->save.rflags = old_rflags;
404 kvm_rip_write(vcpu, svm->next_rip);
408 if (likely(commit_side_effects))
409 svm_set_interrupt_shadow(vcpu, 0);
414 static int svm_skip_emulated_instruction(struct kvm_vcpu *vcpu)
416 return __svm_skip_emulated_instruction(vcpu, true);
419 static int svm_update_soft_interrupt_rip(struct kvm_vcpu *vcpu)
421 unsigned long rip, old_rip = kvm_rip_read(vcpu);
422 struct vcpu_svm *svm = to_svm(vcpu);
425 * Due to architectural shortcomings, the CPU doesn't always provide
426 * NextRIP, e.g. if KVM intercepted an exception that occurred while
427 * the CPU was vectoring an INTO/INT3 in the guest. Temporarily skip
428 * the instruction even if NextRIP is supported to acquire the next
429 * RIP so that it can be shoved into the NextRIP field, otherwise
430 * hardware will fail to advance guest RIP during event injection.
431 * Drop the exception/interrupt if emulation fails and effectively
432 * retry the instruction, it's the least awful option. If NRIPS is
433 * in use, the skip must not commit any side effects such as clearing
434 * the interrupt shadow or RFLAGS.RF.
436 if (!__svm_skip_emulated_instruction(vcpu, !nrips))
439 rip = kvm_rip_read(vcpu);
442 * Save the injection information, even when using next_rip, as the
443 * VMCB's next_rip will be lost (cleared on VM-Exit) if the injection
444 * doesn't complete due to a VM-Exit occurring while the CPU is
445 * vectoring the event. Decoding the instruction isn't guaranteed to
446 * work as there may be no backing instruction, e.g. if the event is
447 * being injected by L1 for L2, or if the guest is patching INT3 into
448 * a different instruction.
450 svm->soft_int_injected = true;
451 svm->soft_int_csbase = svm->vmcb->save.cs.base;
452 svm->soft_int_old_rip = old_rip;
453 svm->soft_int_next_rip = rip;
456 kvm_rip_write(vcpu, old_rip);
458 if (static_cpu_has(X86_FEATURE_NRIPS))
459 svm->vmcb->control.next_rip = rip;
464 static void svm_queue_exception(struct kvm_vcpu *vcpu)
466 struct vcpu_svm *svm = to_svm(vcpu);
467 unsigned nr = vcpu->arch.exception.nr;
468 bool has_error_code = vcpu->arch.exception.has_error_code;
469 u32 error_code = vcpu->arch.exception.error_code;
471 kvm_deliver_exception_payload(vcpu);
473 if (kvm_exception_is_soft(nr) &&
474 svm_update_soft_interrupt_rip(vcpu))
477 svm->vmcb->control.event_inj = nr
479 | (has_error_code ? SVM_EVTINJ_VALID_ERR : 0)
480 | SVM_EVTINJ_TYPE_EXEPT;
481 svm->vmcb->control.event_inj_err = error_code;
484 static void svm_init_erratum_383(void)
490 if (!static_cpu_has_bug(X86_BUG_AMD_TLB_MMATCH))
493 /* Use _safe variants to not break nested virtualization */
494 val = native_read_msr_safe(MSR_AMD64_DC_CFG, &err);
500 low = lower_32_bits(val);
501 high = upper_32_bits(val);
503 native_write_msr_safe(MSR_AMD64_DC_CFG, low, high);
505 erratum_383_found = true;
508 static void svm_init_osvw(struct kvm_vcpu *vcpu)
511 * Guests should see errata 400 and 415 as fixed (assuming that
512 * HLT and IO instructions are intercepted).
514 vcpu->arch.osvw.length = (osvw_len >= 3) ? (osvw_len) : 3;
515 vcpu->arch.osvw.status = osvw_status & ~(6ULL);
518 * By increasing VCPU's osvw.length to 3 we are telling the guest that
519 * all osvw.status bits inside that length, including bit 0 (which is
520 * reserved for erratum 298), are valid. However, if host processor's
521 * osvw_len is 0 then osvw_status[0] carries no information. We need to
522 * be conservative here and therefore we tell the guest that erratum 298
523 * is present (because we really don't know).
525 if (osvw_len == 0 && boot_cpu_data.x86 == 0x10)
526 vcpu->arch.osvw.status |= 1;
529 static int has_svm(void)
533 if (!cpu_has_svm(&msg)) {
534 printk(KERN_INFO "has_svm: %s\n", msg);
538 if (cc_platform_has(CC_ATTR_GUEST_MEM_ENCRYPT)) {
539 pr_info("KVM is unsupported when running as an SEV guest\n");
546 void __svm_write_tsc_multiplier(u64 multiplier)
550 if (multiplier == __this_cpu_read(current_tsc_ratio))
553 wrmsrl(MSR_AMD64_TSC_RATIO, multiplier);
554 __this_cpu_write(current_tsc_ratio, multiplier);
559 static void svm_hardware_disable(void)
561 /* Make sure we clean up behind us */
563 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
567 amd_pmu_disable_virt();
570 static int svm_hardware_enable(void)
573 struct svm_cpu_data *sd;
575 struct desc_struct *gdt;
576 int me = raw_smp_processor_id();
578 rdmsrl(MSR_EFER, efer);
579 if (efer & EFER_SVME)
583 pr_err("%s: err EOPNOTSUPP on %d\n", __func__, me);
586 sd = per_cpu(svm_data, me);
588 pr_err("%s: svm_data is NULL on %d\n", __func__, me);
592 sd->asid_generation = 1;
593 sd->max_asid = cpuid_ebx(SVM_CPUID_FUNC) - 1;
594 sd->next_asid = sd->max_asid + 1;
595 sd->min_asid = max_sev_asid + 1;
597 gdt = get_current_gdt_rw();
598 sd->tss_desc = (struct kvm_ldttss_desc *)(gdt + GDT_ENTRY_TSS);
600 wrmsrl(MSR_EFER, efer | EFER_SVME);
602 wrmsrl(MSR_VM_HSAVE_PA, __sme_page_pa(sd->save_area));
604 if (static_cpu_has(X86_FEATURE_TSCRATEMSR)) {
606 * Set the default value, even if we don't use TSC scaling
607 * to avoid having stale value in the msr
609 __svm_write_tsc_multiplier(SVM_TSC_RATIO_DEFAULT);
616 * Note that it is possible to have a system with mixed processor
617 * revisions and therefore different OSVW bits. If bits are not the same
618 * on different processors then choose the worst case (i.e. if erratum
619 * is present on one processor and not on another then assume that the
620 * erratum is present everywhere).
622 if (cpu_has(&boot_cpu_data, X86_FEATURE_OSVW)) {
623 uint64_t len, status = 0;
626 len = native_read_msr_safe(MSR_AMD64_OSVW_ID_LENGTH, &err);
628 status = native_read_msr_safe(MSR_AMD64_OSVW_STATUS,
632 osvw_status = osvw_len = 0;
636 osvw_status |= status;
637 osvw_status &= (1ULL << osvw_len) - 1;
640 osvw_status = osvw_len = 0;
642 svm_init_erratum_383();
644 amd_pmu_enable_virt();
649 static void svm_cpu_uninit(int cpu)
651 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
656 per_cpu(svm_data, cpu) = NULL;
657 kfree(sd->sev_vmcbs);
658 __free_page(sd->save_area);
662 static int svm_cpu_init(int cpu)
664 struct svm_cpu_data *sd;
667 sd = kzalloc(sizeof(struct svm_cpu_data), GFP_KERNEL);
671 sd->save_area = alloc_page(GFP_KERNEL | __GFP_ZERO);
675 ret = sev_cpu_init(sd);
679 per_cpu(svm_data, cpu) = sd;
684 __free_page(sd->save_area);
691 static int direct_access_msr_slot(u32 msr)
695 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++)
696 if (direct_access_msrs[i].index == msr)
702 static void set_shadow_msr_intercept(struct kvm_vcpu *vcpu, u32 msr, int read,
705 struct vcpu_svm *svm = to_svm(vcpu);
706 int slot = direct_access_msr_slot(msr);
711 /* Set the shadow bitmaps to the desired intercept states */
713 set_bit(slot, svm->shadow_msr_intercept.read);
715 clear_bit(slot, svm->shadow_msr_intercept.read);
718 set_bit(slot, svm->shadow_msr_intercept.write);
720 clear_bit(slot, svm->shadow_msr_intercept.write);
723 static bool valid_msr_intercept(u32 index)
725 return direct_access_msr_slot(index) != -ENOENT;
728 static bool msr_write_intercepted(struct kvm_vcpu *vcpu, u32 msr)
735 msrpm = is_guest_mode(vcpu) ? to_svm(vcpu)->nested.msrpm:
738 offset = svm_msrpm_offset(msr);
739 bit_write = 2 * (msr & 0x0f) + 1;
742 BUG_ON(offset == MSR_INVALID);
744 return !!test_bit(bit_write, &tmp);
747 static void set_msr_interception_bitmap(struct kvm_vcpu *vcpu, u32 *msrpm,
748 u32 msr, int read, int write)
750 struct vcpu_svm *svm = to_svm(vcpu);
751 u8 bit_read, bit_write;
756 * If this warning triggers extend the direct_access_msrs list at the
757 * beginning of the file
759 WARN_ON(!valid_msr_intercept(msr));
761 /* Enforce non allowed MSRs to trap */
762 if (read && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_READ))
765 if (write && !kvm_msr_allowed(vcpu, msr, KVM_MSR_FILTER_WRITE))
768 offset = svm_msrpm_offset(msr);
769 bit_read = 2 * (msr & 0x0f);
770 bit_write = 2 * (msr & 0x0f) + 1;
773 BUG_ON(offset == MSR_INVALID);
775 read ? clear_bit(bit_read, &tmp) : set_bit(bit_read, &tmp);
776 write ? clear_bit(bit_write, &tmp) : set_bit(bit_write, &tmp);
780 svm_hv_vmcb_dirty_nested_enlightenments(vcpu);
781 svm->nested.force_msr_bitmap_recalc = true;
784 void set_msr_interception(struct kvm_vcpu *vcpu, u32 *msrpm, u32 msr,
787 set_shadow_msr_intercept(vcpu, msr, read, write);
788 set_msr_interception_bitmap(vcpu, msrpm, msr, read, write);
791 u32 *svm_vcpu_alloc_msrpm(void)
793 unsigned int order = get_order(MSRPM_SIZE);
794 struct page *pages = alloc_pages(GFP_KERNEL_ACCOUNT, order);
800 msrpm = page_address(pages);
801 memset(msrpm, 0xff, PAGE_SIZE * (1 << order));
806 void svm_vcpu_init_msrpm(struct kvm_vcpu *vcpu, u32 *msrpm)
810 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
811 if (!direct_access_msrs[i].always)
813 set_msr_interception(vcpu, msrpm, direct_access_msrs[i].index, 1, 1);
817 void svm_set_x2apic_msr_interception(struct vcpu_svm *svm, bool intercept)
821 if (intercept == svm->x2avic_msrs_intercepted)
824 if (avic_mode != AVIC_MODE_X2 ||
825 !apic_x2apic_mode(svm->vcpu.arch.apic))
828 for (i = 0; i < MAX_DIRECT_ACCESS_MSRS; i++) {
829 int index = direct_access_msrs[i].index;
831 if ((index < APIC_BASE_MSR) ||
832 (index > APIC_BASE_MSR + 0xff))
834 set_msr_interception(&svm->vcpu, svm->msrpm, index,
835 !intercept, !intercept);
838 svm->x2avic_msrs_intercepted = intercept;
841 void svm_vcpu_free_msrpm(u32 *msrpm)
843 __free_pages(virt_to_page(msrpm), get_order(MSRPM_SIZE));
846 static void svm_msr_filter_changed(struct kvm_vcpu *vcpu)
848 struct vcpu_svm *svm = to_svm(vcpu);
852 * Set intercept permissions for all direct access MSRs again. They
853 * will automatically get filtered through the MSR filter, so we are
854 * back in sync after this.
856 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
857 u32 msr = direct_access_msrs[i].index;
858 u32 read = test_bit(i, svm->shadow_msr_intercept.read);
859 u32 write = test_bit(i, svm->shadow_msr_intercept.write);
861 set_msr_interception_bitmap(vcpu, svm->msrpm, msr, read, write);
865 static void add_msr_offset(u32 offset)
869 for (i = 0; i < MSRPM_OFFSETS; ++i) {
871 /* Offset already in list? */
872 if (msrpm_offsets[i] == offset)
875 /* Slot used by another offset? */
876 if (msrpm_offsets[i] != MSR_INVALID)
879 /* Add offset to list */
880 msrpm_offsets[i] = offset;
886 * If this BUG triggers the msrpm_offsets table has an overflow. Just
887 * increase MSRPM_OFFSETS in this case.
892 static void init_msrpm_offsets(void)
896 memset(msrpm_offsets, 0xff, sizeof(msrpm_offsets));
898 for (i = 0; direct_access_msrs[i].index != MSR_INVALID; i++) {
901 offset = svm_msrpm_offset(direct_access_msrs[i].index);
902 BUG_ON(offset == MSR_INVALID);
904 add_msr_offset(offset);
908 void svm_copy_lbrs(struct vmcb *to_vmcb, struct vmcb *from_vmcb)
910 to_vmcb->save.dbgctl = from_vmcb->save.dbgctl;
911 to_vmcb->save.br_from = from_vmcb->save.br_from;
912 to_vmcb->save.br_to = from_vmcb->save.br_to;
913 to_vmcb->save.last_excp_from = from_vmcb->save.last_excp_from;
914 to_vmcb->save.last_excp_to = from_vmcb->save.last_excp_to;
916 vmcb_mark_dirty(to_vmcb, VMCB_LBR);
919 static void svm_enable_lbrv(struct kvm_vcpu *vcpu)
921 struct vcpu_svm *svm = to_svm(vcpu);
923 svm->vmcb->control.virt_ext |= LBR_CTL_ENABLE_MASK;
924 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 1, 1);
925 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 1, 1);
926 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 1, 1);
927 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 1, 1);
929 /* Move the LBR msrs to the vmcb02 so that the guest can see them. */
930 if (is_guest_mode(vcpu))
931 svm_copy_lbrs(svm->vmcb, svm->vmcb01.ptr);
934 static void svm_disable_lbrv(struct kvm_vcpu *vcpu)
936 struct vcpu_svm *svm = to_svm(vcpu);
938 svm->vmcb->control.virt_ext &= ~LBR_CTL_ENABLE_MASK;
939 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHFROMIP, 0, 0);
940 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTBRANCHTOIP, 0, 0);
941 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTFROMIP, 0, 0);
942 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_LASTINTTOIP, 0, 0);
945 * Move the LBR msrs back to the vmcb01 to avoid copying them
946 * on nested guest entries.
948 if (is_guest_mode(vcpu))
949 svm_copy_lbrs(svm->vmcb01.ptr, svm->vmcb);
952 static int svm_get_lbr_msr(struct vcpu_svm *svm, u32 index)
955 * If the LBR virtualization is disabled, the LBR msrs are always
956 * kept in the vmcb01 to avoid copying them on nested guest entries.
958 * If nested, and the LBR virtualization is enabled/disabled, the msrs
959 * are moved between the vmcb01 and vmcb02 as needed.
962 (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK) ?
963 svm->vmcb : svm->vmcb01.ptr;
966 case MSR_IA32_DEBUGCTLMSR:
967 return vmcb->save.dbgctl;
968 case MSR_IA32_LASTBRANCHFROMIP:
969 return vmcb->save.br_from;
970 case MSR_IA32_LASTBRANCHTOIP:
971 return vmcb->save.br_to;
972 case MSR_IA32_LASTINTFROMIP:
973 return vmcb->save.last_excp_from;
974 case MSR_IA32_LASTINTTOIP:
975 return vmcb->save.last_excp_to;
977 KVM_BUG(false, svm->vcpu.kvm,
978 "%s: Unknown MSR 0x%x", __func__, index);
983 void svm_update_lbrv(struct kvm_vcpu *vcpu)
985 struct vcpu_svm *svm = to_svm(vcpu);
987 bool enable_lbrv = svm_get_lbr_msr(svm, MSR_IA32_DEBUGCTLMSR) &
990 bool current_enable_lbrv = !!(svm->vmcb->control.virt_ext &
991 LBR_CTL_ENABLE_MASK);
993 if (unlikely(is_guest_mode(vcpu) && svm->lbrv_enabled))
994 if (unlikely(svm->nested.ctl.virt_ext & LBR_CTL_ENABLE_MASK))
997 if (enable_lbrv == current_enable_lbrv)
1001 svm_enable_lbrv(vcpu);
1003 svm_disable_lbrv(vcpu);
1006 void disable_nmi_singlestep(struct vcpu_svm *svm)
1008 svm->nmi_singlestep = false;
1010 if (!(svm->vcpu.guest_debug & KVM_GUESTDBG_SINGLESTEP)) {
1011 /* Clear our flags if they were not set by the guest */
1012 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1013 svm->vmcb->save.rflags &= ~X86_EFLAGS_TF;
1014 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1015 svm->vmcb->save.rflags &= ~X86_EFLAGS_RF;
1019 static void grow_ple_window(struct kvm_vcpu *vcpu)
1021 struct vcpu_svm *svm = to_svm(vcpu);
1022 struct vmcb_control_area *control = &svm->vmcb->control;
1023 int old = control->pause_filter_count;
1025 if (kvm_pause_in_guest(vcpu->kvm))
1028 control->pause_filter_count = __grow_ple_window(old,
1030 pause_filter_count_grow,
1031 pause_filter_count_max);
1033 if (control->pause_filter_count != old) {
1034 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1035 trace_kvm_ple_window_update(vcpu->vcpu_id,
1036 control->pause_filter_count, old);
1040 static void shrink_ple_window(struct kvm_vcpu *vcpu)
1042 struct vcpu_svm *svm = to_svm(vcpu);
1043 struct vmcb_control_area *control = &svm->vmcb->control;
1044 int old = control->pause_filter_count;
1046 if (kvm_pause_in_guest(vcpu->kvm))
1049 control->pause_filter_count =
1050 __shrink_ple_window(old,
1052 pause_filter_count_shrink,
1053 pause_filter_count);
1054 if (control->pause_filter_count != old) {
1055 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1056 trace_kvm_ple_window_update(vcpu->vcpu_id,
1057 control->pause_filter_count, old);
1061 static void svm_hardware_unsetup(void)
1065 sev_hardware_unsetup();
1067 for_each_possible_cpu(cpu)
1068 svm_cpu_uninit(cpu);
1070 __free_pages(pfn_to_page(iopm_base >> PAGE_SHIFT),
1071 get_order(IOPM_SIZE));
1075 static void init_seg(struct vmcb_seg *seg)
1078 seg->attrib = SVM_SELECTOR_P_MASK | SVM_SELECTOR_S_MASK |
1079 SVM_SELECTOR_WRITE_MASK; /* Read/Write Data Segment */
1080 seg->limit = 0xffff;
1084 static void init_sys_seg(struct vmcb_seg *seg, uint32_t type)
1087 seg->attrib = SVM_SELECTOR_P_MASK | type;
1088 seg->limit = 0xffff;
1092 static u64 svm_get_l2_tsc_offset(struct kvm_vcpu *vcpu)
1094 struct vcpu_svm *svm = to_svm(vcpu);
1096 return svm->nested.ctl.tsc_offset;
1099 static u64 svm_get_l2_tsc_multiplier(struct kvm_vcpu *vcpu)
1101 struct vcpu_svm *svm = to_svm(vcpu);
1103 return svm->tsc_ratio_msr;
1106 static void svm_write_tsc_offset(struct kvm_vcpu *vcpu, u64 offset)
1108 struct vcpu_svm *svm = to_svm(vcpu);
1110 svm->vmcb01.ptr->control.tsc_offset = vcpu->arch.l1_tsc_offset;
1111 svm->vmcb->control.tsc_offset = offset;
1112 vmcb_mark_dirty(svm->vmcb, VMCB_INTERCEPTS);
1115 static void svm_write_tsc_multiplier(struct kvm_vcpu *vcpu, u64 multiplier)
1117 __svm_write_tsc_multiplier(multiplier);
1121 /* Evaluate instruction intercepts that depend on guest CPUID features. */
1122 static void svm_recalc_instruction_intercepts(struct kvm_vcpu *vcpu,
1123 struct vcpu_svm *svm)
1126 * Intercept INVPCID if shadow paging is enabled to sync/free shadow
1127 * roots, or if INVPCID is disabled in the guest to inject #UD.
1129 if (kvm_cpu_cap_has(X86_FEATURE_INVPCID)) {
1131 !guest_cpuid_has(&svm->vcpu, X86_FEATURE_INVPCID))
1132 svm_set_intercept(svm, INTERCEPT_INVPCID);
1134 svm_clr_intercept(svm, INTERCEPT_INVPCID);
1137 if (kvm_cpu_cap_has(X86_FEATURE_RDTSCP)) {
1138 if (guest_cpuid_has(vcpu, X86_FEATURE_RDTSCP))
1139 svm_clr_intercept(svm, INTERCEPT_RDTSCP);
1141 svm_set_intercept(svm, INTERCEPT_RDTSCP);
1145 static inline void init_vmcb_after_set_cpuid(struct kvm_vcpu *vcpu)
1147 struct vcpu_svm *svm = to_svm(vcpu);
1149 if (guest_cpuid_is_intel(vcpu)) {
1151 * We must intercept SYSENTER_EIP and SYSENTER_ESP
1152 * accesses because the processor only stores 32 bits.
1153 * For the same reason we cannot use virtual VMLOAD/VMSAVE.
1155 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1156 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1157 svm->vmcb->control.virt_ext &= ~VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1159 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 0, 0);
1160 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 0, 0);
1162 svm->v_vmload_vmsave_enabled = false;
1165 * If hardware supports Virtual VMLOAD VMSAVE then enable it
1166 * in VMCB and clear intercepts to avoid #VMEXIT.
1169 svm_clr_intercept(svm, INTERCEPT_VMLOAD);
1170 svm_clr_intercept(svm, INTERCEPT_VMSAVE);
1171 svm->vmcb->control.virt_ext |= VIRTUAL_VMLOAD_VMSAVE_ENABLE_MASK;
1173 /* No need to intercept these MSRs */
1174 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_EIP, 1, 1);
1175 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SYSENTER_ESP, 1, 1);
1179 static void init_vmcb(struct kvm_vcpu *vcpu)
1181 struct vcpu_svm *svm = to_svm(vcpu);
1182 struct vmcb *vmcb = svm->vmcb01.ptr;
1183 struct vmcb_control_area *control = &vmcb->control;
1184 struct vmcb_save_area *save = &vmcb->save;
1186 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1187 svm_set_intercept(svm, INTERCEPT_CR3_READ);
1188 svm_set_intercept(svm, INTERCEPT_CR4_READ);
1189 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1190 svm_set_intercept(svm, INTERCEPT_CR3_WRITE);
1191 svm_set_intercept(svm, INTERCEPT_CR4_WRITE);
1192 if (!kvm_vcpu_apicv_active(vcpu))
1193 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
1195 set_dr_intercepts(svm);
1197 set_exception_intercept(svm, PF_VECTOR);
1198 set_exception_intercept(svm, UD_VECTOR);
1199 set_exception_intercept(svm, MC_VECTOR);
1200 set_exception_intercept(svm, AC_VECTOR);
1201 set_exception_intercept(svm, DB_VECTOR);
1203 * Guest access to VMware backdoor ports could legitimately
1204 * trigger #GP because of TSS I/O permission bitmap.
1205 * We intercept those #GP and allow access to them anyway
1206 * as VMware does. Don't intercept #GP for SEV guests as KVM can't
1207 * decrypt guest memory to decode the faulting instruction.
1209 if (enable_vmware_backdoor && !sev_guest(vcpu->kvm))
1210 set_exception_intercept(svm, GP_VECTOR);
1212 svm_set_intercept(svm, INTERCEPT_INTR);
1213 svm_set_intercept(svm, INTERCEPT_NMI);
1216 svm_set_intercept(svm, INTERCEPT_SMI);
1218 svm_set_intercept(svm, INTERCEPT_SELECTIVE_CR0);
1219 svm_set_intercept(svm, INTERCEPT_RDPMC);
1220 svm_set_intercept(svm, INTERCEPT_CPUID);
1221 svm_set_intercept(svm, INTERCEPT_INVD);
1222 svm_set_intercept(svm, INTERCEPT_INVLPG);
1223 svm_set_intercept(svm, INTERCEPT_INVLPGA);
1224 svm_set_intercept(svm, INTERCEPT_IOIO_PROT);
1225 svm_set_intercept(svm, INTERCEPT_MSR_PROT);
1226 svm_set_intercept(svm, INTERCEPT_TASK_SWITCH);
1227 svm_set_intercept(svm, INTERCEPT_SHUTDOWN);
1228 svm_set_intercept(svm, INTERCEPT_VMRUN);
1229 svm_set_intercept(svm, INTERCEPT_VMMCALL);
1230 svm_set_intercept(svm, INTERCEPT_VMLOAD);
1231 svm_set_intercept(svm, INTERCEPT_VMSAVE);
1232 svm_set_intercept(svm, INTERCEPT_STGI);
1233 svm_set_intercept(svm, INTERCEPT_CLGI);
1234 svm_set_intercept(svm, INTERCEPT_SKINIT);
1235 svm_set_intercept(svm, INTERCEPT_WBINVD);
1236 svm_set_intercept(svm, INTERCEPT_XSETBV);
1237 svm_set_intercept(svm, INTERCEPT_RDPRU);
1238 svm_set_intercept(svm, INTERCEPT_RSM);
1240 if (!kvm_mwait_in_guest(vcpu->kvm)) {
1241 svm_set_intercept(svm, INTERCEPT_MONITOR);
1242 svm_set_intercept(svm, INTERCEPT_MWAIT);
1245 if (!kvm_hlt_in_guest(vcpu->kvm))
1246 svm_set_intercept(svm, INTERCEPT_HLT);
1248 control->iopm_base_pa = __sme_set(iopm_base);
1249 control->msrpm_base_pa = __sme_set(__pa(svm->msrpm));
1250 control->int_ctl = V_INTR_MASKING_MASK;
1252 init_seg(&save->es);
1253 init_seg(&save->ss);
1254 init_seg(&save->ds);
1255 init_seg(&save->fs);
1256 init_seg(&save->gs);
1258 save->cs.selector = 0xf000;
1259 save->cs.base = 0xffff0000;
1260 /* Executable/Readable Code Segment */
1261 save->cs.attrib = SVM_SELECTOR_READ_MASK | SVM_SELECTOR_P_MASK |
1262 SVM_SELECTOR_S_MASK | SVM_SELECTOR_CODE_MASK;
1263 save->cs.limit = 0xffff;
1265 save->gdtr.base = 0;
1266 save->gdtr.limit = 0xffff;
1267 save->idtr.base = 0;
1268 save->idtr.limit = 0xffff;
1270 init_sys_seg(&save->ldtr, SEG_TYPE_LDT);
1271 init_sys_seg(&save->tr, SEG_TYPE_BUSY_TSS16);
1274 /* Setup VMCB for Nested Paging */
1275 control->nested_ctl |= SVM_NESTED_CTL_NP_ENABLE;
1276 svm_clr_intercept(svm, INTERCEPT_INVLPG);
1277 clr_exception_intercept(svm, PF_VECTOR);
1278 svm_clr_intercept(svm, INTERCEPT_CR3_READ);
1279 svm_clr_intercept(svm, INTERCEPT_CR3_WRITE);
1280 save->g_pat = vcpu->arch.pat;
1283 svm->current_vmcb->asid_generation = 0;
1286 svm->nested.vmcb12_gpa = INVALID_GPA;
1287 svm->nested.last_vmcb12_gpa = INVALID_GPA;
1289 if (!kvm_pause_in_guest(vcpu->kvm)) {
1290 control->pause_filter_count = pause_filter_count;
1291 if (pause_filter_thresh)
1292 control->pause_filter_thresh = pause_filter_thresh;
1293 svm_set_intercept(svm, INTERCEPT_PAUSE);
1295 svm_clr_intercept(svm, INTERCEPT_PAUSE);
1298 svm_recalc_instruction_intercepts(vcpu, svm);
1301 * If the host supports V_SPEC_CTRL then disable the interception
1302 * of MSR_IA32_SPEC_CTRL.
1304 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
1305 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
1307 if (kvm_vcpu_apicv_active(vcpu))
1308 avic_init_vmcb(svm, vmcb);
1311 svm_clr_intercept(svm, INTERCEPT_STGI);
1312 svm_clr_intercept(svm, INTERCEPT_CLGI);
1313 svm->vmcb->control.int_ctl |= V_GIF_ENABLE_MASK;
1316 if (sev_guest(vcpu->kvm)) {
1317 svm->vmcb->control.nested_ctl |= SVM_NESTED_CTL_SEV_ENABLE;
1318 clr_exception_intercept(svm, UD_VECTOR);
1320 if (sev_es_guest(vcpu->kvm)) {
1321 /* Perform SEV-ES specific VMCB updates */
1322 sev_es_init_vmcb(svm);
1326 svm_hv_init_vmcb(vmcb);
1327 init_vmcb_after_set_cpuid(vcpu);
1329 vmcb_mark_all_dirty(vmcb);
1334 static void __svm_vcpu_reset(struct kvm_vcpu *vcpu)
1336 struct vcpu_svm *svm = to_svm(vcpu);
1338 svm_vcpu_init_msrpm(vcpu, svm->msrpm);
1340 svm_init_osvw(vcpu);
1341 vcpu->arch.microcode_version = 0x01000065;
1342 svm->tsc_ratio_msr = kvm_caps.default_tsc_scaling_ratio;
1344 if (sev_es_guest(vcpu->kvm))
1345 sev_es_vcpu_reset(svm);
1348 static void svm_vcpu_reset(struct kvm_vcpu *vcpu, bool init_event)
1350 struct vcpu_svm *svm = to_svm(vcpu);
1353 svm->virt_spec_ctrl = 0;
1358 __svm_vcpu_reset(vcpu);
1361 void svm_switch_vmcb(struct vcpu_svm *svm, struct kvm_vmcb_info *target_vmcb)
1363 svm->current_vmcb = target_vmcb;
1364 svm->vmcb = target_vmcb->ptr;
1367 static int svm_vcpu_create(struct kvm_vcpu *vcpu)
1369 struct vcpu_svm *svm;
1370 struct page *vmcb01_page;
1371 struct page *vmsa_page = NULL;
1374 BUILD_BUG_ON(offsetof(struct vcpu_svm, vcpu) != 0);
1378 vmcb01_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1382 if (sev_es_guest(vcpu->kvm)) {
1384 * SEV-ES guests require a separate VMSA page used to contain
1385 * the encrypted register state of the guest.
1387 vmsa_page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_ZERO);
1389 goto error_free_vmcb_page;
1392 * SEV-ES guests maintain an encrypted version of their FPU
1393 * state which is restored and saved on VMRUN and VMEXIT.
1394 * Mark vcpu->arch.guest_fpu->fpstate as scratch so it won't
1395 * do xsave/xrstor on it.
1397 fpstate_set_confidential(&vcpu->arch.guest_fpu);
1400 err = avic_init_vcpu(svm);
1402 goto error_free_vmsa_page;
1404 svm->msrpm = svm_vcpu_alloc_msrpm();
1407 goto error_free_vmsa_page;
1410 svm->x2avic_msrs_intercepted = true;
1412 svm->vmcb01.ptr = page_address(vmcb01_page);
1413 svm->vmcb01.pa = __sme_set(page_to_pfn(vmcb01_page) << PAGE_SHIFT);
1414 svm_switch_vmcb(svm, &svm->vmcb01);
1417 svm->sev_es.vmsa = page_address(vmsa_page);
1419 svm->guest_state_loaded = false;
1423 error_free_vmsa_page:
1425 __free_page(vmsa_page);
1426 error_free_vmcb_page:
1427 __free_page(vmcb01_page);
1432 static void svm_clear_current_vmcb(struct vmcb *vmcb)
1436 for_each_online_cpu(i)
1437 cmpxchg(&per_cpu(svm_data, i)->current_vmcb, vmcb, NULL);
1440 static void svm_vcpu_free(struct kvm_vcpu *vcpu)
1442 struct vcpu_svm *svm = to_svm(vcpu);
1445 * The vmcb page can be recycled, causing a false negative in
1446 * svm_vcpu_load(). So, ensure that no logical CPU has this
1447 * vmcb page recorded as its current vmcb.
1449 svm_clear_current_vmcb(svm->vmcb);
1451 svm_free_nested(svm);
1453 sev_free_vcpu(vcpu);
1455 __free_page(pfn_to_page(__sme_clr(svm->vmcb01.pa) >> PAGE_SHIFT));
1456 __free_pages(virt_to_page(svm->msrpm), get_order(MSRPM_SIZE));
1459 static void svm_prepare_switch_to_guest(struct kvm_vcpu *vcpu)
1461 struct vcpu_svm *svm = to_svm(vcpu);
1462 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
1464 if (sev_es_guest(vcpu->kvm))
1465 sev_es_unmap_ghcb(svm);
1467 if (svm->guest_state_loaded)
1471 * Save additional host state that will be restored on VMEXIT (sev-es)
1472 * or subsequent vmload of host save area.
1474 vmsave(__sme_page_pa(sd->save_area));
1475 if (sev_es_guest(vcpu->kvm)) {
1476 struct sev_es_save_area *hostsa;
1477 hostsa = (struct sev_es_save_area *)(page_address(sd->save_area) + 0x400);
1479 sev_es_prepare_switch_to_guest(hostsa);
1483 __svm_write_tsc_multiplier(vcpu->arch.tsc_scaling_ratio);
1485 if (likely(tsc_aux_uret_slot >= 0))
1486 kvm_set_user_return_msr(tsc_aux_uret_slot, svm->tsc_aux, -1ull);
1488 svm->guest_state_loaded = true;
1491 static void svm_prepare_host_switch(struct kvm_vcpu *vcpu)
1493 to_svm(vcpu)->guest_state_loaded = false;
1496 static void svm_vcpu_load(struct kvm_vcpu *vcpu, int cpu)
1498 struct vcpu_svm *svm = to_svm(vcpu);
1499 struct svm_cpu_data *sd = per_cpu(svm_data, cpu);
1501 if (sd->current_vmcb != svm->vmcb) {
1502 sd->current_vmcb = svm->vmcb;
1503 indirect_branch_prediction_barrier();
1505 if (kvm_vcpu_apicv_active(vcpu))
1506 avic_vcpu_load(vcpu, cpu);
1509 static void svm_vcpu_put(struct kvm_vcpu *vcpu)
1511 if (kvm_vcpu_apicv_active(vcpu))
1512 avic_vcpu_put(vcpu);
1514 svm_prepare_host_switch(vcpu);
1516 ++vcpu->stat.host_state_reload;
1519 static unsigned long svm_get_rflags(struct kvm_vcpu *vcpu)
1521 struct vcpu_svm *svm = to_svm(vcpu);
1522 unsigned long rflags = svm->vmcb->save.rflags;
1524 if (svm->nmi_singlestep) {
1525 /* Hide our flags if they were not set by the guest */
1526 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_TF))
1527 rflags &= ~X86_EFLAGS_TF;
1528 if (!(svm->nmi_singlestep_guest_rflags & X86_EFLAGS_RF))
1529 rflags &= ~X86_EFLAGS_RF;
1534 static void svm_set_rflags(struct kvm_vcpu *vcpu, unsigned long rflags)
1536 if (to_svm(vcpu)->nmi_singlestep)
1537 rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
1540 * Any change of EFLAGS.VM is accompanied by a reload of SS
1541 * (caused by either a task switch or an inter-privilege IRET),
1542 * so we do not need to update the CPL here.
1544 to_svm(vcpu)->vmcb->save.rflags = rflags;
1547 static bool svm_get_if_flag(struct kvm_vcpu *vcpu)
1549 struct vmcb *vmcb = to_svm(vcpu)->vmcb;
1551 return sev_es_guest(vcpu->kvm)
1552 ? vmcb->control.int_state & SVM_GUEST_INTERRUPT_MASK
1553 : kvm_get_rflags(vcpu) & X86_EFLAGS_IF;
1556 static void svm_cache_reg(struct kvm_vcpu *vcpu, enum kvm_reg reg)
1558 kvm_register_mark_available(vcpu, reg);
1561 case VCPU_EXREG_PDPTR:
1563 * When !npt_enabled, mmu->pdptrs[] is already available since
1564 * it is always updated per SDM when moving to CRs.
1567 load_pdptrs(vcpu, kvm_read_cr3(vcpu));
1570 KVM_BUG_ON(1, vcpu->kvm);
1574 static void svm_set_vintr(struct vcpu_svm *svm)
1576 struct vmcb_control_area *control;
1579 * The following fields are ignored when AVIC is enabled
1581 WARN_ON(kvm_vcpu_apicv_activated(&svm->vcpu));
1583 svm_set_intercept(svm, INTERCEPT_VINTR);
1586 * This is just a dummy VINTR to actually cause a vmexit to happen.
1587 * Actual injection of virtual interrupts happens through EVENTINJ.
1589 control = &svm->vmcb->control;
1590 control->int_vector = 0x0;
1591 control->int_ctl &= ~V_INTR_PRIO_MASK;
1592 control->int_ctl |= V_IRQ_MASK |
1593 ((/*control->int_vector >> 4*/ 0xf) << V_INTR_PRIO_SHIFT);
1594 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1597 static void svm_clear_vintr(struct vcpu_svm *svm)
1599 svm_clr_intercept(svm, INTERCEPT_VINTR);
1601 /* Drop int_ctl fields related to VINTR injection. */
1602 svm->vmcb->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1603 if (is_guest_mode(&svm->vcpu)) {
1604 svm->vmcb01.ptr->control.int_ctl &= ~V_IRQ_INJECTION_BITS_MASK;
1606 WARN_ON((svm->vmcb->control.int_ctl & V_TPR_MASK) !=
1607 (svm->nested.ctl.int_ctl & V_TPR_MASK));
1609 svm->vmcb->control.int_ctl |= svm->nested.ctl.int_ctl &
1610 V_IRQ_INJECTION_BITS_MASK;
1612 svm->vmcb->control.int_vector = svm->nested.ctl.int_vector;
1615 vmcb_mark_dirty(svm->vmcb, VMCB_INTR);
1618 static struct vmcb_seg *svm_seg(struct kvm_vcpu *vcpu, int seg)
1620 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1621 struct vmcb_save_area *save01 = &to_svm(vcpu)->vmcb01.ptr->save;
1624 case VCPU_SREG_CS: return &save->cs;
1625 case VCPU_SREG_DS: return &save->ds;
1626 case VCPU_SREG_ES: return &save->es;
1627 case VCPU_SREG_FS: return &save01->fs;
1628 case VCPU_SREG_GS: return &save01->gs;
1629 case VCPU_SREG_SS: return &save->ss;
1630 case VCPU_SREG_TR: return &save01->tr;
1631 case VCPU_SREG_LDTR: return &save01->ldtr;
1637 static u64 svm_get_segment_base(struct kvm_vcpu *vcpu, int seg)
1639 struct vmcb_seg *s = svm_seg(vcpu, seg);
1644 static void svm_get_segment(struct kvm_vcpu *vcpu,
1645 struct kvm_segment *var, int seg)
1647 struct vmcb_seg *s = svm_seg(vcpu, seg);
1649 var->base = s->base;
1650 var->limit = s->limit;
1651 var->selector = s->selector;
1652 var->type = s->attrib & SVM_SELECTOR_TYPE_MASK;
1653 var->s = (s->attrib >> SVM_SELECTOR_S_SHIFT) & 1;
1654 var->dpl = (s->attrib >> SVM_SELECTOR_DPL_SHIFT) & 3;
1655 var->present = (s->attrib >> SVM_SELECTOR_P_SHIFT) & 1;
1656 var->avl = (s->attrib >> SVM_SELECTOR_AVL_SHIFT) & 1;
1657 var->l = (s->attrib >> SVM_SELECTOR_L_SHIFT) & 1;
1658 var->db = (s->attrib >> SVM_SELECTOR_DB_SHIFT) & 1;
1661 * AMD CPUs circa 2014 track the G bit for all segments except CS.
1662 * However, the SVM spec states that the G bit is not observed by the
1663 * CPU, and some VMware virtual CPUs drop the G bit for all segments.
1664 * So let's synthesize a legal G bit for all segments, this helps
1665 * running KVM nested. It also helps cross-vendor migration, because
1666 * Intel's vmentry has a check on the 'G' bit.
1668 var->g = s->limit > 0xfffff;
1671 * AMD's VMCB does not have an explicit unusable field, so emulate it
1672 * for cross vendor migration purposes by "not present"
1674 var->unusable = !var->present;
1679 * Work around a bug where the busy flag in the tr selector
1689 * The accessed bit must always be set in the segment
1690 * descriptor cache, although it can be cleared in the
1691 * descriptor, the cached bit always remains at 1. Since
1692 * Intel has a check on this, set it here to support
1693 * cross-vendor migration.
1700 * On AMD CPUs sometimes the DB bit in the segment
1701 * descriptor is left as 1, although the whole segment has
1702 * been made unusable. Clear it here to pass an Intel VMX
1703 * entry check when cross vendor migrating.
1707 /* This is symmetric with svm_set_segment() */
1708 var->dpl = to_svm(vcpu)->vmcb->save.cpl;
1713 static int svm_get_cpl(struct kvm_vcpu *vcpu)
1715 struct vmcb_save_area *save = &to_svm(vcpu)->vmcb->save;
1720 static void svm_get_cs_db_l_bits(struct kvm_vcpu *vcpu, int *db, int *l)
1722 struct kvm_segment cs;
1724 svm_get_segment(vcpu, &cs, VCPU_SREG_CS);
1729 static void svm_get_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1731 struct vcpu_svm *svm = to_svm(vcpu);
1733 dt->size = svm->vmcb->save.idtr.limit;
1734 dt->address = svm->vmcb->save.idtr.base;
1737 static void svm_set_idt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1739 struct vcpu_svm *svm = to_svm(vcpu);
1741 svm->vmcb->save.idtr.limit = dt->size;
1742 svm->vmcb->save.idtr.base = dt->address ;
1743 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1746 static void svm_get_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1748 struct vcpu_svm *svm = to_svm(vcpu);
1750 dt->size = svm->vmcb->save.gdtr.limit;
1751 dt->address = svm->vmcb->save.gdtr.base;
1754 static void svm_set_gdt(struct kvm_vcpu *vcpu, struct desc_ptr *dt)
1756 struct vcpu_svm *svm = to_svm(vcpu);
1758 svm->vmcb->save.gdtr.limit = dt->size;
1759 svm->vmcb->save.gdtr.base = dt->address ;
1760 vmcb_mark_dirty(svm->vmcb, VMCB_DT);
1763 static void sev_post_set_cr3(struct kvm_vcpu *vcpu, unsigned long cr3)
1765 struct vcpu_svm *svm = to_svm(vcpu);
1768 * For guests that don't set guest_state_protected, the cr3 update is
1769 * handled via kvm_mmu_load() while entering the guest. For guests
1770 * that do (SEV-ES/SEV-SNP), the cr3 update needs to be written to
1771 * VMCB save area now, since the save area will become the initial
1772 * contents of the VMSA, and future VMCB save area updates won't be
1775 if (sev_es_guest(vcpu->kvm)) {
1776 svm->vmcb->save.cr3 = cr3;
1777 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1781 void svm_set_cr0(struct kvm_vcpu *vcpu, unsigned long cr0)
1783 struct vcpu_svm *svm = to_svm(vcpu);
1785 bool old_paging = is_paging(vcpu);
1787 #ifdef CONFIG_X86_64
1788 if (vcpu->arch.efer & EFER_LME && !vcpu->arch.guest_state_protected) {
1789 if (!is_paging(vcpu) && (cr0 & X86_CR0_PG)) {
1790 vcpu->arch.efer |= EFER_LMA;
1791 svm->vmcb->save.efer |= EFER_LMA | EFER_LME;
1794 if (is_paging(vcpu) && !(cr0 & X86_CR0_PG)) {
1795 vcpu->arch.efer &= ~EFER_LMA;
1796 svm->vmcb->save.efer &= ~(EFER_LMA | EFER_LME);
1800 vcpu->arch.cr0 = cr0;
1803 hcr0 |= X86_CR0_PG | X86_CR0_WP;
1804 if (old_paging != is_paging(vcpu))
1805 svm_set_cr4(vcpu, kvm_read_cr4(vcpu));
1809 * re-enable caching here because the QEMU bios
1810 * does not do it - this results in some delay at
1813 if (kvm_check_has_quirk(vcpu->kvm, KVM_X86_QUIRK_CD_NW_CLEARED))
1814 hcr0 &= ~(X86_CR0_CD | X86_CR0_NW);
1816 svm->vmcb->save.cr0 = hcr0;
1817 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
1820 * SEV-ES guests must always keep the CR intercepts cleared. CR
1821 * tracking is done using the CR write traps.
1823 if (sev_es_guest(vcpu->kvm))
1827 /* Selective CR0 write remains on. */
1828 svm_clr_intercept(svm, INTERCEPT_CR0_READ);
1829 svm_clr_intercept(svm, INTERCEPT_CR0_WRITE);
1831 svm_set_intercept(svm, INTERCEPT_CR0_READ);
1832 svm_set_intercept(svm, INTERCEPT_CR0_WRITE);
1836 static bool svm_is_valid_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1841 void svm_set_cr4(struct kvm_vcpu *vcpu, unsigned long cr4)
1843 unsigned long host_cr4_mce = cr4_read_shadow() & X86_CR4_MCE;
1844 unsigned long old_cr4 = vcpu->arch.cr4;
1846 if (npt_enabled && ((old_cr4 ^ cr4) & X86_CR4_PGE))
1847 svm_flush_tlb_current(vcpu);
1849 vcpu->arch.cr4 = cr4;
1853 if (!is_paging(vcpu))
1854 cr4 &= ~(X86_CR4_SMEP | X86_CR4_SMAP | X86_CR4_PKE);
1856 cr4 |= host_cr4_mce;
1857 to_svm(vcpu)->vmcb->save.cr4 = cr4;
1858 vmcb_mark_dirty(to_svm(vcpu)->vmcb, VMCB_CR);
1860 if ((cr4 ^ old_cr4) & (X86_CR4_OSXSAVE | X86_CR4_PKE))
1861 kvm_update_cpuid_runtime(vcpu);
1864 static void svm_set_segment(struct kvm_vcpu *vcpu,
1865 struct kvm_segment *var, int seg)
1867 struct vcpu_svm *svm = to_svm(vcpu);
1868 struct vmcb_seg *s = svm_seg(vcpu, seg);
1870 s->base = var->base;
1871 s->limit = var->limit;
1872 s->selector = var->selector;
1873 s->attrib = (var->type & SVM_SELECTOR_TYPE_MASK);
1874 s->attrib |= (var->s & 1) << SVM_SELECTOR_S_SHIFT;
1875 s->attrib |= (var->dpl & 3) << SVM_SELECTOR_DPL_SHIFT;
1876 s->attrib |= ((var->present & 1) && !var->unusable) << SVM_SELECTOR_P_SHIFT;
1877 s->attrib |= (var->avl & 1) << SVM_SELECTOR_AVL_SHIFT;
1878 s->attrib |= (var->l & 1) << SVM_SELECTOR_L_SHIFT;
1879 s->attrib |= (var->db & 1) << SVM_SELECTOR_DB_SHIFT;
1880 s->attrib |= (var->g & 1) << SVM_SELECTOR_G_SHIFT;
1883 * This is always accurate, except if SYSRET returned to a segment
1884 * with SS.DPL != 3. Intel does not have this quirk, and always
1885 * forces SS.DPL to 3 on sysret, so we ignore that case; fixing it
1886 * would entail passing the CPL to userspace and back.
1888 if (seg == VCPU_SREG_SS)
1889 /* This is symmetric with svm_get_segment() */
1890 svm->vmcb->save.cpl = (var->dpl & 3);
1892 vmcb_mark_dirty(svm->vmcb, VMCB_SEG);
1895 static void svm_update_exception_bitmap(struct kvm_vcpu *vcpu)
1897 struct vcpu_svm *svm = to_svm(vcpu);
1899 clr_exception_intercept(svm, BP_VECTOR);
1901 if (vcpu->guest_debug & KVM_GUESTDBG_ENABLE) {
1902 if (vcpu->guest_debug & KVM_GUESTDBG_USE_SW_BP)
1903 set_exception_intercept(svm, BP_VECTOR);
1907 static void new_asid(struct vcpu_svm *svm, struct svm_cpu_data *sd)
1909 if (sd->next_asid > sd->max_asid) {
1910 ++sd->asid_generation;
1911 sd->next_asid = sd->min_asid;
1912 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ALL_ASID;
1913 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
1916 svm->current_vmcb->asid_generation = sd->asid_generation;
1917 svm->asid = sd->next_asid++;
1920 static void svm_set_dr6(struct vcpu_svm *svm, unsigned long value)
1922 struct vmcb *vmcb = svm->vmcb;
1924 if (svm->vcpu.arch.guest_state_protected)
1927 if (unlikely(value != vmcb->save.dr6)) {
1928 vmcb->save.dr6 = value;
1929 vmcb_mark_dirty(vmcb, VMCB_DR);
1933 static void svm_sync_dirty_debug_regs(struct kvm_vcpu *vcpu)
1935 struct vcpu_svm *svm = to_svm(vcpu);
1937 if (vcpu->arch.guest_state_protected)
1940 get_debugreg(vcpu->arch.db[0], 0);
1941 get_debugreg(vcpu->arch.db[1], 1);
1942 get_debugreg(vcpu->arch.db[2], 2);
1943 get_debugreg(vcpu->arch.db[3], 3);
1945 * We cannot reset svm->vmcb->save.dr6 to DR6_ACTIVE_LOW here,
1946 * because db_interception might need it. We can do it before vmentry.
1948 vcpu->arch.dr6 = svm->vmcb->save.dr6;
1949 vcpu->arch.dr7 = svm->vmcb->save.dr7;
1950 vcpu->arch.switch_db_regs &= ~KVM_DEBUGREG_WONT_EXIT;
1951 set_dr_intercepts(svm);
1954 static void svm_set_dr7(struct kvm_vcpu *vcpu, unsigned long value)
1956 struct vcpu_svm *svm = to_svm(vcpu);
1958 if (vcpu->arch.guest_state_protected)
1961 svm->vmcb->save.dr7 = value;
1962 vmcb_mark_dirty(svm->vmcb, VMCB_DR);
1965 static int pf_interception(struct kvm_vcpu *vcpu)
1967 struct vcpu_svm *svm = to_svm(vcpu);
1969 u64 fault_address = svm->vmcb->control.exit_info_2;
1970 u64 error_code = svm->vmcb->control.exit_info_1;
1972 return kvm_handle_page_fault(vcpu, error_code, fault_address,
1973 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1974 svm->vmcb->control.insn_bytes : NULL,
1975 svm->vmcb->control.insn_len);
1978 static int npf_interception(struct kvm_vcpu *vcpu)
1980 struct vcpu_svm *svm = to_svm(vcpu);
1982 u64 fault_address = svm->vmcb->control.exit_info_2;
1983 u64 error_code = svm->vmcb->control.exit_info_1;
1985 trace_kvm_page_fault(fault_address, error_code);
1986 return kvm_mmu_page_fault(vcpu, fault_address, error_code,
1987 static_cpu_has(X86_FEATURE_DECODEASSISTS) ?
1988 svm->vmcb->control.insn_bytes : NULL,
1989 svm->vmcb->control.insn_len);
1992 static int db_interception(struct kvm_vcpu *vcpu)
1994 struct kvm_run *kvm_run = vcpu->run;
1995 struct vcpu_svm *svm = to_svm(vcpu);
1997 if (!(vcpu->guest_debug &
1998 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) &&
1999 !svm->nmi_singlestep) {
2000 u32 payload = svm->vmcb->save.dr6 ^ DR6_ACTIVE_LOW;
2001 kvm_queue_exception_p(vcpu, DB_VECTOR, payload);
2005 if (svm->nmi_singlestep) {
2006 disable_nmi_singlestep(svm);
2007 /* Make sure we check for pending NMIs upon entry */
2008 kvm_make_request(KVM_REQ_EVENT, vcpu);
2011 if (vcpu->guest_debug &
2012 (KVM_GUESTDBG_SINGLESTEP | KVM_GUESTDBG_USE_HW_BP)) {
2013 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2014 kvm_run->debug.arch.dr6 = svm->vmcb->save.dr6;
2015 kvm_run->debug.arch.dr7 = svm->vmcb->save.dr7;
2016 kvm_run->debug.arch.pc =
2017 svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2018 kvm_run->debug.arch.exception = DB_VECTOR;
2025 static int bp_interception(struct kvm_vcpu *vcpu)
2027 struct vcpu_svm *svm = to_svm(vcpu);
2028 struct kvm_run *kvm_run = vcpu->run;
2030 kvm_run->exit_reason = KVM_EXIT_DEBUG;
2031 kvm_run->debug.arch.pc = svm->vmcb->save.cs.base + svm->vmcb->save.rip;
2032 kvm_run->debug.arch.exception = BP_VECTOR;
2036 static int ud_interception(struct kvm_vcpu *vcpu)
2038 return handle_ud(vcpu);
2041 static int ac_interception(struct kvm_vcpu *vcpu)
2043 kvm_queue_exception_e(vcpu, AC_VECTOR, 0);
2047 static bool is_erratum_383(void)
2052 if (!erratum_383_found)
2055 value = native_read_msr_safe(MSR_IA32_MC0_STATUS, &err);
2059 /* Bit 62 may or may not be set for this mce */
2060 value &= ~(1ULL << 62);
2062 if (value != 0xb600000000010015ULL)
2065 /* Clear MCi_STATUS registers */
2066 for (i = 0; i < 6; ++i)
2067 native_write_msr_safe(MSR_IA32_MCx_STATUS(i), 0, 0);
2069 value = native_read_msr_safe(MSR_IA32_MCG_STATUS, &err);
2073 value &= ~(1ULL << 2);
2074 low = lower_32_bits(value);
2075 high = upper_32_bits(value);
2077 native_write_msr_safe(MSR_IA32_MCG_STATUS, low, high);
2080 /* Flush tlb to evict multi-match entries */
2086 static void svm_handle_mce(struct kvm_vcpu *vcpu)
2088 if (is_erratum_383()) {
2090 * Erratum 383 triggered. Guest state is corrupt so kill the
2093 pr_err("KVM: Guest triggered AMD Erratum 383\n");
2095 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
2101 * On an #MC intercept the MCE handler is not called automatically in
2102 * the host. So do it by hand here.
2104 kvm_machine_check();
2107 static int mc_interception(struct kvm_vcpu *vcpu)
2112 static int shutdown_interception(struct kvm_vcpu *vcpu)
2114 struct kvm_run *kvm_run = vcpu->run;
2115 struct vcpu_svm *svm = to_svm(vcpu);
2118 * The VM save area has already been encrypted so it
2119 * cannot be reinitialized - just terminate.
2121 if (sev_es_guest(vcpu->kvm))
2125 * VMCB is undefined after a SHUTDOWN intercept. INIT the vCPU to put
2126 * the VMCB in a known good state. Unfortuately, KVM doesn't have
2127 * KVM_MP_STATE_SHUTDOWN and can't add it without potentially breaking
2128 * userspace. At a platform view, INIT is acceptable behavior as
2129 * there exist bare metal platforms that automatically INIT the CPU
2130 * in response to shutdown.
2132 clear_page(svm->vmcb);
2133 kvm_vcpu_reset(vcpu, true);
2135 kvm_run->exit_reason = KVM_EXIT_SHUTDOWN;
2139 static int io_interception(struct kvm_vcpu *vcpu)
2141 struct vcpu_svm *svm = to_svm(vcpu);
2142 u32 io_info = svm->vmcb->control.exit_info_1; /* address size bug? */
2143 int size, in, string;
2146 ++vcpu->stat.io_exits;
2147 string = (io_info & SVM_IOIO_STR_MASK) != 0;
2148 in = (io_info & SVM_IOIO_TYPE_MASK) != 0;
2149 port = io_info >> 16;
2150 size = (io_info & SVM_IOIO_SIZE_MASK) >> SVM_IOIO_SIZE_SHIFT;
2153 if (sev_es_guest(vcpu->kvm))
2154 return sev_es_string_io(svm, size, port, in);
2156 return kvm_emulate_instruction(vcpu, 0);
2159 svm->next_rip = svm->vmcb->control.exit_info_2;
2161 return kvm_fast_pio(vcpu, size, port, in);
2164 static int nmi_interception(struct kvm_vcpu *vcpu)
2169 static int smi_interception(struct kvm_vcpu *vcpu)
2174 static int intr_interception(struct kvm_vcpu *vcpu)
2176 ++vcpu->stat.irq_exits;
2180 static int vmload_vmsave_interception(struct kvm_vcpu *vcpu, bool vmload)
2182 struct vcpu_svm *svm = to_svm(vcpu);
2183 struct vmcb *vmcb12;
2184 struct kvm_host_map map;
2187 if (nested_svm_check_permissions(vcpu))
2190 ret = kvm_vcpu_map(vcpu, gpa_to_gfn(svm->vmcb->save.rax), &map);
2193 kvm_inject_gp(vcpu, 0);
2199 ret = kvm_skip_emulated_instruction(vcpu);
2202 svm_copy_vmloadsave_state(svm->vmcb, vmcb12);
2203 svm->sysenter_eip_hi = 0;
2204 svm->sysenter_esp_hi = 0;
2206 svm_copy_vmloadsave_state(vmcb12, svm->vmcb);
2209 kvm_vcpu_unmap(vcpu, &map, true);
2214 static int vmload_interception(struct kvm_vcpu *vcpu)
2216 return vmload_vmsave_interception(vcpu, true);
2219 static int vmsave_interception(struct kvm_vcpu *vcpu)
2221 return vmload_vmsave_interception(vcpu, false);
2224 static int vmrun_interception(struct kvm_vcpu *vcpu)
2226 if (nested_svm_check_permissions(vcpu))
2229 return nested_svm_vmrun(vcpu);
2239 /* Return NONE_SVM_INSTR if not SVM instrs, otherwise return decode result */
2240 static int svm_instr_opcode(struct kvm_vcpu *vcpu)
2242 struct x86_emulate_ctxt *ctxt = vcpu->arch.emulate_ctxt;
2244 if (ctxt->b != 0x1 || ctxt->opcode_len != 2)
2245 return NONE_SVM_INSTR;
2247 switch (ctxt->modrm) {
2248 case 0xd8: /* VMRUN */
2249 return SVM_INSTR_VMRUN;
2250 case 0xda: /* VMLOAD */
2251 return SVM_INSTR_VMLOAD;
2252 case 0xdb: /* VMSAVE */
2253 return SVM_INSTR_VMSAVE;
2258 return NONE_SVM_INSTR;
2261 static int emulate_svm_instr(struct kvm_vcpu *vcpu, int opcode)
2263 const int guest_mode_exit_codes[] = {
2264 [SVM_INSTR_VMRUN] = SVM_EXIT_VMRUN,
2265 [SVM_INSTR_VMLOAD] = SVM_EXIT_VMLOAD,
2266 [SVM_INSTR_VMSAVE] = SVM_EXIT_VMSAVE,
2268 int (*const svm_instr_handlers[])(struct kvm_vcpu *vcpu) = {
2269 [SVM_INSTR_VMRUN] = vmrun_interception,
2270 [SVM_INSTR_VMLOAD] = vmload_interception,
2271 [SVM_INSTR_VMSAVE] = vmsave_interception,
2273 struct vcpu_svm *svm = to_svm(vcpu);
2276 if (is_guest_mode(vcpu)) {
2277 /* Returns '1' or -errno on failure, '0' on success. */
2278 ret = nested_svm_simple_vmexit(svm, guest_mode_exit_codes[opcode]);
2283 return svm_instr_handlers[opcode](vcpu);
2287 * #GP handling code. Note that #GP can be triggered under the following two
2289 * 1) SVM VM-related instructions (VMRUN/VMSAVE/VMLOAD) that trigger #GP on
2290 * some AMD CPUs when EAX of these instructions are in the reserved memory
2291 * regions (e.g. SMM memory on host).
2292 * 2) VMware backdoor
2294 static int gp_interception(struct kvm_vcpu *vcpu)
2296 struct vcpu_svm *svm = to_svm(vcpu);
2297 u32 error_code = svm->vmcb->control.exit_info_1;
2300 /* Both #GP cases have zero error_code */
2304 /* Decode the instruction for usage later */
2305 if (x86_decode_emulated_instruction(vcpu, 0, NULL, 0) != EMULATION_OK)
2308 opcode = svm_instr_opcode(vcpu);
2310 if (opcode == NONE_SVM_INSTR) {
2311 if (!enable_vmware_backdoor)
2315 * VMware backdoor emulation on #GP interception only handles
2316 * IN{S}, OUT{S}, and RDPMC.
2318 if (!is_guest_mode(vcpu))
2319 return kvm_emulate_instruction(vcpu,
2320 EMULTYPE_VMWARE_GP | EMULTYPE_NO_DECODE);
2322 /* All SVM instructions expect page aligned RAX */
2323 if (svm->vmcb->save.rax & ~PAGE_MASK)
2326 return emulate_svm_instr(vcpu, opcode);
2330 kvm_queue_exception_e(vcpu, GP_VECTOR, error_code);
2334 void svm_set_gif(struct vcpu_svm *svm, bool value)
2338 * If VGIF is enabled, the STGI intercept is only added to
2339 * detect the opening of the SMI/NMI window; remove it now.
2340 * Likewise, clear the VINTR intercept, we will set it
2341 * again while processing KVM_REQ_EVENT if needed.
2344 svm_clr_intercept(svm, INTERCEPT_STGI);
2345 if (svm_is_intercept(svm, INTERCEPT_VINTR))
2346 svm_clear_vintr(svm);
2349 if (svm->vcpu.arch.smi_pending ||
2350 svm->vcpu.arch.nmi_pending ||
2351 kvm_cpu_has_injectable_intr(&svm->vcpu))
2352 kvm_make_request(KVM_REQ_EVENT, &svm->vcpu);
2357 * After a CLGI no interrupts should come. But if vGIF is
2358 * in use, we still rely on the VINTR intercept (rather than
2359 * STGI) to detect an open interrupt window.
2362 svm_clear_vintr(svm);
2366 static int stgi_interception(struct kvm_vcpu *vcpu)
2370 if (nested_svm_check_permissions(vcpu))
2373 ret = kvm_skip_emulated_instruction(vcpu);
2374 svm_set_gif(to_svm(vcpu), true);
2378 static int clgi_interception(struct kvm_vcpu *vcpu)
2382 if (nested_svm_check_permissions(vcpu))
2385 ret = kvm_skip_emulated_instruction(vcpu);
2386 svm_set_gif(to_svm(vcpu), false);
2390 static int invlpga_interception(struct kvm_vcpu *vcpu)
2392 gva_t gva = kvm_rax_read(vcpu);
2393 u32 asid = kvm_rcx_read(vcpu);
2395 /* FIXME: Handle an address size prefix. */
2396 if (!is_long_mode(vcpu))
2399 trace_kvm_invlpga(to_svm(vcpu)->vmcb->save.rip, asid, gva);
2401 /* Let's treat INVLPGA the same as INVLPG (can be optimized!) */
2402 kvm_mmu_invlpg(vcpu, gva);
2404 return kvm_skip_emulated_instruction(vcpu);
2407 static int skinit_interception(struct kvm_vcpu *vcpu)
2409 trace_kvm_skinit(to_svm(vcpu)->vmcb->save.rip, kvm_rax_read(vcpu));
2411 kvm_queue_exception(vcpu, UD_VECTOR);
2415 static int task_switch_interception(struct kvm_vcpu *vcpu)
2417 struct vcpu_svm *svm = to_svm(vcpu);
2420 int int_type = svm->vmcb->control.exit_int_info &
2421 SVM_EXITINTINFO_TYPE_MASK;
2422 int int_vec = svm->vmcb->control.exit_int_info & SVM_EVTINJ_VEC_MASK;
2424 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_TYPE_MASK;
2426 svm->vmcb->control.exit_int_info & SVM_EXITINTINFO_VALID;
2427 bool has_error_code = false;
2430 tss_selector = (u16)svm->vmcb->control.exit_info_1;
2432 if (svm->vmcb->control.exit_info_2 &
2433 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_IRET))
2434 reason = TASK_SWITCH_IRET;
2435 else if (svm->vmcb->control.exit_info_2 &
2436 (1ULL << SVM_EXITINFOSHIFT_TS_REASON_JMP))
2437 reason = TASK_SWITCH_JMP;
2439 reason = TASK_SWITCH_GATE;
2441 reason = TASK_SWITCH_CALL;
2443 if (reason == TASK_SWITCH_GATE) {
2445 case SVM_EXITINTINFO_TYPE_NMI:
2446 vcpu->arch.nmi_injected = false;
2448 case SVM_EXITINTINFO_TYPE_EXEPT:
2449 if (svm->vmcb->control.exit_info_2 &
2450 (1ULL << SVM_EXITINFOSHIFT_TS_HAS_ERROR_CODE)) {
2451 has_error_code = true;
2453 (u32)svm->vmcb->control.exit_info_2;
2455 kvm_clear_exception_queue(vcpu);
2457 case SVM_EXITINTINFO_TYPE_INTR:
2458 case SVM_EXITINTINFO_TYPE_SOFT:
2459 kvm_clear_interrupt_queue(vcpu);
2466 if (reason != TASK_SWITCH_GATE ||
2467 int_type == SVM_EXITINTINFO_TYPE_SOFT ||
2468 (int_type == SVM_EXITINTINFO_TYPE_EXEPT &&
2469 (int_vec == OF_VECTOR || int_vec == BP_VECTOR))) {
2470 if (!svm_skip_emulated_instruction(vcpu))
2474 if (int_type != SVM_EXITINTINFO_TYPE_SOFT)
2477 return kvm_task_switch(vcpu, tss_selector, int_vec, reason,
2478 has_error_code, error_code);
2481 static int iret_interception(struct kvm_vcpu *vcpu)
2483 struct vcpu_svm *svm = to_svm(vcpu);
2485 ++vcpu->stat.nmi_window_exits;
2486 vcpu->arch.hflags |= HF_IRET_MASK;
2487 if (!sev_es_guest(vcpu->kvm)) {
2488 svm_clr_intercept(svm, INTERCEPT_IRET);
2489 svm->nmi_iret_rip = kvm_rip_read(vcpu);
2491 kvm_make_request(KVM_REQ_EVENT, vcpu);
2495 static int invlpg_interception(struct kvm_vcpu *vcpu)
2497 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2498 return kvm_emulate_instruction(vcpu, 0);
2500 kvm_mmu_invlpg(vcpu, to_svm(vcpu)->vmcb->control.exit_info_1);
2501 return kvm_skip_emulated_instruction(vcpu);
2504 static int emulate_on_interception(struct kvm_vcpu *vcpu)
2506 return kvm_emulate_instruction(vcpu, 0);
2509 static int rsm_interception(struct kvm_vcpu *vcpu)
2511 return kvm_emulate_instruction_from_buffer(vcpu, rsm_ins_bytes, 2);
2514 static bool check_selective_cr0_intercepted(struct kvm_vcpu *vcpu,
2517 struct vcpu_svm *svm = to_svm(vcpu);
2518 unsigned long cr0 = vcpu->arch.cr0;
2521 if (!is_guest_mode(vcpu) ||
2522 (!(vmcb12_is_intercept(&svm->nested.ctl, INTERCEPT_SELECTIVE_CR0))))
2525 cr0 &= ~SVM_CR0_SELECTIVE_MASK;
2526 val &= ~SVM_CR0_SELECTIVE_MASK;
2529 svm->vmcb->control.exit_code = SVM_EXIT_CR0_SEL_WRITE;
2530 ret = (nested_svm_exit_handled(svm) == NESTED_EXIT_DONE);
2536 #define CR_VALID (1ULL << 63)
2538 static int cr_interception(struct kvm_vcpu *vcpu)
2540 struct vcpu_svm *svm = to_svm(vcpu);
2545 if (!static_cpu_has(X86_FEATURE_DECODEASSISTS))
2546 return emulate_on_interception(vcpu);
2548 if (unlikely((svm->vmcb->control.exit_info_1 & CR_VALID) == 0))
2549 return emulate_on_interception(vcpu);
2551 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2552 if (svm->vmcb->control.exit_code == SVM_EXIT_CR0_SEL_WRITE)
2553 cr = SVM_EXIT_WRITE_CR0 - SVM_EXIT_READ_CR0;
2555 cr = svm->vmcb->control.exit_code - SVM_EXIT_READ_CR0;
2558 if (cr >= 16) { /* mov to cr */
2560 val = kvm_register_read(vcpu, reg);
2561 trace_kvm_cr_write(cr, val);
2564 if (!check_selective_cr0_intercepted(vcpu, val))
2565 err = kvm_set_cr0(vcpu, val);
2571 err = kvm_set_cr3(vcpu, val);
2574 err = kvm_set_cr4(vcpu, val);
2577 err = kvm_set_cr8(vcpu, val);
2580 WARN(1, "unhandled write to CR%d", cr);
2581 kvm_queue_exception(vcpu, UD_VECTOR);
2584 } else { /* mov from cr */
2587 val = kvm_read_cr0(vcpu);
2590 val = vcpu->arch.cr2;
2593 val = kvm_read_cr3(vcpu);
2596 val = kvm_read_cr4(vcpu);
2599 val = kvm_get_cr8(vcpu);
2602 WARN(1, "unhandled read from CR%d", cr);
2603 kvm_queue_exception(vcpu, UD_VECTOR);
2606 kvm_register_write(vcpu, reg, val);
2607 trace_kvm_cr_read(cr, val);
2609 return kvm_complete_insn_gp(vcpu, err);
2612 static int cr_trap(struct kvm_vcpu *vcpu)
2614 struct vcpu_svm *svm = to_svm(vcpu);
2615 unsigned long old_value, new_value;
2619 new_value = (unsigned long)svm->vmcb->control.exit_info_1;
2621 cr = svm->vmcb->control.exit_code - SVM_EXIT_CR0_WRITE_TRAP;
2624 old_value = kvm_read_cr0(vcpu);
2625 svm_set_cr0(vcpu, new_value);
2627 kvm_post_set_cr0(vcpu, old_value, new_value);
2630 old_value = kvm_read_cr4(vcpu);
2631 svm_set_cr4(vcpu, new_value);
2633 kvm_post_set_cr4(vcpu, old_value, new_value);
2636 ret = kvm_set_cr8(vcpu, new_value);
2639 WARN(1, "unhandled CR%d write trap", cr);
2640 kvm_queue_exception(vcpu, UD_VECTOR);
2644 return kvm_complete_insn_gp(vcpu, ret);
2647 static int dr_interception(struct kvm_vcpu *vcpu)
2649 struct vcpu_svm *svm = to_svm(vcpu);
2654 if (vcpu->guest_debug == 0) {
2656 * No more DR vmexits; force a reload of the debug registers
2657 * and reenter on this instruction. The next vmexit will
2658 * retrieve the full state of the debug registers.
2660 clr_dr_intercepts(svm);
2661 vcpu->arch.switch_db_regs |= KVM_DEBUGREG_WONT_EXIT;
2665 if (!boot_cpu_has(X86_FEATURE_DECODEASSISTS))
2666 return emulate_on_interception(vcpu);
2668 reg = svm->vmcb->control.exit_info_1 & SVM_EXITINFO_REG_MASK;
2669 dr = svm->vmcb->control.exit_code - SVM_EXIT_READ_DR0;
2670 if (dr >= 16) { /* mov to DRn */
2672 val = kvm_register_read(vcpu, reg);
2673 err = kvm_set_dr(vcpu, dr, val);
2675 kvm_get_dr(vcpu, dr, &val);
2676 kvm_register_write(vcpu, reg, val);
2679 return kvm_complete_insn_gp(vcpu, err);
2682 static int cr8_write_interception(struct kvm_vcpu *vcpu)
2686 u8 cr8_prev = kvm_get_cr8(vcpu);
2687 /* instruction emulation calls kvm_set_cr8() */
2688 r = cr_interception(vcpu);
2689 if (lapic_in_kernel(vcpu))
2691 if (cr8_prev <= kvm_get_cr8(vcpu))
2693 vcpu->run->exit_reason = KVM_EXIT_SET_TPR;
2697 static int efer_trap(struct kvm_vcpu *vcpu)
2699 struct msr_data msr_info;
2703 * Clear the EFER_SVME bit from EFER. The SVM code always sets this
2704 * bit in svm_set_efer(), but __kvm_valid_efer() checks it against
2705 * whether the guest has X86_FEATURE_SVM - this avoids a failure if
2706 * the guest doesn't have X86_FEATURE_SVM.
2708 msr_info.host_initiated = false;
2709 msr_info.index = MSR_EFER;
2710 msr_info.data = to_svm(vcpu)->vmcb->control.exit_info_1 & ~EFER_SVME;
2711 ret = kvm_set_msr_common(vcpu, &msr_info);
2713 return kvm_complete_insn_gp(vcpu, ret);
2716 static int svm_get_msr_feature(struct kvm_msr_entry *msr)
2720 switch (msr->index) {
2721 case MSR_F10H_DECFG:
2722 if (boot_cpu_has(X86_FEATURE_LFENCE_RDTSC))
2723 msr->data |= MSR_F10H_DECFG_LFENCE_SERIALIZE;
2725 case MSR_IA32_PERF_CAPABILITIES:
2728 return KVM_MSR_RET_INVALID;
2734 static int svm_get_msr(struct kvm_vcpu *vcpu, struct msr_data *msr_info)
2736 struct vcpu_svm *svm = to_svm(vcpu);
2738 switch (msr_info->index) {
2739 case MSR_AMD64_TSC_RATIO:
2740 if (!msr_info->host_initiated && !svm->tsc_scaling_enabled)
2742 msr_info->data = svm->tsc_ratio_msr;
2745 msr_info->data = svm->vmcb01.ptr->save.star;
2747 #ifdef CONFIG_X86_64
2749 msr_info->data = svm->vmcb01.ptr->save.lstar;
2752 msr_info->data = svm->vmcb01.ptr->save.cstar;
2754 case MSR_KERNEL_GS_BASE:
2755 msr_info->data = svm->vmcb01.ptr->save.kernel_gs_base;
2757 case MSR_SYSCALL_MASK:
2758 msr_info->data = svm->vmcb01.ptr->save.sfmask;
2761 case MSR_IA32_SYSENTER_CS:
2762 msr_info->data = svm->vmcb01.ptr->save.sysenter_cs;
2764 case MSR_IA32_SYSENTER_EIP:
2765 msr_info->data = (u32)svm->vmcb01.ptr->save.sysenter_eip;
2766 if (guest_cpuid_is_intel(vcpu))
2767 msr_info->data |= (u64)svm->sysenter_eip_hi << 32;
2769 case MSR_IA32_SYSENTER_ESP:
2770 msr_info->data = svm->vmcb01.ptr->save.sysenter_esp;
2771 if (guest_cpuid_is_intel(vcpu))
2772 msr_info->data |= (u64)svm->sysenter_esp_hi << 32;
2775 msr_info->data = svm->tsc_aux;
2777 case MSR_IA32_DEBUGCTLMSR:
2778 case MSR_IA32_LASTBRANCHFROMIP:
2779 case MSR_IA32_LASTBRANCHTOIP:
2780 case MSR_IA32_LASTINTFROMIP:
2781 case MSR_IA32_LASTINTTOIP:
2782 msr_info->data = svm_get_lbr_msr(svm, msr_info->index);
2784 case MSR_VM_HSAVE_PA:
2785 msr_info->data = svm->nested.hsave_msr;
2788 msr_info->data = svm->nested.vm_cr_msr;
2790 case MSR_IA32_SPEC_CTRL:
2791 if (!msr_info->host_initiated &&
2792 !guest_has_spec_ctrl_msr(vcpu))
2795 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2796 msr_info->data = svm->vmcb->save.spec_ctrl;
2798 msr_info->data = svm->spec_ctrl;
2800 case MSR_AMD64_VIRT_SPEC_CTRL:
2801 if (!msr_info->host_initiated &&
2802 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2805 msr_info->data = svm->virt_spec_ctrl;
2807 case MSR_F15H_IC_CFG: {
2811 family = guest_cpuid_family(vcpu);
2812 model = guest_cpuid_model(vcpu);
2814 if (family < 0 || model < 0)
2815 return kvm_get_msr_common(vcpu, msr_info);
2819 if (family == 0x15 &&
2820 (model >= 0x2 && model < 0x20))
2821 msr_info->data = 0x1E;
2824 case MSR_F10H_DECFG:
2825 msr_info->data = svm->msr_decfg;
2828 return kvm_get_msr_common(vcpu, msr_info);
2833 static int svm_complete_emulated_msr(struct kvm_vcpu *vcpu, int err)
2835 struct vcpu_svm *svm = to_svm(vcpu);
2836 if (!err || !sev_es_guest(vcpu->kvm) || WARN_ON_ONCE(!svm->sev_es.ghcb))
2837 return kvm_complete_insn_gp(vcpu, err);
2839 ghcb_set_sw_exit_info_1(svm->sev_es.ghcb, 1);
2840 ghcb_set_sw_exit_info_2(svm->sev_es.ghcb,
2842 SVM_EVTINJ_TYPE_EXEPT |
2847 static int svm_set_vm_cr(struct kvm_vcpu *vcpu, u64 data)
2849 struct vcpu_svm *svm = to_svm(vcpu);
2850 int svm_dis, chg_mask;
2852 if (data & ~SVM_VM_CR_VALID_MASK)
2855 chg_mask = SVM_VM_CR_VALID_MASK;
2857 if (svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK)
2858 chg_mask &= ~(SVM_VM_CR_SVM_LOCK_MASK | SVM_VM_CR_SVM_DIS_MASK);
2860 svm->nested.vm_cr_msr &= ~chg_mask;
2861 svm->nested.vm_cr_msr |= (data & chg_mask);
2863 svm_dis = svm->nested.vm_cr_msr & SVM_VM_CR_SVM_DIS_MASK;
2865 /* check for svm_disable while efer.svme is set */
2866 if (svm_dis && (vcpu->arch.efer & EFER_SVME))
2872 static int svm_set_msr(struct kvm_vcpu *vcpu, struct msr_data *msr)
2874 struct vcpu_svm *svm = to_svm(vcpu);
2877 u32 ecx = msr->index;
2878 u64 data = msr->data;
2880 case MSR_AMD64_TSC_RATIO:
2882 if (!svm->tsc_scaling_enabled) {
2884 if (!msr->host_initiated)
2887 * In case TSC scaling is not enabled, always
2888 * leave this MSR at the default value.
2890 * Due to bug in qemu 6.2.0, it would try to set
2891 * this msr to 0 if tsc scaling is not enabled.
2892 * Ignore this value as well.
2894 if (data != 0 && data != svm->tsc_ratio_msr)
2899 if (data & SVM_TSC_RATIO_RSVD)
2902 svm->tsc_ratio_msr = data;
2904 if (svm->tsc_scaling_enabled && is_guest_mode(vcpu))
2905 nested_svm_update_tsc_ratio_msr(vcpu);
2908 case MSR_IA32_CR_PAT:
2909 if (!kvm_mtrr_valid(vcpu, MSR_IA32_CR_PAT, data))
2911 vcpu->arch.pat = data;
2912 svm->vmcb01.ptr->save.g_pat = data;
2913 if (is_guest_mode(vcpu))
2914 nested_vmcb02_compute_g_pat(svm);
2915 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
2917 case MSR_IA32_SPEC_CTRL:
2918 if (!msr->host_initiated &&
2919 !guest_has_spec_ctrl_msr(vcpu))
2922 if (kvm_spec_ctrl_test_value(data))
2925 if (boot_cpu_has(X86_FEATURE_V_SPEC_CTRL))
2926 svm->vmcb->save.spec_ctrl = data;
2928 svm->spec_ctrl = data;
2934 * When it's written (to non-zero) for the first time, pass
2938 * The handling of the MSR bitmap for L2 guests is done in
2939 * nested_svm_vmrun_msrpm.
2940 * We update the L1 MSR bit as well since it will end up
2941 * touching the MSR anyway now.
2943 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_SPEC_CTRL, 1, 1);
2945 case MSR_IA32_PRED_CMD:
2946 if (!msr->host_initiated &&
2947 !guest_has_pred_cmd_msr(vcpu))
2950 if (data & ~PRED_CMD_IBPB)
2952 if (!boot_cpu_has(X86_FEATURE_IBPB))
2957 wrmsrl(MSR_IA32_PRED_CMD, PRED_CMD_IBPB);
2958 set_msr_interception(vcpu, svm->msrpm, MSR_IA32_PRED_CMD, 0, 1);
2960 case MSR_AMD64_VIRT_SPEC_CTRL:
2961 if (!msr->host_initiated &&
2962 !guest_cpuid_has(vcpu, X86_FEATURE_VIRT_SSBD))
2965 if (data & ~SPEC_CTRL_SSBD)
2968 svm->virt_spec_ctrl = data;
2971 svm->vmcb01.ptr->save.star = data;
2973 #ifdef CONFIG_X86_64
2975 svm->vmcb01.ptr->save.lstar = data;
2978 svm->vmcb01.ptr->save.cstar = data;
2980 case MSR_KERNEL_GS_BASE:
2981 svm->vmcb01.ptr->save.kernel_gs_base = data;
2983 case MSR_SYSCALL_MASK:
2984 svm->vmcb01.ptr->save.sfmask = data;
2987 case MSR_IA32_SYSENTER_CS:
2988 svm->vmcb01.ptr->save.sysenter_cs = data;
2990 case MSR_IA32_SYSENTER_EIP:
2991 svm->vmcb01.ptr->save.sysenter_eip = (u32)data;
2993 * We only intercept the MSR_IA32_SYSENTER_{EIP|ESP} msrs
2994 * when we spoof an Intel vendor ID (for cross vendor migration).
2995 * In this case we use this intercept to track the high
2996 * 32 bit part of these msrs to support Intel's
2997 * implementation of SYSENTER/SYSEXIT.
2999 svm->sysenter_eip_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
3001 case MSR_IA32_SYSENTER_ESP:
3002 svm->vmcb01.ptr->save.sysenter_esp = (u32)data;
3003 svm->sysenter_esp_hi = guest_cpuid_is_intel(vcpu) ? (data >> 32) : 0;
3007 * TSC_AUX is usually changed only during boot and never read
3008 * directly. Intercept TSC_AUX instead of exposing it to the
3009 * guest via direct_access_msrs, and switch it via user return.
3012 r = kvm_set_user_return_msr(tsc_aux_uret_slot, data, -1ull);
3017 svm->tsc_aux = data;
3019 case MSR_IA32_DEBUGCTLMSR:
3021 vcpu_unimpl(vcpu, "%s: MSR_IA32_DEBUGCTL 0x%llx, nop\n",
3025 if (data & DEBUGCTL_RESERVED_BITS)
3028 if (svm->vmcb->control.virt_ext & LBR_CTL_ENABLE_MASK)
3029 svm->vmcb->save.dbgctl = data;
3031 svm->vmcb01.ptr->save.dbgctl = data;
3033 svm_update_lbrv(vcpu);
3036 case MSR_VM_HSAVE_PA:
3038 * Old kernels did not validate the value written to
3039 * MSR_VM_HSAVE_PA. Allow KVM_SET_MSR to set an invalid
3040 * value to allow live migrating buggy or malicious guests
3041 * originating from those kernels.
3043 if (!msr->host_initiated && !page_address_valid(vcpu, data))
3046 svm->nested.hsave_msr = data & PAGE_MASK;
3049 return svm_set_vm_cr(vcpu, data);
3051 vcpu_unimpl(vcpu, "unimplemented wrmsr: 0x%x data 0x%llx\n", ecx, data);
3053 case MSR_F10H_DECFG: {
3054 struct kvm_msr_entry msr_entry;
3056 msr_entry.index = msr->index;
3057 if (svm_get_msr_feature(&msr_entry))
3060 /* Check the supported bits */
3061 if (data & ~msr_entry.data)
3064 /* Don't allow the guest to change a bit, #GP */
3065 if (!msr->host_initiated && (data ^ msr_entry.data))
3068 svm->msr_decfg = data;
3072 return kvm_set_msr_common(vcpu, msr);
3077 static int msr_interception(struct kvm_vcpu *vcpu)
3079 if (to_svm(vcpu)->vmcb->control.exit_info_1)
3080 return kvm_emulate_wrmsr(vcpu);
3082 return kvm_emulate_rdmsr(vcpu);
3085 static int interrupt_window_interception(struct kvm_vcpu *vcpu)
3087 kvm_make_request(KVM_REQ_EVENT, vcpu);
3088 svm_clear_vintr(to_svm(vcpu));
3091 * If not running nested, for AVIC, the only reason to end up here is ExtINTs.
3092 * In this case AVIC was temporarily disabled for
3093 * requesting the IRQ window and we have to re-enable it.
3095 * If running nested, still remove the VM wide AVIC inhibit to
3096 * support case in which the interrupt window was requested when the
3097 * vCPU was not running nested.
3099 * All vCPUs which run still run nested, will remain to have their
3100 * AVIC still inhibited due to per-cpu AVIC inhibition.
3102 kvm_clear_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3104 ++vcpu->stat.irq_window_exits;
3108 static int pause_interception(struct kvm_vcpu *vcpu)
3112 * CPL is not made available for an SEV-ES guest, therefore
3113 * vcpu->arch.preempted_in_kernel can never be true. Just
3114 * set in_kernel to false as well.
3116 in_kernel = !sev_es_guest(vcpu->kvm) && svm_get_cpl(vcpu) == 0;
3118 grow_ple_window(vcpu);
3120 kvm_vcpu_on_spin(vcpu, in_kernel);
3121 return kvm_skip_emulated_instruction(vcpu);
3124 static int invpcid_interception(struct kvm_vcpu *vcpu)
3126 struct vcpu_svm *svm = to_svm(vcpu);
3130 if (!guest_cpuid_has(vcpu, X86_FEATURE_INVPCID)) {
3131 kvm_queue_exception(vcpu, UD_VECTOR);
3136 * For an INVPCID intercept:
3137 * EXITINFO1 provides the linear address of the memory operand.
3138 * EXITINFO2 provides the contents of the register operand.
3140 type = svm->vmcb->control.exit_info_2;
3141 gva = svm->vmcb->control.exit_info_1;
3143 return kvm_handle_invpcid(vcpu, type, gva);
3146 static int (*const svm_exit_handlers[])(struct kvm_vcpu *vcpu) = {
3147 [SVM_EXIT_READ_CR0] = cr_interception,
3148 [SVM_EXIT_READ_CR3] = cr_interception,
3149 [SVM_EXIT_READ_CR4] = cr_interception,
3150 [SVM_EXIT_READ_CR8] = cr_interception,
3151 [SVM_EXIT_CR0_SEL_WRITE] = cr_interception,
3152 [SVM_EXIT_WRITE_CR0] = cr_interception,
3153 [SVM_EXIT_WRITE_CR3] = cr_interception,
3154 [SVM_EXIT_WRITE_CR4] = cr_interception,
3155 [SVM_EXIT_WRITE_CR8] = cr8_write_interception,
3156 [SVM_EXIT_READ_DR0] = dr_interception,
3157 [SVM_EXIT_READ_DR1] = dr_interception,
3158 [SVM_EXIT_READ_DR2] = dr_interception,
3159 [SVM_EXIT_READ_DR3] = dr_interception,
3160 [SVM_EXIT_READ_DR4] = dr_interception,
3161 [SVM_EXIT_READ_DR5] = dr_interception,
3162 [SVM_EXIT_READ_DR6] = dr_interception,
3163 [SVM_EXIT_READ_DR7] = dr_interception,
3164 [SVM_EXIT_WRITE_DR0] = dr_interception,
3165 [SVM_EXIT_WRITE_DR1] = dr_interception,
3166 [SVM_EXIT_WRITE_DR2] = dr_interception,
3167 [SVM_EXIT_WRITE_DR3] = dr_interception,
3168 [SVM_EXIT_WRITE_DR4] = dr_interception,
3169 [SVM_EXIT_WRITE_DR5] = dr_interception,
3170 [SVM_EXIT_WRITE_DR6] = dr_interception,
3171 [SVM_EXIT_WRITE_DR7] = dr_interception,
3172 [SVM_EXIT_EXCP_BASE + DB_VECTOR] = db_interception,
3173 [SVM_EXIT_EXCP_BASE + BP_VECTOR] = bp_interception,
3174 [SVM_EXIT_EXCP_BASE + UD_VECTOR] = ud_interception,
3175 [SVM_EXIT_EXCP_BASE + PF_VECTOR] = pf_interception,
3176 [SVM_EXIT_EXCP_BASE + MC_VECTOR] = mc_interception,
3177 [SVM_EXIT_EXCP_BASE + AC_VECTOR] = ac_interception,
3178 [SVM_EXIT_EXCP_BASE + GP_VECTOR] = gp_interception,
3179 [SVM_EXIT_INTR] = intr_interception,
3180 [SVM_EXIT_NMI] = nmi_interception,
3181 [SVM_EXIT_SMI] = smi_interception,
3182 [SVM_EXIT_VINTR] = interrupt_window_interception,
3183 [SVM_EXIT_RDPMC] = kvm_emulate_rdpmc,
3184 [SVM_EXIT_CPUID] = kvm_emulate_cpuid,
3185 [SVM_EXIT_IRET] = iret_interception,
3186 [SVM_EXIT_INVD] = kvm_emulate_invd,
3187 [SVM_EXIT_PAUSE] = pause_interception,
3188 [SVM_EXIT_HLT] = kvm_emulate_halt,
3189 [SVM_EXIT_INVLPG] = invlpg_interception,
3190 [SVM_EXIT_INVLPGA] = invlpga_interception,
3191 [SVM_EXIT_IOIO] = io_interception,
3192 [SVM_EXIT_MSR] = msr_interception,
3193 [SVM_EXIT_TASK_SWITCH] = task_switch_interception,
3194 [SVM_EXIT_SHUTDOWN] = shutdown_interception,
3195 [SVM_EXIT_VMRUN] = vmrun_interception,
3196 [SVM_EXIT_VMMCALL] = kvm_emulate_hypercall,
3197 [SVM_EXIT_VMLOAD] = vmload_interception,
3198 [SVM_EXIT_VMSAVE] = vmsave_interception,
3199 [SVM_EXIT_STGI] = stgi_interception,
3200 [SVM_EXIT_CLGI] = clgi_interception,
3201 [SVM_EXIT_SKINIT] = skinit_interception,
3202 [SVM_EXIT_RDTSCP] = kvm_handle_invalid_op,
3203 [SVM_EXIT_WBINVD] = kvm_emulate_wbinvd,
3204 [SVM_EXIT_MONITOR] = kvm_emulate_monitor,
3205 [SVM_EXIT_MWAIT] = kvm_emulate_mwait,
3206 [SVM_EXIT_XSETBV] = kvm_emulate_xsetbv,
3207 [SVM_EXIT_RDPRU] = kvm_handle_invalid_op,
3208 [SVM_EXIT_EFER_WRITE_TRAP] = efer_trap,
3209 [SVM_EXIT_CR0_WRITE_TRAP] = cr_trap,
3210 [SVM_EXIT_CR4_WRITE_TRAP] = cr_trap,
3211 [SVM_EXIT_CR8_WRITE_TRAP] = cr_trap,
3212 [SVM_EXIT_INVPCID] = invpcid_interception,
3213 [SVM_EXIT_NPF] = npf_interception,
3214 [SVM_EXIT_RSM] = rsm_interception,
3215 [SVM_EXIT_AVIC_INCOMPLETE_IPI] = avic_incomplete_ipi_interception,
3216 [SVM_EXIT_AVIC_UNACCELERATED_ACCESS] = avic_unaccelerated_access_interception,
3217 [SVM_EXIT_VMGEXIT] = sev_handle_vmgexit,
3220 static void dump_vmcb(struct kvm_vcpu *vcpu)
3222 struct vcpu_svm *svm = to_svm(vcpu);
3223 struct vmcb_control_area *control = &svm->vmcb->control;
3224 struct vmcb_save_area *save = &svm->vmcb->save;
3225 struct vmcb_save_area *save01 = &svm->vmcb01.ptr->save;
3227 if (!dump_invalid_vmcb) {
3228 pr_warn_ratelimited("set kvm_amd.dump_invalid_vmcb=1 to dump internal KVM state.\n");
3232 pr_err("VMCB %p, last attempted VMRUN on CPU %d\n",
3233 svm->current_vmcb->ptr, vcpu->arch.last_vmentry_cpu);
3234 pr_err("VMCB Control Area:\n");
3235 pr_err("%-20s%04x\n", "cr_read:", control->intercepts[INTERCEPT_CR] & 0xffff);
3236 pr_err("%-20s%04x\n", "cr_write:", control->intercepts[INTERCEPT_CR] >> 16);
3237 pr_err("%-20s%04x\n", "dr_read:", control->intercepts[INTERCEPT_DR] & 0xffff);
3238 pr_err("%-20s%04x\n", "dr_write:", control->intercepts[INTERCEPT_DR] >> 16);
3239 pr_err("%-20s%08x\n", "exceptions:", control->intercepts[INTERCEPT_EXCEPTION]);
3240 pr_err("%-20s%08x %08x\n", "intercepts:",
3241 control->intercepts[INTERCEPT_WORD3],
3242 control->intercepts[INTERCEPT_WORD4]);
3243 pr_err("%-20s%d\n", "pause filter count:", control->pause_filter_count);
3244 pr_err("%-20s%d\n", "pause filter threshold:",
3245 control->pause_filter_thresh);
3246 pr_err("%-20s%016llx\n", "iopm_base_pa:", control->iopm_base_pa);
3247 pr_err("%-20s%016llx\n", "msrpm_base_pa:", control->msrpm_base_pa);
3248 pr_err("%-20s%016llx\n", "tsc_offset:", control->tsc_offset);
3249 pr_err("%-20s%d\n", "asid:", control->asid);
3250 pr_err("%-20s%d\n", "tlb_ctl:", control->tlb_ctl);
3251 pr_err("%-20s%08x\n", "int_ctl:", control->int_ctl);
3252 pr_err("%-20s%08x\n", "int_vector:", control->int_vector);
3253 pr_err("%-20s%08x\n", "int_state:", control->int_state);
3254 pr_err("%-20s%08x\n", "exit_code:", control->exit_code);
3255 pr_err("%-20s%016llx\n", "exit_info1:", control->exit_info_1);
3256 pr_err("%-20s%016llx\n", "exit_info2:", control->exit_info_2);
3257 pr_err("%-20s%08x\n", "exit_int_info:", control->exit_int_info);
3258 pr_err("%-20s%08x\n", "exit_int_info_err:", control->exit_int_info_err);
3259 pr_err("%-20s%lld\n", "nested_ctl:", control->nested_ctl);
3260 pr_err("%-20s%016llx\n", "nested_cr3:", control->nested_cr3);
3261 pr_err("%-20s%016llx\n", "avic_vapic_bar:", control->avic_vapic_bar);
3262 pr_err("%-20s%016llx\n", "ghcb:", control->ghcb_gpa);
3263 pr_err("%-20s%08x\n", "event_inj:", control->event_inj);
3264 pr_err("%-20s%08x\n", "event_inj_err:", control->event_inj_err);
3265 pr_err("%-20s%lld\n", "virt_ext:", control->virt_ext);
3266 pr_err("%-20s%016llx\n", "next_rip:", control->next_rip);
3267 pr_err("%-20s%016llx\n", "avic_backing_page:", control->avic_backing_page);
3268 pr_err("%-20s%016llx\n", "avic_logical_id:", control->avic_logical_id);
3269 pr_err("%-20s%016llx\n", "avic_physical_id:", control->avic_physical_id);
3270 pr_err("%-20s%016llx\n", "vmsa_pa:", control->vmsa_pa);
3271 pr_err("VMCB State Save Area:\n");
3272 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3274 save->es.selector, save->es.attrib,
3275 save->es.limit, save->es.base);
3276 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3278 save->cs.selector, save->cs.attrib,
3279 save->cs.limit, save->cs.base);
3280 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3282 save->ss.selector, save->ss.attrib,
3283 save->ss.limit, save->ss.base);
3284 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3286 save->ds.selector, save->ds.attrib,
3287 save->ds.limit, save->ds.base);
3288 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3290 save01->fs.selector, save01->fs.attrib,
3291 save01->fs.limit, save01->fs.base);
3292 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3294 save01->gs.selector, save01->gs.attrib,
3295 save01->gs.limit, save01->gs.base);
3296 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3298 save->gdtr.selector, save->gdtr.attrib,
3299 save->gdtr.limit, save->gdtr.base);
3300 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3302 save01->ldtr.selector, save01->ldtr.attrib,
3303 save01->ldtr.limit, save01->ldtr.base);
3304 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3306 save->idtr.selector, save->idtr.attrib,
3307 save->idtr.limit, save->idtr.base);
3308 pr_err("%-5s s: %04x a: %04x l: %08x b: %016llx\n",
3310 save01->tr.selector, save01->tr.attrib,
3311 save01->tr.limit, save01->tr.base);
3312 pr_err("vmpl: %d cpl: %d efer: %016llx\n",
3313 save->vmpl, save->cpl, save->efer);
3314 pr_err("%-15s %016llx %-13s %016llx\n",
3315 "cr0:", save->cr0, "cr2:", save->cr2);
3316 pr_err("%-15s %016llx %-13s %016llx\n",
3317 "cr3:", save->cr3, "cr4:", save->cr4);
3318 pr_err("%-15s %016llx %-13s %016llx\n",
3319 "dr6:", save->dr6, "dr7:", save->dr7);
3320 pr_err("%-15s %016llx %-13s %016llx\n",
3321 "rip:", save->rip, "rflags:", save->rflags);
3322 pr_err("%-15s %016llx %-13s %016llx\n",
3323 "rsp:", save->rsp, "rax:", save->rax);
3324 pr_err("%-15s %016llx %-13s %016llx\n",
3325 "star:", save01->star, "lstar:", save01->lstar);
3326 pr_err("%-15s %016llx %-13s %016llx\n",
3327 "cstar:", save01->cstar, "sfmask:", save01->sfmask);
3328 pr_err("%-15s %016llx %-13s %016llx\n",
3329 "kernel_gs_base:", save01->kernel_gs_base,
3330 "sysenter_cs:", save01->sysenter_cs);
3331 pr_err("%-15s %016llx %-13s %016llx\n",
3332 "sysenter_esp:", save01->sysenter_esp,
3333 "sysenter_eip:", save01->sysenter_eip);
3334 pr_err("%-15s %016llx %-13s %016llx\n",
3335 "gpat:", save->g_pat, "dbgctl:", save->dbgctl);
3336 pr_err("%-15s %016llx %-13s %016llx\n",
3337 "br_from:", save->br_from, "br_to:", save->br_to);
3338 pr_err("%-15s %016llx %-13s %016llx\n",
3339 "excp_from:", save->last_excp_from,
3340 "excp_to:", save->last_excp_to);
3343 static bool svm_check_exit_valid(u64 exit_code)
3345 return (exit_code < ARRAY_SIZE(svm_exit_handlers) &&
3346 svm_exit_handlers[exit_code]);
3349 static int svm_handle_invalid_exit(struct kvm_vcpu *vcpu, u64 exit_code)
3351 vcpu_unimpl(vcpu, "svm: unexpected exit reason 0x%llx\n", exit_code);
3353 vcpu->run->exit_reason = KVM_EXIT_INTERNAL_ERROR;
3354 vcpu->run->internal.suberror = KVM_INTERNAL_ERROR_UNEXPECTED_EXIT_REASON;
3355 vcpu->run->internal.ndata = 2;
3356 vcpu->run->internal.data[0] = exit_code;
3357 vcpu->run->internal.data[1] = vcpu->arch.last_vmentry_cpu;
3361 int svm_invoke_exit_handler(struct kvm_vcpu *vcpu, u64 exit_code)
3363 if (!svm_check_exit_valid(exit_code))
3364 return svm_handle_invalid_exit(vcpu, exit_code);
3366 #ifdef CONFIG_RETPOLINE
3367 if (exit_code == SVM_EXIT_MSR)
3368 return msr_interception(vcpu);
3369 else if (exit_code == SVM_EXIT_VINTR)
3370 return interrupt_window_interception(vcpu);
3371 else if (exit_code == SVM_EXIT_INTR)
3372 return intr_interception(vcpu);
3373 else if (exit_code == SVM_EXIT_HLT)
3374 return kvm_emulate_halt(vcpu);
3375 else if (exit_code == SVM_EXIT_NPF)
3376 return npf_interception(vcpu);
3378 return svm_exit_handlers[exit_code](vcpu);
3381 static void svm_get_exit_info(struct kvm_vcpu *vcpu, u32 *reason,
3382 u64 *info1, u64 *info2,
3383 u32 *intr_info, u32 *error_code)
3385 struct vmcb_control_area *control = &to_svm(vcpu)->vmcb->control;
3387 *reason = control->exit_code;
3388 *info1 = control->exit_info_1;
3389 *info2 = control->exit_info_2;
3390 *intr_info = control->exit_int_info;
3391 if ((*intr_info & SVM_EXITINTINFO_VALID) &&
3392 (*intr_info & SVM_EXITINTINFO_VALID_ERR))
3393 *error_code = control->exit_int_info_err;
3398 static int svm_handle_exit(struct kvm_vcpu *vcpu, fastpath_t exit_fastpath)
3400 struct vcpu_svm *svm = to_svm(vcpu);
3401 struct kvm_run *kvm_run = vcpu->run;
3402 u32 exit_code = svm->vmcb->control.exit_code;
3404 trace_kvm_exit(vcpu, KVM_ISA_SVM);
3406 /* SEV-ES guests must use the CR write traps to track CR registers. */
3407 if (!sev_es_guest(vcpu->kvm)) {
3408 if (!svm_is_intercept(svm, INTERCEPT_CR0_WRITE))
3409 vcpu->arch.cr0 = svm->vmcb->save.cr0;
3411 vcpu->arch.cr3 = svm->vmcb->save.cr3;
3414 if (is_guest_mode(vcpu)) {
3417 trace_kvm_nested_vmexit(vcpu, KVM_ISA_SVM);
3419 vmexit = nested_svm_exit_special(svm);
3421 if (vmexit == NESTED_EXIT_CONTINUE)
3422 vmexit = nested_svm_exit_handled(svm);
3424 if (vmexit == NESTED_EXIT_DONE)
3428 if (svm->vmcb->control.exit_code == SVM_EXIT_ERR) {
3429 kvm_run->exit_reason = KVM_EXIT_FAIL_ENTRY;
3430 kvm_run->fail_entry.hardware_entry_failure_reason
3431 = svm->vmcb->control.exit_code;
3432 kvm_run->fail_entry.cpu = vcpu->arch.last_vmentry_cpu;
3437 if (is_external_interrupt(svm->vmcb->control.exit_int_info) &&
3438 exit_code != SVM_EXIT_EXCP_BASE + PF_VECTOR &&
3439 exit_code != SVM_EXIT_NPF && exit_code != SVM_EXIT_TASK_SWITCH &&
3440 exit_code != SVM_EXIT_INTR && exit_code != SVM_EXIT_NMI)
3441 printk(KERN_ERR "%s: unexpected exit_int_info 0x%x "
3443 __func__, svm->vmcb->control.exit_int_info,
3446 if (exit_fastpath != EXIT_FASTPATH_NONE)
3449 return svm_invoke_exit_handler(vcpu, exit_code);
3452 static void reload_tss(struct kvm_vcpu *vcpu)
3454 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3456 sd->tss_desc->type = 9; /* available 32/64-bit TSS */
3460 static void pre_svm_run(struct kvm_vcpu *vcpu)
3462 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3463 struct vcpu_svm *svm = to_svm(vcpu);
3466 * If the previous vmrun of the vmcb occurred on a different physical
3467 * cpu, then mark the vmcb dirty and assign a new asid. Hardware's
3468 * vmcb clean bits are per logical CPU, as are KVM's asid assignments.
3470 if (unlikely(svm->current_vmcb->cpu != vcpu->cpu)) {
3471 svm->current_vmcb->asid_generation = 0;
3472 vmcb_mark_all_dirty(svm->vmcb);
3473 svm->current_vmcb->cpu = vcpu->cpu;
3476 if (sev_guest(vcpu->kvm))
3477 return pre_sev_run(svm, vcpu->cpu);
3479 /* FIXME: handle wraparound of asid_generation */
3480 if (svm->current_vmcb->asid_generation != sd->asid_generation)
3484 static void svm_inject_nmi(struct kvm_vcpu *vcpu)
3486 struct vcpu_svm *svm = to_svm(vcpu);
3488 svm->vmcb->control.event_inj = SVM_EVTINJ_VALID | SVM_EVTINJ_TYPE_NMI;
3490 if (svm->nmi_l1_to_l2)
3493 vcpu->arch.hflags |= HF_NMI_MASK;
3494 if (!sev_es_guest(vcpu->kvm))
3495 svm_set_intercept(svm, INTERCEPT_IRET);
3496 ++vcpu->stat.nmi_injections;
3499 static void svm_inject_irq(struct kvm_vcpu *vcpu, bool reinjected)
3501 struct vcpu_svm *svm = to_svm(vcpu);
3504 if (vcpu->arch.interrupt.soft) {
3505 if (svm_update_soft_interrupt_rip(vcpu))
3508 type = SVM_EVTINJ_TYPE_SOFT;
3510 type = SVM_EVTINJ_TYPE_INTR;
3513 trace_kvm_inj_virq(vcpu->arch.interrupt.nr,
3514 vcpu->arch.interrupt.soft, reinjected);
3515 ++vcpu->stat.irq_injections;
3517 svm->vmcb->control.event_inj = vcpu->arch.interrupt.nr |
3518 SVM_EVTINJ_VALID | type;
3521 void svm_complete_interrupt_delivery(struct kvm_vcpu *vcpu, int delivery_mode,
3522 int trig_mode, int vector)
3525 * apic->apicv_active must be read after vcpu->mode.
3526 * Pairs with smp_store_release in vcpu_enter_guest.
3528 bool in_guest_mode = (smp_load_acquire(&vcpu->mode) == IN_GUEST_MODE);
3530 /* Note, this is called iff the local APIC is in-kernel. */
3531 if (!READ_ONCE(vcpu->arch.apic->apicv_active)) {
3532 /* Process the interrupt via inject_pending_event */
3533 kvm_make_request(KVM_REQ_EVENT, vcpu);
3534 kvm_vcpu_kick(vcpu);
3538 trace_kvm_apicv_accept_irq(vcpu->vcpu_id, delivery_mode, trig_mode, vector);
3539 if (in_guest_mode) {
3541 * Signal the doorbell to tell hardware to inject the IRQ. If
3542 * the vCPU exits the guest before the doorbell chimes, hardware
3543 * will automatically process AVIC interrupts at the next VMRUN.
3545 avic_ring_doorbell(vcpu);
3548 * Wake the vCPU if it was blocking. KVM will then detect the
3549 * pending IRQ when checking if the vCPU has a wake event.
3551 kvm_vcpu_wake_up(vcpu);
3555 static void svm_deliver_interrupt(struct kvm_lapic *apic, int delivery_mode,
3556 int trig_mode, int vector)
3558 kvm_lapic_set_irr(vector, apic);
3561 * Pairs with the smp_mb_*() after setting vcpu->guest_mode in
3562 * vcpu_enter_guest() to ensure the write to the vIRR is ordered before
3563 * the read of guest_mode. This guarantees that either VMRUN will see
3564 * and process the new vIRR entry, or that svm_complete_interrupt_delivery
3565 * will signal the doorbell if the CPU has already entered the guest.
3567 smp_mb__after_atomic();
3568 svm_complete_interrupt_delivery(apic->vcpu, delivery_mode, trig_mode, vector);
3571 static void svm_update_cr8_intercept(struct kvm_vcpu *vcpu, int tpr, int irr)
3573 struct vcpu_svm *svm = to_svm(vcpu);
3576 * SEV-ES guests must always keep the CR intercepts cleared. CR
3577 * tracking is done using the CR write traps.
3579 if (sev_es_guest(vcpu->kvm))
3582 if (nested_svm_virtualize_tpr(vcpu))
3585 svm_clr_intercept(svm, INTERCEPT_CR8_WRITE);
3591 svm_set_intercept(svm, INTERCEPT_CR8_WRITE);
3594 bool svm_nmi_blocked(struct kvm_vcpu *vcpu)
3596 struct vcpu_svm *svm = to_svm(vcpu);
3597 struct vmcb *vmcb = svm->vmcb;
3603 if (is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3606 ret = (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK) ||
3607 (vcpu->arch.hflags & HF_NMI_MASK);
3612 static int svm_nmi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3614 struct vcpu_svm *svm = to_svm(vcpu);
3615 if (svm->nested.nested_run_pending)
3618 if (svm_nmi_blocked(vcpu))
3621 /* An NMI must not be injected into L2 if it's supposed to VM-Exit. */
3622 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_nmi(svm))
3627 static bool svm_get_nmi_mask(struct kvm_vcpu *vcpu)
3629 return !!(vcpu->arch.hflags & HF_NMI_MASK);
3632 static void svm_set_nmi_mask(struct kvm_vcpu *vcpu, bool masked)
3634 struct vcpu_svm *svm = to_svm(vcpu);
3637 vcpu->arch.hflags |= HF_NMI_MASK;
3638 if (!sev_es_guest(vcpu->kvm))
3639 svm_set_intercept(svm, INTERCEPT_IRET);
3641 vcpu->arch.hflags &= ~HF_NMI_MASK;
3642 if (!sev_es_guest(vcpu->kvm))
3643 svm_clr_intercept(svm, INTERCEPT_IRET);
3647 bool svm_interrupt_blocked(struct kvm_vcpu *vcpu)
3649 struct vcpu_svm *svm = to_svm(vcpu);
3650 struct vmcb *vmcb = svm->vmcb;
3655 if (is_guest_mode(vcpu)) {
3656 /* As long as interrupts are being delivered... */
3657 if ((svm->nested.ctl.int_ctl & V_INTR_MASKING_MASK)
3658 ? !(svm->vmcb01.ptr->save.rflags & X86_EFLAGS_IF)
3659 : !(kvm_get_rflags(vcpu) & X86_EFLAGS_IF))
3662 /* ... vmexits aren't blocked by the interrupt shadow */
3663 if (nested_exit_on_intr(svm))
3666 if (!svm_get_if_flag(vcpu))
3670 return (vmcb->control.int_state & SVM_INTERRUPT_SHADOW_MASK);
3673 static int svm_interrupt_allowed(struct kvm_vcpu *vcpu, bool for_injection)
3675 struct vcpu_svm *svm = to_svm(vcpu);
3677 if (svm->nested.nested_run_pending)
3680 if (svm_interrupt_blocked(vcpu))
3684 * An IRQ must not be injected into L2 if it's supposed to VM-Exit,
3685 * e.g. if the IRQ arrived asynchronously after checking nested events.
3687 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_intr(svm))
3693 static void svm_enable_irq_window(struct kvm_vcpu *vcpu)
3695 struct vcpu_svm *svm = to_svm(vcpu);
3698 * In case GIF=0 we can't rely on the CPU to tell us when GIF becomes
3699 * 1, because that's a separate STGI/VMRUN intercept. The next time we
3700 * get that intercept, this function will be called again though and
3701 * we'll get the vintr intercept. However, if the vGIF feature is
3702 * enabled, the STGI interception will not occur. Enable the irq
3703 * window under the assumption that the hardware will set the GIF.
3705 if (vgif || gif_set(svm)) {
3707 * IRQ window is not needed when AVIC is enabled,
3708 * unless we have pending ExtINT since it cannot be injected
3709 * via AVIC. In such case, KVM needs to temporarily disable AVIC,
3710 * and fallback to injecting IRQ via V_IRQ.
3712 * If running nested, AVIC is already locally inhibited
3713 * on this vCPU, therefore there is no need to request
3714 * the VM wide AVIC inhibition.
3716 if (!is_guest_mode(vcpu))
3717 kvm_set_apicv_inhibit(vcpu->kvm, APICV_INHIBIT_REASON_IRQWIN);
3723 static void svm_enable_nmi_window(struct kvm_vcpu *vcpu)
3725 struct vcpu_svm *svm = to_svm(vcpu);
3727 if ((vcpu->arch.hflags & (HF_NMI_MASK | HF_IRET_MASK)) == HF_NMI_MASK)
3728 return; /* IRET will cause a vm exit */
3730 if (!gif_set(svm)) {
3732 svm_set_intercept(svm, INTERCEPT_STGI);
3733 return; /* STGI will cause a vm exit */
3737 * Something prevents NMI from been injected. Single step over possible
3738 * problem (IRET or exception injection or interrupt shadow)
3740 svm->nmi_singlestep_guest_rflags = svm_get_rflags(vcpu);
3741 svm->nmi_singlestep = true;
3742 svm->vmcb->save.rflags |= (X86_EFLAGS_TF | X86_EFLAGS_RF);
3745 static void svm_flush_tlb_current(struct kvm_vcpu *vcpu)
3747 struct vcpu_svm *svm = to_svm(vcpu);
3750 * Flush only the current ASID even if the TLB flush was invoked via
3751 * kvm_flush_remote_tlbs(). Although flushing remote TLBs requires all
3752 * ASIDs to be flushed, KVM uses a single ASID for L1 and L2, and
3753 * unconditionally does a TLB flush on both nested VM-Enter and nested
3754 * VM-Exit (via kvm_mmu_reset_context()).
3756 if (static_cpu_has(X86_FEATURE_FLUSHBYASID))
3757 svm->vmcb->control.tlb_ctl = TLB_CONTROL_FLUSH_ASID;
3759 svm->current_vmcb->asid_generation--;
3762 static void svm_flush_tlb_gva(struct kvm_vcpu *vcpu, gva_t gva)
3764 struct vcpu_svm *svm = to_svm(vcpu);
3766 invlpga(gva, svm->vmcb->control.asid);
3769 static inline void sync_cr8_to_lapic(struct kvm_vcpu *vcpu)
3771 struct vcpu_svm *svm = to_svm(vcpu);
3773 if (nested_svm_virtualize_tpr(vcpu))
3776 if (!svm_is_intercept(svm, INTERCEPT_CR8_WRITE)) {
3777 int cr8 = svm->vmcb->control.int_ctl & V_TPR_MASK;
3778 kvm_set_cr8(vcpu, cr8);
3782 static inline void sync_lapic_to_cr8(struct kvm_vcpu *vcpu)
3784 struct vcpu_svm *svm = to_svm(vcpu);
3787 if (nested_svm_virtualize_tpr(vcpu) ||
3788 kvm_vcpu_apicv_active(vcpu))
3791 cr8 = kvm_get_cr8(vcpu);
3792 svm->vmcb->control.int_ctl &= ~V_TPR_MASK;
3793 svm->vmcb->control.int_ctl |= cr8 & V_TPR_MASK;
3796 static void svm_complete_soft_interrupt(struct kvm_vcpu *vcpu, u8 vector,
3799 bool is_exception = (type == SVM_EXITINTINFO_TYPE_EXEPT);
3800 bool is_soft = (type == SVM_EXITINTINFO_TYPE_SOFT);
3801 struct vcpu_svm *svm = to_svm(vcpu);
3804 * If NRIPS is enabled, KVM must snapshot the pre-VMRUN next_rip that's
3805 * associated with the original soft exception/interrupt. next_rip is
3806 * cleared on all exits that can occur while vectoring an event, so KVM
3807 * needs to manually set next_rip for re-injection. Unlike the !nrips
3808 * case below, this needs to be done if and only if KVM is re-injecting
3809 * the same event, i.e. if the event is a soft exception/interrupt,
3810 * otherwise next_rip is unused on VMRUN.
3812 if (nrips && (is_soft || (is_exception && kvm_exception_is_soft(vector))) &&
3813 kvm_is_linear_rip(vcpu, svm->soft_int_old_rip + svm->soft_int_csbase))
3814 svm->vmcb->control.next_rip = svm->soft_int_next_rip;
3816 * If NRIPS isn't enabled, KVM must manually advance RIP prior to
3817 * injecting the soft exception/interrupt. That advancement needs to
3818 * be unwound if vectoring didn't complete. Note, the new event may
3819 * not be the injected event, e.g. if KVM injected an INTn, the INTn
3820 * hit a #NP in the guest, and the #NP encountered a #PF, the #NP will
3821 * be the reported vectored event, but RIP still needs to be unwound.
3823 else if (!nrips && (is_soft || is_exception) &&
3824 kvm_is_linear_rip(vcpu, svm->soft_int_next_rip + svm->soft_int_csbase))
3825 kvm_rip_write(vcpu, svm->soft_int_old_rip);
3828 static void svm_complete_interrupts(struct kvm_vcpu *vcpu)
3830 struct vcpu_svm *svm = to_svm(vcpu);
3833 u32 exitintinfo = svm->vmcb->control.exit_int_info;
3834 bool nmi_l1_to_l2 = svm->nmi_l1_to_l2;
3835 bool soft_int_injected = svm->soft_int_injected;
3837 svm->nmi_l1_to_l2 = false;
3838 svm->soft_int_injected = false;
3841 * If we've made progress since setting HF_IRET_MASK, we've
3842 * executed an IRET and can allow NMI injection.
3844 if ((vcpu->arch.hflags & HF_IRET_MASK) &&
3845 (sev_es_guest(vcpu->kvm) ||
3846 kvm_rip_read(vcpu) != svm->nmi_iret_rip)) {
3847 vcpu->arch.hflags &= ~(HF_NMI_MASK | HF_IRET_MASK);
3848 kvm_make_request(KVM_REQ_EVENT, vcpu);
3851 vcpu->arch.nmi_injected = false;
3852 kvm_clear_exception_queue(vcpu);
3853 kvm_clear_interrupt_queue(vcpu);
3855 if (!(exitintinfo & SVM_EXITINTINFO_VALID))
3858 kvm_make_request(KVM_REQ_EVENT, vcpu);
3860 vector = exitintinfo & SVM_EXITINTINFO_VEC_MASK;
3861 type = exitintinfo & SVM_EXITINTINFO_TYPE_MASK;
3863 if (soft_int_injected)
3864 svm_complete_soft_interrupt(vcpu, vector, type);
3867 case SVM_EXITINTINFO_TYPE_NMI:
3868 vcpu->arch.nmi_injected = true;
3869 svm->nmi_l1_to_l2 = nmi_l1_to_l2;
3871 case SVM_EXITINTINFO_TYPE_EXEPT:
3873 * Never re-inject a #VC exception.
3875 if (vector == X86_TRAP_VC)
3878 if (exitintinfo & SVM_EXITINTINFO_VALID_ERR) {
3879 u32 err = svm->vmcb->control.exit_int_info_err;
3880 kvm_requeue_exception_e(vcpu, vector, err);
3883 kvm_requeue_exception(vcpu, vector);
3885 case SVM_EXITINTINFO_TYPE_INTR:
3886 kvm_queue_interrupt(vcpu, vector, false);
3888 case SVM_EXITINTINFO_TYPE_SOFT:
3889 kvm_queue_interrupt(vcpu, vector, true);
3897 static void svm_cancel_injection(struct kvm_vcpu *vcpu)
3899 struct vcpu_svm *svm = to_svm(vcpu);
3900 struct vmcb_control_area *control = &svm->vmcb->control;
3902 control->exit_int_info = control->event_inj;
3903 control->exit_int_info_err = control->event_inj_err;
3904 control->event_inj = 0;
3905 svm_complete_interrupts(vcpu);
3908 static int svm_vcpu_pre_run(struct kvm_vcpu *vcpu)
3913 static fastpath_t svm_exit_handlers_fastpath(struct kvm_vcpu *vcpu)
3915 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_MSR &&
3916 to_svm(vcpu)->vmcb->control.exit_info_1)
3917 return handle_fastpath_set_msr_irqoff(vcpu);
3919 return EXIT_FASTPATH_NONE;
3922 static noinstr void svm_vcpu_enter_exit(struct kvm_vcpu *vcpu)
3924 struct vcpu_svm *svm = to_svm(vcpu);
3925 unsigned long vmcb_pa = svm->current_vmcb->pa;
3927 guest_state_enter_irqoff();
3929 if (sev_es_guest(vcpu->kvm)) {
3930 __svm_sev_es_vcpu_run(vmcb_pa);
3932 struct svm_cpu_data *sd = per_cpu(svm_data, vcpu->cpu);
3935 * Use a single vmcb (vmcb01 because it's always valid) for
3936 * context switching guest state via VMLOAD/VMSAVE, that way
3937 * the state doesn't need to be copied between vmcb01 and
3938 * vmcb02 when switching vmcbs for nested virtualization.
3940 vmload(svm->vmcb01.pa);
3941 __svm_vcpu_run(vmcb_pa, (unsigned long *)&vcpu->arch.regs);
3942 vmsave(svm->vmcb01.pa);
3944 vmload(__sme_page_pa(sd->save_area));
3947 guest_state_exit_irqoff();
3950 static __no_kcsan fastpath_t svm_vcpu_run(struct kvm_vcpu *vcpu)
3952 struct vcpu_svm *svm = to_svm(vcpu);
3954 trace_kvm_entry(vcpu);
3956 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
3957 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
3958 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
3961 * Disable singlestep if we're injecting an interrupt/exception.
3962 * We don't want our modified rflags to be pushed on the stack where
3963 * we might not be able to easily reset them if we disabled NMI
3966 if (svm->nmi_singlestep && svm->vmcb->control.event_inj) {
3968 * Event injection happens before external interrupts cause a
3969 * vmexit and interrupts are disabled here, so smp_send_reschedule
3970 * is enough to force an immediate vmexit.
3972 disable_nmi_singlestep(svm);
3973 smp_send_reschedule(vcpu->cpu);
3978 sync_lapic_to_cr8(vcpu);
3980 if (unlikely(svm->asid != svm->vmcb->control.asid)) {
3981 svm->vmcb->control.asid = svm->asid;
3982 vmcb_mark_dirty(svm->vmcb, VMCB_ASID);
3984 svm->vmcb->save.cr2 = vcpu->arch.cr2;
3986 svm_hv_update_vp_id(svm->vmcb, vcpu);
3989 * Run with all-zero DR6 unless needed, so that we can get the exact cause
3992 if (unlikely(vcpu->arch.switch_db_regs & KVM_DEBUGREG_WONT_EXIT))
3993 svm_set_dr6(svm, vcpu->arch.dr6);
3995 svm_set_dr6(svm, DR6_ACTIVE_LOW);
3998 kvm_load_guest_xsave_state(vcpu);
4000 kvm_wait_lapic_expire(vcpu);
4003 * If this vCPU has touched SPEC_CTRL, restore the guest's value if
4004 * it's non-zero. Since vmentry is serialising on affected CPUs, there
4005 * is no need to worry about the conditional branch over the wrmsr
4006 * being speculatively taken.
4008 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4009 x86_spec_ctrl_set_guest(svm->spec_ctrl, svm->virt_spec_ctrl);
4011 svm_vcpu_enter_exit(vcpu);
4014 * We do not use IBRS in the kernel. If this vCPU has used the
4015 * SPEC_CTRL MSR it may have left it on; save the value and
4016 * turn it off. This is much more efficient than blindly adding
4017 * it to the atomic save/restore list. Especially as the former
4018 * (Saving guest MSRs on vmexit) doesn't even exist in KVM.
4020 * For non-nested case:
4021 * If the L01 MSR bitmap does not intercept the MSR, then we need to
4025 * If the L02 MSR bitmap does not intercept the MSR, then we need to
4028 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL) &&
4029 unlikely(!msr_write_intercepted(vcpu, MSR_IA32_SPEC_CTRL)))
4030 svm->spec_ctrl = native_read_msr(MSR_IA32_SPEC_CTRL);
4032 if (!sev_es_guest(vcpu->kvm))
4035 if (!static_cpu_has(X86_FEATURE_V_SPEC_CTRL))
4036 x86_spec_ctrl_restore_host(svm->spec_ctrl, svm->virt_spec_ctrl);
4038 if (!sev_es_guest(vcpu->kvm)) {
4039 vcpu->arch.cr2 = svm->vmcb->save.cr2;
4040 vcpu->arch.regs[VCPU_REGS_RAX] = svm->vmcb->save.rax;
4041 vcpu->arch.regs[VCPU_REGS_RSP] = svm->vmcb->save.rsp;
4042 vcpu->arch.regs[VCPU_REGS_RIP] = svm->vmcb->save.rip;
4044 vcpu->arch.regs_dirty = 0;
4046 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4047 kvm_before_interrupt(vcpu, KVM_HANDLING_NMI);
4049 kvm_load_host_xsave_state(vcpu);
4052 /* Any pending NMI will happen here */
4054 if (unlikely(svm->vmcb->control.exit_code == SVM_EXIT_NMI))
4055 kvm_after_interrupt(vcpu);
4057 sync_cr8_to_lapic(vcpu);
4060 if (is_guest_mode(vcpu)) {
4061 nested_sync_control_from_vmcb02(svm);
4063 /* Track VMRUNs that have made past consistency checking */
4064 if (svm->nested.nested_run_pending &&
4065 svm->vmcb->control.exit_code != SVM_EXIT_ERR)
4066 ++vcpu->stat.nested_run;
4068 svm->nested.nested_run_pending = 0;
4071 svm->vmcb->control.tlb_ctl = TLB_CONTROL_DO_NOTHING;
4072 vmcb_mark_all_clean(svm->vmcb);
4074 /* if exit due to PF check for async PF */
4075 if (svm->vmcb->control.exit_code == SVM_EXIT_EXCP_BASE + PF_VECTOR)
4076 vcpu->arch.apf.host_apf_flags =
4077 kvm_read_and_reset_apf_flags();
4079 vcpu->arch.regs_avail &= ~SVM_REGS_LAZY_LOAD_SET;
4082 * We need to handle MC intercepts here before the vcpu has a chance to
4083 * change the physical cpu
4085 if (unlikely(svm->vmcb->control.exit_code ==
4086 SVM_EXIT_EXCP_BASE + MC_VECTOR))
4087 svm_handle_mce(vcpu);
4089 svm_complete_interrupts(vcpu);
4091 if (is_guest_mode(vcpu))
4092 return EXIT_FASTPATH_NONE;
4094 return svm_exit_handlers_fastpath(vcpu);
4097 static void svm_load_mmu_pgd(struct kvm_vcpu *vcpu, hpa_t root_hpa,
4100 struct vcpu_svm *svm = to_svm(vcpu);
4104 svm->vmcb->control.nested_cr3 = __sme_set(root_hpa);
4105 vmcb_mark_dirty(svm->vmcb, VMCB_NPT);
4107 hv_track_root_tdp(vcpu, root_hpa);
4109 cr3 = vcpu->arch.cr3;
4110 } else if (root_level >= PT64_ROOT_4LEVEL) {
4111 cr3 = __sme_set(root_hpa) | kvm_get_active_pcid(vcpu);
4113 /* PCID in the guest should be impossible with a 32-bit MMU. */
4114 WARN_ON_ONCE(kvm_get_active_pcid(vcpu));
4118 svm->vmcb->save.cr3 = cr3;
4119 vmcb_mark_dirty(svm->vmcb, VMCB_CR);
4122 static int is_disabled(void)
4126 rdmsrl(MSR_VM_CR, vm_cr);
4127 if (vm_cr & (1 << SVM_VM_CR_SVM_DISABLE))
4134 svm_patch_hypercall(struct kvm_vcpu *vcpu, unsigned char *hypercall)
4137 * Patch in the VMMCALL instruction:
4139 hypercall[0] = 0x0f;
4140 hypercall[1] = 0x01;
4141 hypercall[2] = 0xd9;
4144 static int __init svm_check_processor_compat(void)
4150 * The kvm parameter can be NULL (module initialization, or invocation before
4151 * VM creation). Be sure to check the kvm parameter before using it.
4153 static bool svm_has_emulated_msr(struct kvm *kvm, u32 index)
4156 case MSR_IA32_MCG_EXT_CTL:
4157 case MSR_IA32_VMX_BASIC ... MSR_IA32_VMX_VMFUNC:
4159 case MSR_IA32_SMBASE:
4160 /* SEV-ES guests do not support SMM, so report false */
4161 if (kvm && sev_es_guest(kvm))
4171 static void svm_vcpu_after_set_cpuid(struct kvm_vcpu *vcpu)
4173 struct vcpu_svm *svm = to_svm(vcpu);
4174 struct kvm_cpuid_entry2 *best;
4176 vcpu->arch.xsaves_enabled = guest_cpuid_has(vcpu, X86_FEATURE_XSAVE) &&
4177 boot_cpu_has(X86_FEATURE_XSAVE) &&
4178 boot_cpu_has(X86_FEATURE_XSAVES);
4180 /* Update nrips enabled cache */
4181 svm->nrips_enabled = kvm_cpu_cap_has(X86_FEATURE_NRIPS) &&
4182 guest_cpuid_has(vcpu, X86_FEATURE_NRIPS);
4184 svm->tsc_scaling_enabled = tsc_scaling && guest_cpuid_has(vcpu, X86_FEATURE_TSCRATEMSR);
4185 svm->lbrv_enabled = lbrv && guest_cpuid_has(vcpu, X86_FEATURE_LBRV);
4187 svm->v_vmload_vmsave_enabled = vls && guest_cpuid_has(vcpu, X86_FEATURE_V_VMSAVE_VMLOAD);
4189 svm->pause_filter_enabled = kvm_cpu_cap_has(X86_FEATURE_PAUSEFILTER) &&
4190 guest_cpuid_has(vcpu, X86_FEATURE_PAUSEFILTER);
4192 svm->pause_threshold_enabled = kvm_cpu_cap_has(X86_FEATURE_PFTHRESHOLD) &&
4193 guest_cpuid_has(vcpu, X86_FEATURE_PFTHRESHOLD);
4195 svm->vgif_enabled = vgif && guest_cpuid_has(vcpu, X86_FEATURE_VGIF);
4197 svm_recalc_instruction_intercepts(vcpu, svm);
4199 /* For sev guests, the memory encryption bit is not reserved in CR3. */
4200 if (sev_guest(vcpu->kvm)) {
4201 best = kvm_find_cpuid_entry(vcpu, 0x8000001F);
4203 vcpu->arch.reserved_gpa_bits &= ~(1UL << (best->ebx & 0x3f));
4206 init_vmcb_after_set_cpuid(vcpu);
4209 static bool svm_has_wbinvd_exit(void)
4214 #define PRE_EX(exit) { .exit_code = (exit), \
4215 .stage = X86_ICPT_PRE_EXCEPT, }
4216 #define POST_EX(exit) { .exit_code = (exit), \
4217 .stage = X86_ICPT_POST_EXCEPT, }
4218 #define POST_MEM(exit) { .exit_code = (exit), \
4219 .stage = X86_ICPT_POST_MEMACCESS, }
4221 static const struct __x86_intercept {
4223 enum x86_intercept_stage stage;
4224 } x86_intercept_map[] = {
4225 [x86_intercept_cr_read] = POST_EX(SVM_EXIT_READ_CR0),
4226 [x86_intercept_cr_write] = POST_EX(SVM_EXIT_WRITE_CR0),
4227 [x86_intercept_clts] = POST_EX(SVM_EXIT_WRITE_CR0),
4228 [x86_intercept_lmsw] = POST_EX(SVM_EXIT_WRITE_CR0),
4229 [x86_intercept_smsw] = POST_EX(SVM_EXIT_READ_CR0),
4230 [x86_intercept_dr_read] = POST_EX(SVM_EXIT_READ_DR0),
4231 [x86_intercept_dr_write] = POST_EX(SVM_EXIT_WRITE_DR0),
4232 [x86_intercept_sldt] = POST_EX(SVM_EXIT_LDTR_READ),
4233 [x86_intercept_str] = POST_EX(SVM_EXIT_TR_READ),
4234 [x86_intercept_lldt] = POST_EX(SVM_EXIT_LDTR_WRITE),
4235 [x86_intercept_ltr] = POST_EX(SVM_EXIT_TR_WRITE),
4236 [x86_intercept_sgdt] = POST_EX(SVM_EXIT_GDTR_READ),
4237 [x86_intercept_sidt] = POST_EX(SVM_EXIT_IDTR_READ),
4238 [x86_intercept_lgdt] = POST_EX(SVM_EXIT_GDTR_WRITE),
4239 [x86_intercept_lidt] = POST_EX(SVM_EXIT_IDTR_WRITE),
4240 [x86_intercept_vmrun] = POST_EX(SVM_EXIT_VMRUN),
4241 [x86_intercept_vmmcall] = POST_EX(SVM_EXIT_VMMCALL),
4242 [x86_intercept_vmload] = POST_EX(SVM_EXIT_VMLOAD),
4243 [x86_intercept_vmsave] = POST_EX(SVM_EXIT_VMSAVE),
4244 [x86_intercept_stgi] = POST_EX(SVM_EXIT_STGI),
4245 [x86_intercept_clgi] = POST_EX(SVM_EXIT_CLGI),
4246 [x86_intercept_skinit] = POST_EX(SVM_EXIT_SKINIT),
4247 [x86_intercept_invlpga] = POST_EX(SVM_EXIT_INVLPGA),
4248 [x86_intercept_rdtscp] = POST_EX(SVM_EXIT_RDTSCP),
4249 [x86_intercept_monitor] = POST_MEM(SVM_EXIT_MONITOR),
4250 [x86_intercept_mwait] = POST_EX(SVM_EXIT_MWAIT),
4251 [x86_intercept_invlpg] = POST_EX(SVM_EXIT_INVLPG),
4252 [x86_intercept_invd] = POST_EX(SVM_EXIT_INVD),
4253 [x86_intercept_wbinvd] = POST_EX(SVM_EXIT_WBINVD),
4254 [x86_intercept_wrmsr] = POST_EX(SVM_EXIT_MSR),
4255 [x86_intercept_rdtsc] = POST_EX(SVM_EXIT_RDTSC),
4256 [x86_intercept_rdmsr] = POST_EX(SVM_EXIT_MSR),
4257 [x86_intercept_rdpmc] = POST_EX(SVM_EXIT_RDPMC),
4258 [x86_intercept_cpuid] = PRE_EX(SVM_EXIT_CPUID),
4259 [x86_intercept_rsm] = PRE_EX(SVM_EXIT_RSM),
4260 [x86_intercept_pause] = PRE_EX(SVM_EXIT_PAUSE),
4261 [x86_intercept_pushf] = PRE_EX(SVM_EXIT_PUSHF),
4262 [x86_intercept_popf] = PRE_EX(SVM_EXIT_POPF),
4263 [x86_intercept_intn] = PRE_EX(SVM_EXIT_SWINT),
4264 [x86_intercept_iret] = PRE_EX(SVM_EXIT_IRET),
4265 [x86_intercept_icebp] = PRE_EX(SVM_EXIT_ICEBP),
4266 [x86_intercept_hlt] = POST_EX(SVM_EXIT_HLT),
4267 [x86_intercept_in] = POST_EX(SVM_EXIT_IOIO),
4268 [x86_intercept_ins] = POST_EX(SVM_EXIT_IOIO),
4269 [x86_intercept_out] = POST_EX(SVM_EXIT_IOIO),
4270 [x86_intercept_outs] = POST_EX(SVM_EXIT_IOIO),
4271 [x86_intercept_xsetbv] = PRE_EX(SVM_EXIT_XSETBV),
4278 static int svm_check_intercept(struct kvm_vcpu *vcpu,
4279 struct x86_instruction_info *info,
4280 enum x86_intercept_stage stage,
4281 struct x86_exception *exception)
4283 struct vcpu_svm *svm = to_svm(vcpu);
4284 int vmexit, ret = X86EMUL_CONTINUE;
4285 struct __x86_intercept icpt_info;
4286 struct vmcb *vmcb = svm->vmcb;
4288 if (info->intercept >= ARRAY_SIZE(x86_intercept_map))
4291 icpt_info = x86_intercept_map[info->intercept];
4293 if (stage != icpt_info.stage)
4296 switch (icpt_info.exit_code) {
4297 case SVM_EXIT_READ_CR0:
4298 if (info->intercept == x86_intercept_cr_read)
4299 icpt_info.exit_code += info->modrm_reg;
4301 case SVM_EXIT_WRITE_CR0: {
4302 unsigned long cr0, val;
4304 if (info->intercept == x86_intercept_cr_write)
4305 icpt_info.exit_code += info->modrm_reg;
4307 if (icpt_info.exit_code != SVM_EXIT_WRITE_CR0 ||
4308 info->intercept == x86_intercept_clts)
4311 if (!(vmcb12_is_intercept(&svm->nested.ctl,
4312 INTERCEPT_SELECTIVE_CR0)))
4315 cr0 = vcpu->arch.cr0 & ~SVM_CR0_SELECTIVE_MASK;
4316 val = info->src_val & ~SVM_CR0_SELECTIVE_MASK;
4318 if (info->intercept == x86_intercept_lmsw) {
4321 /* lmsw can't clear PE - catch this here */
4322 if (cr0 & X86_CR0_PE)
4327 icpt_info.exit_code = SVM_EXIT_CR0_SEL_WRITE;
4331 case SVM_EXIT_READ_DR0:
4332 case SVM_EXIT_WRITE_DR0:
4333 icpt_info.exit_code += info->modrm_reg;
4336 if (info->intercept == x86_intercept_wrmsr)
4337 vmcb->control.exit_info_1 = 1;
4339 vmcb->control.exit_info_1 = 0;
4341 case SVM_EXIT_PAUSE:
4343 * We get this for NOP only, but pause
4344 * is rep not, check this here
4346 if (info->rep_prefix != REPE_PREFIX)
4349 case SVM_EXIT_IOIO: {
4353 if (info->intercept == x86_intercept_in ||
4354 info->intercept == x86_intercept_ins) {
4355 exit_info = ((info->src_val & 0xffff) << 16) |
4357 bytes = info->dst_bytes;
4359 exit_info = (info->dst_val & 0xffff) << 16;
4360 bytes = info->src_bytes;
4363 if (info->intercept == x86_intercept_outs ||
4364 info->intercept == x86_intercept_ins)
4365 exit_info |= SVM_IOIO_STR_MASK;
4367 if (info->rep_prefix)
4368 exit_info |= SVM_IOIO_REP_MASK;
4370 bytes = min(bytes, 4u);
4372 exit_info |= bytes << SVM_IOIO_SIZE_SHIFT;
4374 exit_info |= (u32)info->ad_bytes << (SVM_IOIO_ASIZE_SHIFT - 1);
4376 vmcb->control.exit_info_1 = exit_info;
4377 vmcb->control.exit_info_2 = info->next_rip;
4385 /* TODO: Advertise NRIPS to guest hypervisor unconditionally */
4386 if (static_cpu_has(X86_FEATURE_NRIPS))
4387 vmcb->control.next_rip = info->next_rip;
4388 vmcb->control.exit_code = icpt_info.exit_code;
4389 vmexit = nested_svm_exit_handled(svm);
4391 ret = (vmexit == NESTED_EXIT_DONE) ? X86EMUL_INTERCEPTED
4398 static void svm_handle_exit_irqoff(struct kvm_vcpu *vcpu)
4400 if (to_svm(vcpu)->vmcb->control.exit_code == SVM_EXIT_INTR)
4401 vcpu->arch.at_instruction_boundary = true;
4404 static void svm_sched_in(struct kvm_vcpu *vcpu, int cpu)
4406 if (!kvm_pause_in_guest(vcpu->kvm))
4407 shrink_ple_window(vcpu);
4410 static void svm_setup_mce(struct kvm_vcpu *vcpu)
4412 /* [63:9] are reserved. */
4413 vcpu->arch.mcg_cap &= 0x1ff;
4416 bool svm_smi_blocked(struct kvm_vcpu *vcpu)
4418 struct vcpu_svm *svm = to_svm(vcpu);
4420 /* Per APM Vol.2 15.22.2 "Response to SMI" */
4424 return is_smm(vcpu);
4427 static int svm_smi_allowed(struct kvm_vcpu *vcpu, bool for_injection)
4429 struct vcpu_svm *svm = to_svm(vcpu);
4430 if (svm->nested.nested_run_pending)
4433 if (svm_smi_blocked(vcpu))
4436 /* An SMI must not be injected into L2 if it's supposed to VM-Exit. */
4437 if (for_injection && is_guest_mode(vcpu) && nested_exit_on_smi(svm))
4443 static int svm_enter_smm(struct kvm_vcpu *vcpu, char *smstate)
4445 struct vcpu_svm *svm = to_svm(vcpu);
4446 struct kvm_host_map map_save;
4449 if (!is_guest_mode(vcpu))
4452 /* FED8h - SVM Guest */
4453 put_smstate(u64, smstate, 0x7ed8, 1);
4454 /* FEE0h - SVM Guest VMCB Physical Address */
4455 put_smstate(u64, smstate, 0x7ee0, svm->nested.vmcb12_gpa);
4457 svm->vmcb->save.rax = vcpu->arch.regs[VCPU_REGS_RAX];
4458 svm->vmcb->save.rsp = vcpu->arch.regs[VCPU_REGS_RSP];
4459 svm->vmcb->save.rip = vcpu->arch.regs[VCPU_REGS_RIP];
4461 ret = nested_svm_simple_vmexit(svm, SVM_EXIT_SW);
4466 * KVM uses VMCB01 to store L1 host state while L2 runs but
4467 * VMCB01 is going to be used during SMM and thus the state will
4468 * be lost. Temporary save non-VMLOAD/VMSAVE state to the host save
4469 * area pointed to by MSR_VM_HSAVE_PA. APM guarantees that the
4470 * format of the area is identical to guest save area offsetted
4471 * by 0x400 (matches the offset of 'struct vmcb_save_area'
4472 * within 'struct vmcb'). Note: HSAVE area may also be used by
4473 * L1 hypervisor to save additional host context (e.g. KVM does
4474 * that, see svm_prepare_switch_to_guest()) which must be
4477 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr),
4478 &map_save) == -EINVAL)
4481 BUILD_BUG_ON(offsetof(struct vmcb, save) != 0x400);
4483 svm_copy_vmrun_state(map_save.hva + 0x400,
4484 &svm->vmcb01.ptr->save);
4486 kvm_vcpu_unmap(vcpu, &map_save, true);
4490 static int svm_leave_smm(struct kvm_vcpu *vcpu, const char *smstate)
4492 struct vcpu_svm *svm = to_svm(vcpu);
4493 struct kvm_host_map map, map_save;
4494 u64 saved_efer, vmcb12_gpa;
4495 struct vmcb *vmcb12;
4498 if (!guest_cpuid_has(vcpu, X86_FEATURE_LM))
4501 /* Non-zero if SMI arrived while vCPU was in guest mode. */
4502 if (!GET_SMSTATE(u64, smstate, 0x7ed8))
4505 if (!guest_cpuid_has(vcpu, X86_FEATURE_SVM))
4508 saved_efer = GET_SMSTATE(u64, smstate, 0x7ed0);
4509 if (!(saved_efer & EFER_SVME))
4512 vmcb12_gpa = GET_SMSTATE(u64, smstate, 0x7ee0);
4513 if (kvm_vcpu_map(vcpu, gpa_to_gfn(vmcb12_gpa), &map) == -EINVAL)
4517 if (kvm_vcpu_map(vcpu, gpa_to_gfn(svm->nested.hsave_msr), &map_save) == -EINVAL)
4520 if (svm_allocate_nested(svm))
4524 * Restore L1 host state from L1 HSAVE area as VMCB01 was
4525 * used during SMM (see svm_enter_smm())
4528 svm_copy_vmrun_state(&svm->vmcb01.ptr->save, map_save.hva + 0x400);
4531 * Enter the nested guest now
4534 vmcb_mark_all_dirty(svm->vmcb01.ptr);
4537 nested_copy_vmcb_control_to_cache(svm, &vmcb12->control);
4538 nested_copy_vmcb_save_to_cache(svm, &vmcb12->save);
4539 ret = enter_svm_guest_mode(vcpu, vmcb12_gpa, vmcb12, false);
4544 svm->nested.nested_run_pending = 1;
4547 kvm_vcpu_unmap(vcpu, &map_save, true);
4549 kvm_vcpu_unmap(vcpu, &map, true);
4553 static void svm_enable_smi_window(struct kvm_vcpu *vcpu)
4555 struct vcpu_svm *svm = to_svm(vcpu);
4557 if (!gif_set(svm)) {
4559 svm_set_intercept(svm, INTERCEPT_STGI);
4560 /* STGI will cause a vm exit */
4562 /* We must be in SMM; RSM will cause a vmexit anyway. */
4566 static bool svm_can_emulate_instruction(struct kvm_vcpu *vcpu, int emul_type,
4567 void *insn, int insn_len)
4569 bool smep, smap, is_user;
4573 /* Emulation is always possible when KVM has access to all guest state. */
4574 if (!sev_guest(vcpu->kvm))
4577 /* #UD and #GP should never be intercepted for SEV guests. */
4578 WARN_ON_ONCE(emul_type & (EMULTYPE_TRAP_UD |
4579 EMULTYPE_TRAP_UD_FORCED |
4580 EMULTYPE_VMWARE_GP));
4583 * Emulation is impossible for SEV-ES guests as KVM doesn't have access
4584 * to guest register state.
4586 if (sev_es_guest(vcpu->kvm))
4590 * Emulation is possible if the instruction is already decoded, e.g.
4591 * when completing I/O after returning from userspace.
4593 if (emul_type & EMULTYPE_NO_DECODE)
4597 * Emulation is possible for SEV guests if and only if a prefilled
4598 * buffer containing the bytes of the intercepted instruction is
4599 * available. SEV guest memory is encrypted with a guest specific key
4600 * and cannot be decrypted by KVM, i.e. KVM would read cyphertext and
4603 * Inject #UD if KVM reached this point without an instruction buffer.
4604 * In practice, this path should never be hit by a well-behaved guest,
4605 * e.g. KVM doesn't intercept #UD or #GP for SEV guests, but this path
4606 * is still theoretically reachable, e.g. via unaccelerated fault-like
4607 * AVIC access, and needs to be handled by KVM to avoid putting the
4608 * guest into an infinite loop. Injecting #UD is somewhat arbitrary,
4609 * but its the least awful option given lack of insight into the guest.
4611 if (unlikely(!insn)) {
4612 kvm_queue_exception(vcpu, UD_VECTOR);
4617 * Emulate for SEV guests if the insn buffer is not empty. The buffer
4618 * will be empty if the DecodeAssist microcode cannot fetch bytes for
4619 * the faulting instruction because the code fetch itself faulted, e.g.
4620 * the guest attempted to fetch from emulated MMIO or a guest page
4621 * table used to translate CS:RIP resides in emulated MMIO.
4623 if (likely(insn_len))
4627 * Detect and workaround Errata 1096 Fam_17h_00_0Fh.
4630 * When CPU raises #NPF on guest data access and vCPU CR4.SMAP=1, it is
4631 * possible that CPU microcode implementing DecodeAssist will fail to
4632 * read guest memory at CS:RIP and vmcb.GuestIntrBytes will incorrectly
4633 * be '0'. This happens because microcode reads CS:RIP using a _data_
4634 * loap uop with CPL=0 privileges. If the load hits a SMAP #PF, ucode
4635 * gives up and does not fill the instruction bytes buffer.
4637 * As above, KVM reaches this point iff the VM is an SEV guest, the CPU
4638 * supports DecodeAssist, a #NPF was raised, KVM's page fault handler
4639 * triggered emulation (e.g. for MMIO), and the CPU returned 0 in the
4640 * GuestIntrBytes field of the VMCB.
4642 * This does _not_ mean that the erratum has been encountered, as the
4643 * DecodeAssist will also fail if the load for CS:RIP hits a legitimate
4644 * #PF, e.g. if the guest attempt to execute from emulated MMIO and
4645 * encountered a reserved/not-present #PF.
4647 * To hit the erratum, the following conditions must be true:
4648 * 1. CR4.SMAP=1 (obviously).
4649 * 2. CR4.SMEP=0 || CPL=3. If SMEP=1 and CPL<3, the erratum cannot
4650 * have been hit as the guest would have encountered a SMEP
4651 * violation #PF, not a #NPF.
4652 * 3. The #NPF is not due to a code fetch, in which case failure to
4653 * retrieve the instruction bytes is legitimate (see abvoe).
4655 * In addition, don't apply the erratum workaround if the #NPF occurred
4656 * while translating guest page tables (see below).
4658 error_code = to_svm(vcpu)->vmcb->control.exit_info_1;
4659 if (error_code & (PFERR_GUEST_PAGE_MASK | PFERR_FETCH_MASK))
4662 cr4 = kvm_read_cr4(vcpu);
4663 smep = cr4 & X86_CR4_SMEP;
4664 smap = cr4 & X86_CR4_SMAP;
4665 is_user = svm_get_cpl(vcpu) == 3;
4666 if (smap && (!smep || is_user)) {
4667 pr_err_ratelimited("KVM: SEV Guest triggered AMD Erratum 1096\n");
4670 * If the fault occurred in userspace, arbitrarily inject #GP
4671 * to avoid killing the guest and to hopefully avoid confusing
4672 * the guest kernel too much, e.g. injecting #PF would not be
4673 * coherent with respect to the guest's page tables. Request
4674 * triple fault if the fault occurred in the kernel as there's
4675 * no fault that KVM can inject without confusing the guest.
4676 * In practice, the triple fault is moot as no sane SEV kernel
4677 * will execute from user memory while also running with SMAP=1.
4680 kvm_inject_gp(vcpu, 0);
4682 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
4687 * If the erratum was not hit, simply resume the guest and let it fault
4688 * again. While awful, e.g. the vCPU may get stuck in an infinite loop
4689 * if the fault is at CPL=0, it's the lesser of all evils. Exiting to
4690 * userspace will kill the guest, and letting the emulator read garbage
4691 * will yield random behavior and potentially corrupt the guest.
4693 * Simply resuming the guest is technically not a violation of the SEV
4694 * architecture. AMD's APM states that all code fetches and page table
4695 * accesses for SEV guest are encrypted, regardless of the C-Bit. The
4696 * APM also states that encrypted accesses to MMIO are "ignored", but
4697 * doesn't explicitly define "ignored", i.e. doing nothing and letting
4698 * the guest spin is technically "ignoring" the access.
4703 static bool svm_apic_init_signal_blocked(struct kvm_vcpu *vcpu)
4705 struct vcpu_svm *svm = to_svm(vcpu);
4708 * TODO: Last condition latch INIT signals on vCPU when
4709 * vCPU is in guest-mode and vmcb12 defines intercept on INIT.
4710 * To properly emulate the INIT intercept,
4711 * svm_check_nested_events() should call nested_svm_vmexit()
4712 * if an INIT signal is pending.
4714 return !gif_set(svm) ||
4715 (vmcb_is_intercept(&svm->vmcb->control, INTERCEPT_INIT));
4718 static void svm_vcpu_deliver_sipi_vector(struct kvm_vcpu *vcpu, u8 vector)
4720 if (!sev_es_guest(vcpu->kvm))
4721 return kvm_vcpu_deliver_sipi_vector(vcpu, vector);
4723 sev_vcpu_deliver_sipi_vector(vcpu, vector);
4726 static void svm_vm_destroy(struct kvm *kvm)
4728 avic_vm_destroy(kvm);
4729 sev_vm_destroy(kvm);
4732 static int svm_vm_init(struct kvm *kvm)
4734 if (!pause_filter_count || !pause_filter_thresh)
4735 kvm->arch.pause_in_guest = true;
4738 int ret = avic_vm_init(kvm);
4746 static struct kvm_x86_ops svm_x86_ops __initdata = {
4749 .hardware_unsetup = svm_hardware_unsetup,
4750 .hardware_enable = svm_hardware_enable,
4751 .hardware_disable = svm_hardware_disable,
4752 .has_emulated_msr = svm_has_emulated_msr,
4754 .vcpu_create = svm_vcpu_create,
4755 .vcpu_free = svm_vcpu_free,
4756 .vcpu_reset = svm_vcpu_reset,
4758 .vm_size = sizeof(struct kvm_svm),
4759 .vm_init = svm_vm_init,
4760 .vm_destroy = svm_vm_destroy,
4762 .prepare_switch_to_guest = svm_prepare_switch_to_guest,
4763 .vcpu_load = svm_vcpu_load,
4764 .vcpu_put = svm_vcpu_put,
4765 .vcpu_blocking = avic_vcpu_blocking,
4766 .vcpu_unblocking = avic_vcpu_unblocking,
4768 .update_exception_bitmap = svm_update_exception_bitmap,
4769 .get_msr_feature = svm_get_msr_feature,
4770 .get_msr = svm_get_msr,
4771 .set_msr = svm_set_msr,
4772 .get_segment_base = svm_get_segment_base,
4773 .get_segment = svm_get_segment,
4774 .set_segment = svm_set_segment,
4775 .get_cpl = svm_get_cpl,
4776 .get_cs_db_l_bits = svm_get_cs_db_l_bits,
4777 .set_cr0 = svm_set_cr0,
4778 .post_set_cr3 = sev_post_set_cr3,
4779 .is_valid_cr4 = svm_is_valid_cr4,
4780 .set_cr4 = svm_set_cr4,
4781 .set_efer = svm_set_efer,
4782 .get_idt = svm_get_idt,
4783 .set_idt = svm_set_idt,
4784 .get_gdt = svm_get_gdt,
4785 .set_gdt = svm_set_gdt,
4786 .set_dr7 = svm_set_dr7,
4787 .sync_dirty_debug_regs = svm_sync_dirty_debug_regs,
4788 .cache_reg = svm_cache_reg,
4789 .get_rflags = svm_get_rflags,
4790 .set_rflags = svm_set_rflags,
4791 .get_if_flag = svm_get_if_flag,
4793 .flush_tlb_all = svm_flush_tlb_current,
4794 .flush_tlb_current = svm_flush_tlb_current,
4795 .flush_tlb_gva = svm_flush_tlb_gva,
4796 .flush_tlb_guest = svm_flush_tlb_current,
4798 .vcpu_pre_run = svm_vcpu_pre_run,
4799 .vcpu_run = svm_vcpu_run,
4800 .handle_exit = svm_handle_exit,
4801 .skip_emulated_instruction = svm_skip_emulated_instruction,
4802 .update_emulated_instruction = NULL,
4803 .set_interrupt_shadow = svm_set_interrupt_shadow,
4804 .get_interrupt_shadow = svm_get_interrupt_shadow,
4805 .patch_hypercall = svm_patch_hypercall,
4806 .inject_irq = svm_inject_irq,
4807 .inject_nmi = svm_inject_nmi,
4808 .queue_exception = svm_queue_exception,
4809 .cancel_injection = svm_cancel_injection,
4810 .interrupt_allowed = svm_interrupt_allowed,
4811 .nmi_allowed = svm_nmi_allowed,
4812 .get_nmi_mask = svm_get_nmi_mask,
4813 .set_nmi_mask = svm_set_nmi_mask,
4814 .enable_nmi_window = svm_enable_nmi_window,
4815 .enable_irq_window = svm_enable_irq_window,
4816 .update_cr8_intercept = svm_update_cr8_intercept,
4817 .set_virtual_apic_mode = avic_set_virtual_apic_mode,
4818 .refresh_apicv_exec_ctrl = avic_refresh_apicv_exec_ctrl,
4819 .check_apicv_inhibit_reasons = avic_check_apicv_inhibit_reasons,
4820 .apicv_post_state_restore = avic_apicv_post_state_restore,
4822 .get_exit_info = svm_get_exit_info,
4824 .vcpu_after_set_cpuid = svm_vcpu_after_set_cpuid,
4826 .has_wbinvd_exit = svm_has_wbinvd_exit,
4828 .get_l2_tsc_offset = svm_get_l2_tsc_offset,
4829 .get_l2_tsc_multiplier = svm_get_l2_tsc_multiplier,
4830 .write_tsc_offset = svm_write_tsc_offset,
4831 .write_tsc_multiplier = svm_write_tsc_multiplier,
4833 .load_mmu_pgd = svm_load_mmu_pgd,
4835 .check_intercept = svm_check_intercept,
4836 .handle_exit_irqoff = svm_handle_exit_irqoff,
4838 .request_immediate_exit = __kvm_request_immediate_exit,
4840 .sched_in = svm_sched_in,
4842 .nested_ops = &svm_nested_ops,
4844 .deliver_interrupt = svm_deliver_interrupt,
4845 .pi_update_irte = avic_pi_update_irte,
4846 .setup_mce = svm_setup_mce,
4848 .smi_allowed = svm_smi_allowed,
4849 .enter_smm = svm_enter_smm,
4850 .leave_smm = svm_leave_smm,
4851 .enable_smi_window = svm_enable_smi_window,
4853 .mem_enc_ioctl = sev_mem_enc_ioctl,
4854 .mem_enc_register_region = sev_mem_enc_register_region,
4855 .mem_enc_unregister_region = sev_mem_enc_unregister_region,
4856 .guest_memory_reclaimed = sev_guest_memory_reclaimed,
4858 .vm_copy_enc_context_from = sev_vm_copy_enc_context_from,
4859 .vm_move_enc_context_from = sev_vm_move_enc_context_from,
4861 .can_emulate_instruction = svm_can_emulate_instruction,
4863 .apic_init_signal_blocked = svm_apic_init_signal_blocked,
4865 .msr_filter_changed = svm_msr_filter_changed,
4866 .complete_emulated_msr = svm_complete_emulated_msr,
4868 .vcpu_deliver_sipi_vector = svm_vcpu_deliver_sipi_vector,
4869 .vcpu_get_apicv_inhibit_reasons = avic_vcpu_get_apicv_inhibit_reasons,
4873 * The default MMIO mask is a single bit (excluding the present bit),
4874 * which could conflict with the memory encryption bit. Check for
4875 * memory encryption support and override the default MMIO mask if
4876 * memory encryption is enabled.
4878 static __init void svm_adjust_mmio_mask(void)
4880 unsigned int enc_bit, mask_bit;
4883 /* If there is no memory encryption support, use existing mask */
4884 if (cpuid_eax(0x80000000) < 0x8000001f)
4887 /* If memory encryption is not enabled, use existing mask */
4888 rdmsrl(MSR_AMD64_SYSCFG, msr);
4889 if (!(msr & MSR_AMD64_SYSCFG_MEM_ENCRYPT))
4892 enc_bit = cpuid_ebx(0x8000001f) & 0x3f;
4893 mask_bit = boot_cpu_data.x86_phys_bits;
4895 /* Increment the mask bit if it is the same as the encryption bit */
4896 if (enc_bit == mask_bit)
4900 * If the mask bit location is below 52, then some bits above the
4901 * physical addressing limit will always be reserved, so use the
4902 * rsvd_bits() function to generate the mask. This mask, along with
4903 * the present bit, will be used to generate a page fault with
4906 * If the mask bit location is 52 (or above), then clear the mask.
4908 mask = (mask_bit < 52) ? rsvd_bits(mask_bit, 51) | PT_PRESENT_MASK : 0;
4910 kvm_mmu_set_mmio_spte_mask(mask, mask, PT_WRITABLE_MASK | PT_USER_MASK);
4913 static __init void svm_set_cpu_caps(void)
4917 kvm_caps.supported_xss = 0;
4919 /* CPUID 0x80000001 and 0x8000000A (SVM features) */
4921 kvm_cpu_cap_set(X86_FEATURE_SVM);
4922 kvm_cpu_cap_set(X86_FEATURE_VMCBCLEAN);
4925 kvm_cpu_cap_set(X86_FEATURE_NRIPS);
4928 kvm_cpu_cap_set(X86_FEATURE_NPT);
4931 kvm_cpu_cap_set(X86_FEATURE_TSCRATEMSR);
4934 kvm_cpu_cap_set(X86_FEATURE_V_VMSAVE_VMLOAD);
4936 kvm_cpu_cap_set(X86_FEATURE_LBRV);
4938 if (boot_cpu_has(X86_FEATURE_PAUSEFILTER))
4939 kvm_cpu_cap_set(X86_FEATURE_PAUSEFILTER);
4941 if (boot_cpu_has(X86_FEATURE_PFTHRESHOLD))
4942 kvm_cpu_cap_set(X86_FEATURE_PFTHRESHOLD);
4945 kvm_cpu_cap_set(X86_FEATURE_VGIF);
4947 /* Nested VM can receive #VMEXIT instead of triggering #GP */
4948 kvm_cpu_cap_set(X86_FEATURE_SVME_ADDR_CHK);
4951 /* CPUID 0x80000008 */
4952 if (boot_cpu_has(X86_FEATURE_LS_CFG_SSBD) ||
4953 boot_cpu_has(X86_FEATURE_AMD_SSBD))
4954 kvm_cpu_cap_set(X86_FEATURE_VIRT_SSBD);
4956 /* AMD PMU PERFCTR_CORE CPUID */
4957 if (enable_pmu && boot_cpu_has(X86_FEATURE_PERFCTR_CORE))
4958 kvm_cpu_cap_set(X86_FEATURE_PERFCTR_CORE);
4960 /* CPUID 0x8000001F (SME/SEV features) */
4964 static __init int svm_hardware_setup(void)
4967 struct page *iopm_pages;
4970 unsigned int order = get_order(IOPM_SIZE);
4973 * NX is required for shadow paging and for NPT if the NX huge pages
4974 * mitigation is enabled.
4976 if (!boot_cpu_has(X86_FEATURE_NX)) {
4977 pr_err_ratelimited("NX (Execute Disable) not supported\n");
4980 kvm_enable_efer_bits(EFER_NX);
4982 iopm_pages = alloc_pages(GFP_KERNEL, order);
4987 iopm_va = page_address(iopm_pages);
4988 memset(iopm_va, 0xff, PAGE_SIZE * (1 << order));
4989 iopm_base = page_to_pfn(iopm_pages) << PAGE_SHIFT;
4991 init_msrpm_offsets();
4993 kvm_caps.supported_xcr0 &= ~(XFEATURE_MASK_BNDREGS |
4994 XFEATURE_MASK_BNDCSR);
4996 if (boot_cpu_has(X86_FEATURE_FXSR_OPT))
4997 kvm_enable_efer_bits(EFER_FFXSR);
5000 if (!boot_cpu_has(X86_FEATURE_TSCRATEMSR)) {
5001 tsc_scaling = false;
5003 pr_info("TSC scaling supported\n");
5004 kvm_caps.has_tsc_control = true;
5007 kvm_caps.max_tsc_scaling_ratio = SVM_TSC_RATIO_MAX;
5008 kvm_caps.tsc_scaling_ratio_frac_bits = 32;
5010 tsc_aux_uret_slot = kvm_add_user_return_msr(MSR_TSC_AUX);
5012 /* Check for pause filtering support */
5013 if (!boot_cpu_has(X86_FEATURE_PAUSEFILTER)) {
5014 pause_filter_count = 0;
5015 pause_filter_thresh = 0;
5016 } else if (!boot_cpu_has(X86_FEATURE_PFTHRESHOLD)) {
5017 pause_filter_thresh = 0;
5021 printk(KERN_INFO "kvm: Nested Virtualization enabled\n");
5022 kvm_enable_efer_bits(EFER_SVME | EFER_LMSLE);
5026 * KVM's MMU doesn't support using 2-level paging for itself, and thus
5027 * NPT isn't supported if the host is using 2-level paging since host
5028 * CR4 is unchanged on VMRUN.
5030 if (!IS_ENABLED(CONFIG_X86_64) && !IS_ENABLED(CONFIG_X86_PAE))
5031 npt_enabled = false;
5033 if (!boot_cpu_has(X86_FEATURE_NPT))
5034 npt_enabled = false;
5036 /* Force VM NPT level equal to the host's paging level */
5037 kvm_configure_mmu(npt_enabled, get_npt_level(),
5038 get_npt_level(), PG_LEVEL_1G);
5039 pr_info("kvm: Nested Paging %sabled\n", npt_enabled ? "en" : "dis");
5041 /* Setup shadow_me_value and shadow_me_mask */
5042 kvm_mmu_set_me_spte_mask(sme_me_mask, sme_me_mask);
5044 /* Note, SEV setup consumes npt_enabled. */
5045 sev_hardware_setup();
5047 svm_hv_hardware_setup();
5049 svm_adjust_mmio_mask();
5051 for_each_possible_cpu(cpu) {
5052 r = svm_cpu_init(cpu);
5058 if (!boot_cpu_has(X86_FEATURE_NRIPS))
5062 enable_apicv = avic = avic && avic_hardware_setup(&svm_x86_ops);
5064 if (!enable_apicv) {
5065 svm_x86_ops.vcpu_blocking = NULL;
5066 svm_x86_ops.vcpu_unblocking = NULL;
5067 svm_x86_ops.vcpu_get_apicv_inhibit_reasons = NULL;
5072 !boot_cpu_has(X86_FEATURE_V_VMSAVE_VMLOAD) ||
5073 !IS_ENABLED(CONFIG_X86_64)) {
5076 pr_info("Virtual VMLOAD VMSAVE supported\n");
5080 if (boot_cpu_has(X86_FEATURE_SVME_ADDR_CHK))
5081 svm_gp_erratum_intercept = false;
5084 if (!boot_cpu_has(X86_FEATURE_VGIF))
5087 pr_info("Virtual GIF supported\n");
5091 if (!boot_cpu_has(X86_FEATURE_LBRV))
5094 pr_info("LBR virtualization supported\n");
5098 pr_info("PMU virtualization is disabled\n");
5103 * It seems that on AMD processors PTE's accessed bit is
5104 * being set by the CPU hardware before the NPF vmexit.
5105 * This is not expected behaviour and our tests fail because
5107 * A workaround here is to disable support for
5108 * GUEST_MAXPHYADDR < HOST_MAXPHYADDR if NPT is enabled.
5109 * In this case userspace can know if there is support using
5110 * KVM_CAP_SMALLER_MAXPHYADDR extension and decide how to handle
5112 * If future AMD CPU models change the behaviour described above,
5113 * this variable can be changed accordingly
5115 allow_smaller_maxphyaddr = !npt_enabled;
5120 svm_hardware_unsetup();
5125 static struct kvm_x86_init_ops svm_init_ops __initdata = {
5126 .cpu_has_kvm_support = has_svm,
5127 .disabled_by_bios = is_disabled,
5128 .hardware_setup = svm_hardware_setup,
5129 .check_processor_compatibility = svm_check_processor_compat,
5131 .runtime_ops = &svm_x86_ops,
5132 .pmu_ops = &amd_pmu_ops,
5135 static int __init svm_init(void)
5137 __unused_size_checks();
5139 return kvm_init(&svm_init_ops, sizeof(struct vcpu_svm),
5140 __alignof__(struct vcpu_svm), THIS_MODULE);
5143 static void __exit svm_exit(void)
5148 module_init(svm_init)
5149 module_exit(svm_exit)