1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
5 * This module enables machines with Intel VT-x extensions to run virtual
6 * machines without emulation or binary translation.
10 * Copyright (C) 2006 Qumranet, Inc.
11 * Copyright 2010 Red Hat, Inc. and/or its affiliates.
14 * Yaniv Kamay <yaniv@qumranet.com>
15 * Avi Kivity <avi@qumranet.com>
21 #include "mmu_internal.h"
24 #include "kvm_cache_regs.h"
25 #include "kvm_emulate.h"
29 #include <linux/kvm_host.h>
30 #include <linux/types.h>
31 #include <linux/string.h>
33 #include <linux/highmem.h>
34 #include <linux/moduleparam.h>
35 #include <linux/export.h>
36 #include <linux/swap.h>
37 #include <linux/hugetlb.h>
38 #include <linux/compiler.h>
39 #include <linux/srcu.h>
40 #include <linux/slab.h>
41 #include <linux/sched/signal.h>
42 #include <linux/uaccess.h>
43 #include <linux/hash.h>
44 #include <linux/kern_levels.h>
45 #include <linux/kthread.h>
48 #include <asm/memtype.h>
49 #include <asm/cmpxchg.h>
51 #include <asm/set_memory.h>
53 #include <asm/kvm_page_track.h>
56 extern bool itlb_multihit_kvm_mitigation;
58 int __read_mostly nx_huge_pages = -1;
59 #ifdef CONFIG_PREEMPT_RT
60 /* Recovery can cause latency spikes, disable it for PREEMPT_RT. */
61 static uint __read_mostly nx_huge_pages_recovery_ratio = 0;
63 static uint __read_mostly nx_huge_pages_recovery_ratio = 60;
66 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp);
67 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp);
69 static const struct kernel_param_ops nx_huge_pages_ops = {
70 .set = set_nx_huge_pages,
71 .get = param_get_bool,
74 static const struct kernel_param_ops nx_huge_pages_recovery_ratio_ops = {
75 .set = set_nx_huge_pages_recovery_ratio,
76 .get = param_get_uint,
79 module_param_cb(nx_huge_pages, &nx_huge_pages_ops, &nx_huge_pages, 0644);
80 __MODULE_PARM_TYPE(nx_huge_pages, "bool");
81 module_param_cb(nx_huge_pages_recovery_ratio, &nx_huge_pages_recovery_ratio_ops,
82 &nx_huge_pages_recovery_ratio, 0644);
83 __MODULE_PARM_TYPE(nx_huge_pages_recovery_ratio, "uint");
85 static bool __read_mostly force_flush_and_sync_on_reuse;
86 module_param_named(flush_on_reuse, force_flush_and_sync_on_reuse, bool, 0644);
89 * When setting this variable to true it enables Two-Dimensional-Paging
90 * where the hardware walks 2 page tables:
91 * 1. the guest-virtual to guest-physical
92 * 2. while doing 1. it walks guest-physical to host-physical
93 * If the hardware supports that we don't need to do shadow paging.
95 bool tdp_enabled = false;
97 static int max_huge_page_level __read_mostly;
98 static int max_tdp_level __read_mostly;
101 AUDIT_PRE_PAGE_FAULT,
102 AUDIT_POST_PAGE_FAULT,
104 AUDIT_POST_PTE_WRITE,
111 module_param(dbg, bool, 0644);
114 #define PTE_PREFETCH_NUM 8
116 #define PT32_LEVEL_BITS 10
118 #define PT32_LEVEL_SHIFT(level) \
119 (PAGE_SHIFT + (level - 1) * PT32_LEVEL_BITS)
121 #define PT32_LVL_OFFSET_MASK(level) \
122 (PT32_BASE_ADDR_MASK & ((1ULL << (PAGE_SHIFT + (((level) - 1) \
123 * PT32_LEVEL_BITS))) - 1))
125 #define PT32_INDEX(address, level)\
126 (((address) >> PT32_LEVEL_SHIFT(level)) & ((1 << PT32_LEVEL_BITS) - 1))
129 #define PT32_BASE_ADDR_MASK PAGE_MASK
130 #define PT32_DIR_BASE_ADDR_MASK \
131 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + PT32_LEVEL_BITS)) - 1))
132 #define PT32_LVL_ADDR_MASK(level) \
133 (PAGE_MASK & ~((1ULL << (PAGE_SHIFT + (((level) - 1) \
134 * PT32_LEVEL_BITS))) - 1))
136 #include <trace/events/kvm.h>
138 /* make pte_list_desc fit well in cache line */
139 #define PTE_LIST_EXT 3
141 struct pte_list_desc {
142 u64 *sptes[PTE_LIST_EXT];
143 struct pte_list_desc *more;
146 struct kvm_shadow_walk_iterator {
154 #define for_each_shadow_entry_using_root(_vcpu, _root, _addr, _walker) \
155 for (shadow_walk_init_using_root(&(_walker), (_vcpu), \
157 shadow_walk_okay(&(_walker)); \
158 shadow_walk_next(&(_walker)))
160 #define for_each_shadow_entry(_vcpu, _addr, _walker) \
161 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
162 shadow_walk_okay(&(_walker)); \
163 shadow_walk_next(&(_walker)))
165 #define for_each_shadow_entry_lockless(_vcpu, _addr, _walker, spte) \
166 for (shadow_walk_init(&(_walker), _vcpu, _addr); \
167 shadow_walk_okay(&(_walker)) && \
168 ({ spte = mmu_spte_get_lockless(_walker.sptep); 1; }); \
169 __shadow_walk_next(&(_walker), spte))
171 static struct kmem_cache *pte_list_desc_cache;
172 struct kmem_cache *mmu_page_header_cache;
173 static struct percpu_counter kvm_total_used_mmu_pages;
175 static void mmu_spte_set(u64 *sptep, u64 spte);
176 static union kvm_mmu_page_role
177 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu);
179 struct kvm_mmu_role_regs {
180 const unsigned long cr0;
181 const unsigned long cr4;
185 #define CREATE_TRACE_POINTS
186 #include "mmutrace.h"
189 * Yes, lot's of underscores. They're a hint that you probably shouldn't be
190 * reading from the role_regs. Once the mmu_role is constructed, it becomes
191 * the single source of truth for the MMU's state.
193 #define BUILD_MMU_ROLE_REGS_ACCESSOR(reg, name, flag) \
194 static inline bool ____is_##reg##_##name(struct kvm_mmu_role_regs *regs)\
196 return !!(regs->reg & flag); \
198 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, pg, X86_CR0_PG);
199 BUILD_MMU_ROLE_REGS_ACCESSOR(cr0, wp, X86_CR0_WP);
200 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pse, X86_CR4_PSE);
201 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pae, X86_CR4_PAE);
202 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smep, X86_CR4_SMEP);
203 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, smap, X86_CR4_SMAP);
204 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, pke, X86_CR4_PKE);
205 BUILD_MMU_ROLE_REGS_ACCESSOR(cr4, la57, X86_CR4_LA57);
206 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, nx, EFER_NX);
207 BUILD_MMU_ROLE_REGS_ACCESSOR(efer, lma, EFER_LMA);
209 static struct kvm_mmu_role_regs vcpu_to_role_regs(struct kvm_vcpu *vcpu)
211 struct kvm_mmu_role_regs regs = {
212 .cr0 = kvm_read_cr0_bits(vcpu, KVM_MMU_CR0_ROLE_BITS),
213 .cr4 = kvm_read_cr4_bits(vcpu, KVM_MMU_CR4_ROLE_BITS),
214 .efer = vcpu->arch.efer,
220 static inline bool kvm_available_flush_tlb_with_range(void)
222 return kvm_x86_ops.tlb_remote_flush_with_range;
225 static void kvm_flush_remote_tlbs_with_range(struct kvm *kvm,
226 struct kvm_tlb_range *range)
230 if (range && kvm_x86_ops.tlb_remote_flush_with_range)
231 ret = static_call(kvm_x86_tlb_remote_flush_with_range)(kvm, range);
234 kvm_flush_remote_tlbs(kvm);
237 void kvm_flush_remote_tlbs_with_address(struct kvm *kvm,
238 u64 start_gfn, u64 pages)
240 struct kvm_tlb_range range;
242 range.start_gfn = start_gfn;
245 kvm_flush_remote_tlbs_with_range(kvm, &range);
248 static void mark_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, u64 gfn,
251 u64 spte = make_mmio_spte(vcpu, gfn, access);
253 trace_mark_mmio_spte(sptep, gfn, spte);
254 mmu_spte_set(sptep, spte);
257 static gfn_t get_mmio_spte_gfn(u64 spte)
259 u64 gpa = spte & shadow_nonpresent_or_rsvd_lower_gfn_mask;
261 gpa |= (spte >> SHADOW_NONPRESENT_OR_RSVD_MASK_LEN)
262 & shadow_nonpresent_or_rsvd_mask;
264 return gpa >> PAGE_SHIFT;
267 static unsigned get_mmio_spte_access(u64 spte)
269 return spte & shadow_mmio_access_mask;
272 static bool check_mmio_spte(struct kvm_vcpu *vcpu, u64 spte)
274 u64 kvm_gen, spte_gen, gen;
276 gen = kvm_vcpu_memslots(vcpu)->generation;
277 if (unlikely(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS))
280 kvm_gen = gen & MMIO_SPTE_GEN_MASK;
281 spte_gen = get_mmio_spte_generation(spte);
283 trace_check_mmio_spte(spte, kvm_gen, spte_gen);
284 return likely(kvm_gen == spte_gen);
287 static gpa_t translate_gpa(struct kvm_vcpu *vcpu, gpa_t gpa, u32 access,
288 struct x86_exception *exception)
290 /* Check if guest physical address doesn't exceed guest maximum */
291 if (kvm_vcpu_is_illegal_gpa(vcpu, gpa)) {
292 exception->error_code |= PFERR_RSVD_MASK;
299 static int is_cpuid_PSE36(void)
304 static int is_nx(struct kvm_vcpu *vcpu)
306 return vcpu->arch.efer & EFER_NX;
309 static gfn_t pse36_gfn_delta(u32 gpte)
311 int shift = 32 - PT32_DIR_PSE36_SHIFT - PAGE_SHIFT;
313 return (gpte & PT32_DIR_PSE36_MASK) << shift;
317 static void __set_spte(u64 *sptep, u64 spte)
319 WRITE_ONCE(*sptep, spte);
322 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
324 WRITE_ONCE(*sptep, spte);
327 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
329 return xchg(sptep, spte);
332 static u64 __get_spte_lockless(u64 *sptep)
334 return READ_ONCE(*sptep);
345 static void count_spte_clear(u64 *sptep, u64 spte)
347 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
349 if (is_shadow_present_pte(spte))
352 /* Ensure the spte is completely set before we increase the count */
354 sp->clear_spte_count++;
357 static void __set_spte(u64 *sptep, u64 spte)
359 union split_spte *ssptep, sspte;
361 ssptep = (union split_spte *)sptep;
362 sspte = (union split_spte)spte;
364 ssptep->spte_high = sspte.spte_high;
367 * If we map the spte from nonpresent to present, We should store
368 * the high bits firstly, then set present bit, so cpu can not
369 * fetch this spte while we are setting the spte.
373 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
376 static void __update_clear_spte_fast(u64 *sptep, u64 spte)
378 union split_spte *ssptep, sspte;
380 ssptep = (union split_spte *)sptep;
381 sspte = (union split_spte)spte;
383 WRITE_ONCE(ssptep->spte_low, sspte.spte_low);
386 * If we map the spte from present to nonpresent, we should clear
387 * present bit firstly to avoid vcpu fetch the old high bits.
391 ssptep->spte_high = sspte.spte_high;
392 count_spte_clear(sptep, spte);
395 static u64 __update_clear_spte_slow(u64 *sptep, u64 spte)
397 union split_spte *ssptep, sspte, orig;
399 ssptep = (union split_spte *)sptep;
400 sspte = (union split_spte)spte;
402 /* xchg acts as a barrier before the setting of the high bits */
403 orig.spte_low = xchg(&ssptep->spte_low, sspte.spte_low);
404 orig.spte_high = ssptep->spte_high;
405 ssptep->spte_high = sspte.spte_high;
406 count_spte_clear(sptep, spte);
412 * The idea using the light way get the spte on x86_32 guest is from
413 * gup_get_pte (mm/gup.c).
415 * An spte tlb flush may be pending, because kvm_set_pte_rmapp
416 * coalesces them and we are running out of the MMU lock. Therefore
417 * we need to protect against in-progress updates of the spte.
419 * Reading the spte while an update is in progress may get the old value
420 * for the high part of the spte. The race is fine for a present->non-present
421 * change (because the high part of the spte is ignored for non-present spte),
422 * but for a present->present change we must reread the spte.
424 * All such changes are done in two steps (present->non-present and
425 * non-present->present), hence it is enough to count the number of
426 * present->non-present updates: if it changed while reading the spte,
427 * we might have hit the race. This is done using clear_spte_count.
429 static u64 __get_spte_lockless(u64 *sptep)
431 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
432 union split_spte spte, *orig = (union split_spte *)sptep;
436 count = sp->clear_spte_count;
439 spte.spte_low = orig->spte_low;
442 spte.spte_high = orig->spte_high;
445 if (unlikely(spte.spte_low != orig->spte_low ||
446 count != sp->clear_spte_count))
453 static bool spte_has_volatile_bits(u64 spte)
455 if (!is_shadow_present_pte(spte))
459 * Always atomically update spte if it can be updated
460 * out of mmu-lock, it can ensure dirty bit is not lost,
461 * also, it can help us to get a stable is_writable_pte()
462 * to ensure tlb flush is not missed.
464 if (spte_can_locklessly_be_made_writable(spte) ||
465 is_access_track_spte(spte))
468 if (spte_ad_enabled(spte)) {
469 if ((spte & shadow_accessed_mask) == 0 ||
470 (is_writable_pte(spte) && (spte & shadow_dirty_mask) == 0))
477 /* Rules for using mmu_spte_set:
478 * Set the sptep from nonpresent to present.
479 * Note: the sptep being assigned *must* be either not present
480 * or in a state where the hardware will not attempt to update
483 static void mmu_spte_set(u64 *sptep, u64 new_spte)
485 WARN_ON(is_shadow_present_pte(*sptep));
486 __set_spte(sptep, new_spte);
490 * Update the SPTE (excluding the PFN), but do not track changes in its
491 * accessed/dirty status.
493 static u64 mmu_spte_update_no_track(u64 *sptep, u64 new_spte)
495 u64 old_spte = *sptep;
497 WARN_ON(!is_shadow_present_pte(new_spte));
499 if (!is_shadow_present_pte(old_spte)) {
500 mmu_spte_set(sptep, new_spte);
504 if (!spte_has_volatile_bits(old_spte))
505 __update_clear_spte_fast(sptep, new_spte);
507 old_spte = __update_clear_spte_slow(sptep, new_spte);
509 WARN_ON(spte_to_pfn(old_spte) != spte_to_pfn(new_spte));
514 /* Rules for using mmu_spte_update:
515 * Update the state bits, it means the mapped pfn is not changed.
517 * Whenever we overwrite a writable spte with a read-only one we
518 * should flush remote TLBs. Otherwise rmap_write_protect
519 * will find a read-only spte, even though the writable spte
520 * might be cached on a CPU's TLB, the return value indicates this
523 * Returns true if the TLB needs to be flushed
525 static bool mmu_spte_update(u64 *sptep, u64 new_spte)
528 u64 old_spte = mmu_spte_update_no_track(sptep, new_spte);
530 if (!is_shadow_present_pte(old_spte))
534 * For the spte updated out of mmu-lock is safe, since
535 * we always atomically update it, see the comments in
536 * spte_has_volatile_bits().
538 if (spte_can_locklessly_be_made_writable(old_spte) &&
539 !is_writable_pte(new_spte))
543 * Flush TLB when accessed/dirty states are changed in the page tables,
544 * to guarantee consistency between TLB and page tables.
547 if (is_accessed_spte(old_spte) && !is_accessed_spte(new_spte)) {
549 kvm_set_pfn_accessed(spte_to_pfn(old_spte));
552 if (is_dirty_spte(old_spte) && !is_dirty_spte(new_spte)) {
554 kvm_set_pfn_dirty(spte_to_pfn(old_spte));
561 * Rules for using mmu_spte_clear_track_bits:
562 * It sets the sptep from present to nonpresent, and track the
563 * state bits, it is used to clear the last level sptep.
564 * Returns non-zero if the PTE was previously valid.
566 static int mmu_spte_clear_track_bits(u64 *sptep)
569 u64 old_spte = *sptep;
571 if (!spte_has_volatile_bits(old_spte))
572 __update_clear_spte_fast(sptep, 0ull);
574 old_spte = __update_clear_spte_slow(sptep, 0ull);
576 if (!is_shadow_present_pte(old_spte))
579 pfn = spte_to_pfn(old_spte);
582 * KVM does not hold the refcount of the page used by
583 * kvm mmu, before reclaiming the page, we should
584 * unmap it from mmu first.
586 WARN_ON(!kvm_is_reserved_pfn(pfn) && !page_count(pfn_to_page(pfn)));
588 if (is_accessed_spte(old_spte))
589 kvm_set_pfn_accessed(pfn);
591 if (is_dirty_spte(old_spte))
592 kvm_set_pfn_dirty(pfn);
598 * Rules for using mmu_spte_clear_no_track:
599 * Directly clear spte without caring the state bits of sptep,
600 * it is used to set the upper level spte.
602 static void mmu_spte_clear_no_track(u64 *sptep)
604 __update_clear_spte_fast(sptep, 0ull);
607 static u64 mmu_spte_get_lockless(u64 *sptep)
609 return __get_spte_lockless(sptep);
612 /* Restore an acc-track PTE back to a regular PTE */
613 static u64 restore_acc_track_spte(u64 spte)
616 u64 saved_bits = (spte >> SHADOW_ACC_TRACK_SAVED_BITS_SHIFT)
617 & SHADOW_ACC_TRACK_SAVED_BITS_MASK;
619 WARN_ON_ONCE(spte_ad_enabled(spte));
620 WARN_ON_ONCE(!is_access_track_spte(spte));
622 new_spte &= ~shadow_acc_track_mask;
623 new_spte &= ~(SHADOW_ACC_TRACK_SAVED_BITS_MASK <<
624 SHADOW_ACC_TRACK_SAVED_BITS_SHIFT);
625 new_spte |= saved_bits;
630 /* Returns the Accessed status of the PTE and resets it at the same time. */
631 static bool mmu_spte_age(u64 *sptep)
633 u64 spte = mmu_spte_get_lockless(sptep);
635 if (!is_accessed_spte(spte))
638 if (spte_ad_enabled(spte)) {
639 clear_bit((ffs(shadow_accessed_mask) - 1),
640 (unsigned long *)sptep);
643 * Capture the dirty status of the page, so that it doesn't get
644 * lost when the SPTE is marked for access tracking.
646 if (is_writable_pte(spte))
647 kvm_set_pfn_dirty(spte_to_pfn(spte));
649 spte = mark_spte_for_access_track(spte);
650 mmu_spte_update_no_track(sptep, spte);
656 static void walk_shadow_page_lockless_begin(struct kvm_vcpu *vcpu)
659 * Prevent page table teardown by making any free-er wait during
660 * kvm_flush_remote_tlbs() IPI to all active vcpus.
665 * Make sure a following spte read is not reordered ahead of the write
668 smp_store_mb(vcpu->mode, READING_SHADOW_PAGE_TABLES);
671 static void walk_shadow_page_lockless_end(struct kvm_vcpu *vcpu)
674 * Make sure the write to vcpu->mode is not reordered in front of
675 * reads to sptes. If it does, kvm_mmu_commit_zap_page() can see us
676 * OUTSIDE_GUEST_MODE and proceed to free the shadow page table.
678 smp_store_release(&vcpu->mode, OUTSIDE_GUEST_MODE);
682 static int mmu_topup_memory_caches(struct kvm_vcpu *vcpu, bool maybe_indirect)
686 /* 1 rmap, 1 parent PTE per level, and the prefetched rmaps. */
687 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache,
688 1 + PT64_ROOT_MAX_LEVEL + PTE_PREFETCH_NUM);
691 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_shadow_page_cache,
692 PT64_ROOT_MAX_LEVEL);
695 if (maybe_indirect) {
696 r = kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_gfn_array_cache,
697 PT64_ROOT_MAX_LEVEL);
701 return kvm_mmu_topup_memory_cache(&vcpu->arch.mmu_page_header_cache,
702 PT64_ROOT_MAX_LEVEL);
705 static void mmu_free_memory_caches(struct kvm_vcpu *vcpu)
707 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_pte_list_desc_cache);
708 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_shadow_page_cache);
709 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_gfn_array_cache);
710 kvm_mmu_free_memory_cache(&vcpu->arch.mmu_page_header_cache);
713 static struct pte_list_desc *mmu_alloc_pte_list_desc(struct kvm_vcpu *vcpu)
715 return kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_pte_list_desc_cache);
718 static void mmu_free_pte_list_desc(struct pte_list_desc *pte_list_desc)
720 kmem_cache_free(pte_list_desc_cache, pte_list_desc);
723 static gfn_t kvm_mmu_page_get_gfn(struct kvm_mmu_page *sp, int index)
725 if (!sp->role.direct)
726 return sp->gfns[index];
728 return sp->gfn + (index << ((sp->role.level - 1) * PT64_LEVEL_BITS));
731 static void kvm_mmu_page_set_gfn(struct kvm_mmu_page *sp, int index, gfn_t gfn)
733 if (!sp->role.direct) {
734 sp->gfns[index] = gfn;
738 if (WARN_ON(gfn != kvm_mmu_page_get_gfn(sp, index)))
739 pr_err_ratelimited("gfn mismatch under direct page %llx "
740 "(expected %llx, got %llx)\n",
742 kvm_mmu_page_get_gfn(sp, index), gfn);
746 * Return the pointer to the large page information for a given gfn,
747 * handling slots that are not large page aligned.
749 static struct kvm_lpage_info *lpage_info_slot(gfn_t gfn,
750 const struct kvm_memory_slot *slot, int level)
754 idx = gfn_to_index(gfn, slot->base_gfn, level);
755 return &slot->arch.lpage_info[level - 2][idx];
758 static void update_gfn_disallow_lpage_count(struct kvm_memory_slot *slot,
759 gfn_t gfn, int count)
761 struct kvm_lpage_info *linfo;
764 for (i = PG_LEVEL_2M; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
765 linfo = lpage_info_slot(gfn, slot, i);
766 linfo->disallow_lpage += count;
767 WARN_ON(linfo->disallow_lpage < 0);
771 void kvm_mmu_gfn_disallow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
773 update_gfn_disallow_lpage_count(slot, gfn, 1);
776 void kvm_mmu_gfn_allow_lpage(struct kvm_memory_slot *slot, gfn_t gfn)
778 update_gfn_disallow_lpage_count(slot, gfn, -1);
781 static void account_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
783 struct kvm_memslots *slots;
784 struct kvm_memory_slot *slot;
787 kvm->arch.indirect_shadow_pages++;
789 slots = kvm_memslots_for_spte_role(kvm, sp->role);
790 slot = __gfn_to_memslot(slots, gfn);
792 /* the non-leaf shadow pages are keeping readonly. */
793 if (sp->role.level > PG_LEVEL_4K)
794 return kvm_slot_page_track_add_page(kvm, slot, gfn,
795 KVM_PAGE_TRACK_WRITE);
797 kvm_mmu_gfn_disallow_lpage(slot, gfn);
800 void account_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
802 if (sp->lpage_disallowed)
805 ++kvm->stat.nx_lpage_splits;
806 list_add_tail(&sp->lpage_disallowed_link,
807 &kvm->arch.lpage_disallowed_mmu_pages);
808 sp->lpage_disallowed = true;
811 static void unaccount_shadowed(struct kvm *kvm, struct kvm_mmu_page *sp)
813 struct kvm_memslots *slots;
814 struct kvm_memory_slot *slot;
817 kvm->arch.indirect_shadow_pages--;
819 slots = kvm_memslots_for_spte_role(kvm, sp->role);
820 slot = __gfn_to_memslot(slots, gfn);
821 if (sp->role.level > PG_LEVEL_4K)
822 return kvm_slot_page_track_remove_page(kvm, slot, gfn,
823 KVM_PAGE_TRACK_WRITE);
825 kvm_mmu_gfn_allow_lpage(slot, gfn);
828 void unaccount_huge_nx_page(struct kvm *kvm, struct kvm_mmu_page *sp)
830 --kvm->stat.nx_lpage_splits;
831 sp->lpage_disallowed = false;
832 list_del(&sp->lpage_disallowed_link);
835 static struct kvm_memory_slot *
836 gfn_to_memslot_dirty_bitmap(struct kvm_vcpu *vcpu, gfn_t gfn,
839 struct kvm_memory_slot *slot;
841 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
842 if (!slot || slot->flags & KVM_MEMSLOT_INVALID)
844 if (no_dirty_log && kvm_slot_dirty_track_enabled(slot))
851 * About rmap_head encoding:
853 * If the bit zero of rmap_head->val is clear, then it points to the only spte
854 * in this rmap chain. Otherwise, (rmap_head->val & ~1) points to a struct
855 * pte_list_desc containing more mappings.
859 * Returns the number of pointers in the rmap chain, not counting the new one.
861 static int pte_list_add(struct kvm_vcpu *vcpu, u64 *spte,
862 struct kvm_rmap_head *rmap_head)
864 struct pte_list_desc *desc;
867 if (!rmap_head->val) {
868 rmap_printk("%p %llx 0->1\n", spte, *spte);
869 rmap_head->val = (unsigned long)spte;
870 } else if (!(rmap_head->val & 1)) {
871 rmap_printk("%p %llx 1->many\n", spte, *spte);
872 desc = mmu_alloc_pte_list_desc(vcpu);
873 desc->sptes[0] = (u64 *)rmap_head->val;
874 desc->sptes[1] = spte;
875 rmap_head->val = (unsigned long)desc | 1;
878 rmap_printk("%p %llx many->many\n", spte, *spte);
879 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
880 while (desc->sptes[PTE_LIST_EXT-1]) {
881 count += PTE_LIST_EXT;
884 desc->more = mmu_alloc_pte_list_desc(vcpu);
890 for (i = 0; desc->sptes[i]; ++i)
892 desc->sptes[i] = spte;
898 pte_list_desc_remove_entry(struct kvm_rmap_head *rmap_head,
899 struct pte_list_desc *desc, int i,
900 struct pte_list_desc *prev_desc)
904 for (j = PTE_LIST_EXT - 1; !desc->sptes[j] && j > i; --j)
906 desc->sptes[i] = desc->sptes[j];
907 desc->sptes[j] = NULL;
910 if (!prev_desc && !desc->more)
914 prev_desc->more = desc->more;
916 rmap_head->val = (unsigned long)desc->more | 1;
917 mmu_free_pte_list_desc(desc);
920 static void __pte_list_remove(u64 *spte, struct kvm_rmap_head *rmap_head)
922 struct pte_list_desc *desc;
923 struct pte_list_desc *prev_desc;
926 if (!rmap_head->val) {
927 pr_err("%s: %p 0->BUG\n", __func__, spte);
929 } else if (!(rmap_head->val & 1)) {
930 rmap_printk("%p 1->0\n", spte);
931 if ((u64 *)rmap_head->val != spte) {
932 pr_err("%s: %p 1->BUG\n", __func__, spte);
937 rmap_printk("%p many->many\n", spte);
938 desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
941 for (i = 0; i < PTE_LIST_EXT && desc->sptes[i]; ++i) {
942 if (desc->sptes[i] == spte) {
943 pte_list_desc_remove_entry(rmap_head,
951 pr_err("%s: %p many->many\n", __func__, spte);
956 static void pte_list_remove(struct kvm_rmap_head *rmap_head, u64 *sptep)
958 mmu_spte_clear_track_bits(sptep);
959 __pte_list_remove(sptep, rmap_head);
962 static struct kvm_rmap_head *__gfn_to_rmap(gfn_t gfn, int level,
963 struct kvm_memory_slot *slot)
967 idx = gfn_to_index(gfn, slot->base_gfn, level);
968 return &slot->arch.rmap[level - PG_LEVEL_4K][idx];
971 static struct kvm_rmap_head *gfn_to_rmap(struct kvm *kvm, gfn_t gfn,
972 struct kvm_mmu_page *sp)
974 struct kvm_memslots *slots;
975 struct kvm_memory_slot *slot;
977 slots = kvm_memslots_for_spte_role(kvm, sp->role);
978 slot = __gfn_to_memslot(slots, gfn);
979 return __gfn_to_rmap(gfn, sp->role.level, slot);
982 static bool rmap_can_add(struct kvm_vcpu *vcpu)
984 struct kvm_mmu_memory_cache *mc;
986 mc = &vcpu->arch.mmu_pte_list_desc_cache;
987 return kvm_mmu_memory_cache_nr_free_objects(mc);
990 static int rmap_add(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
992 struct kvm_mmu_page *sp;
993 struct kvm_rmap_head *rmap_head;
995 sp = sptep_to_sp(spte);
996 kvm_mmu_page_set_gfn(sp, spte - sp->spt, gfn);
997 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
998 return pte_list_add(vcpu, spte, rmap_head);
1001 static void rmap_remove(struct kvm *kvm, u64 *spte)
1003 struct kvm_mmu_page *sp;
1005 struct kvm_rmap_head *rmap_head;
1007 sp = sptep_to_sp(spte);
1008 gfn = kvm_mmu_page_get_gfn(sp, spte - sp->spt);
1009 rmap_head = gfn_to_rmap(kvm, gfn, sp);
1010 __pte_list_remove(spte, rmap_head);
1014 * Used by the following functions to iterate through the sptes linked by a
1015 * rmap. All fields are private and not assumed to be used outside.
1017 struct rmap_iterator {
1018 /* private fields */
1019 struct pte_list_desc *desc; /* holds the sptep if not NULL */
1020 int pos; /* index of the sptep */
1024 * Iteration must be started by this function. This should also be used after
1025 * removing/dropping sptes from the rmap link because in such cases the
1026 * information in the iterator may not be valid.
1028 * Returns sptep if found, NULL otherwise.
1030 static u64 *rmap_get_first(struct kvm_rmap_head *rmap_head,
1031 struct rmap_iterator *iter)
1035 if (!rmap_head->val)
1038 if (!(rmap_head->val & 1)) {
1040 sptep = (u64 *)rmap_head->val;
1044 iter->desc = (struct pte_list_desc *)(rmap_head->val & ~1ul);
1046 sptep = iter->desc->sptes[iter->pos];
1048 BUG_ON(!is_shadow_present_pte(*sptep));
1053 * Must be used with a valid iterator: e.g. after rmap_get_first().
1055 * Returns sptep if found, NULL otherwise.
1057 static u64 *rmap_get_next(struct rmap_iterator *iter)
1062 if (iter->pos < PTE_LIST_EXT - 1) {
1064 sptep = iter->desc->sptes[iter->pos];
1069 iter->desc = iter->desc->more;
1073 /* desc->sptes[0] cannot be NULL */
1074 sptep = iter->desc->sptes[iter->pos];
1081 BUG_ON(!is_shadow_present_pte(*sptep));
1085 #define for_each_rmap_spte(_rmap_head_, _iter_, _spte_) \
1086 for (_spte_ = rmap_get_first(_rmap_head_, _iter_); \
1087 _spte_; _spte_ = rmap_get_next(_iter_))
1089 static void drop_spte(struct kvm *kvm, u64 *sptep)
1091 if (mmu_spte_clear_track_bits(sptep))
1092 rmap_remove(kvm, sptep);
1096 static bool __drop_large_spte(struct kvm *kvm, u64 *sptep)
1098 if (is_large_pte(*sptep)) {
1099 WARN_ON(sptep_to_sp(sptep)->role.level == PG_LEVEL_4K);
1100 drop_spte(kvm, sptep);
1108 static void drop_large_spte(struct kvm_vcpu *vcpu, u64 *sptep)
1110 if (__drop_large_spte(vcpu->kvm, sptep)) {
1111 struct kvm_mmu_page *sp = sptep_to_sp(sptep);
1113 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1114 KVM_PAGES_PER_HPAGE(sp->role.level));
1119 * Write-protect on the specified @sptep, @pt_protect indicates whether
1120 * spte write-protection is caused by protecting shadow page table.
1122 * Note: write protection is difference between dirty logging and spte
1124 * - for dirty logging, the spte can be set to writable at anytime if
1125 * its dirty bitmap is properly set.
1126 * - for spte protection, the spte can be writable only after unsync-ing
1129 * Return true if tlb need be flushed.
1131 static bool spte_write_protect(u64 *sptep, bool pt_protect)
1135 if (!is_writable_pte(spte) &&
1136 !(pt_protect && spte_can_locklessly_be_made_writable(spte)))
1139 rmap_printk("spte %p %llx\n", sptep, *sptep);
1142 spte &= ~shadow_mmu_writable_mask;
1143 spte = spte & ~PT_WRITABLE_MASK;
1145 return mmu_spte_update(sptep, spte);
1148 static bool __rmap_write_protect(struct kvm *kvm,
1149 struct kvm_rmap_head *rmap_head,
1153 struct rmap_iterator iter;
1156 for_each_rmap_spte(rmap_head, &iter, sptep)
1157 flush |= spte_write_protect(sptep, pt_protect);
1162 static bool spte_clear_dirty(u64 *sptep)
1166 rmap_printk("spte %p %llx\n", sptep, *sptep);
1168 MMU_WARN_ON(!spte_ad_enabled(spte));
1169 spte &= ~shadow_dirty_mask;
1170 return mmu_spte_update(sptep, spte);
1173 static bool spte_wrprot_for_clear_dirty(u64 *sptep)
1175 bool was_writable = test_and_clear_bit(PT_WRITABLE_SHIFT,
1176 (unsigned long *)sptep);
1177 if (was_writable && !spte_ad_enabled(*sptep))
1178 kvm_set_pfn_dirty(spte_to_pfn(*sptep));
1180 return was_writable;
1184 * Gets the GFN ready for another round of dirty logging by clearing the
1185 * - D bit on ad-enabled SPTEs, and
1186 * - W bit on ad-disabled SPTEs.
1187 * Returns true iff any D or W bits were cleared.
1189 static bool __rmap_clear_dirty(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1190 struct kvm_memory_slot *slot)
1193 struct rmap_iterator iter;
1196 for_each_rmap_spte(rmap_head, &iter, sptep)
1197 if (spte_ad_need_write_protect(*sptep))
1198 flush |= spte_wrprot_for_clear_dirty(sptep);
1200 flush |= spte_clear_dirty(sptep);
1206 * kvm_mmu_write_protect_pt_masked - write protect selected PT level pages
1207 * @kvm: kvm instance
1208 * @slot: slot to protect
1209 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1210 * @mask: indicates which pages we should protect
1212 * Used when we do not need to care about huge page mappings.
1214 static void kvm_mmu_write_protect_pt_masked(struct kvm *kvm,
1215 struct kvm_memory_slot *slot,
1216 gfn_t gfn_offset, unsigned long mask)
1218 struct kvm_rmap_head *rmap_head;
1220 if (is_tdp_mmu_enabled(kvm))
1221 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1222 slot->base_gfn + gfn_offset, mask, true);
1224 if (!kvm_memslots_have_rmaps(kvm))
1228 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1230 __rmap_write_protect(kvm, rmap_head, false);
1232 /* clear the first set bit */
1238 * kvm_mmu_clear_dirty_pt_masked - clear MMU D-bit for PT level pages, or write
1239 * protect the page if the D-bit isn't supported.
1240 * @kvm: kvm instance
1241 * @slot: slot to clear D-bit
1242 * @gfn_offset: start of the BITS_PER_LONG pages we care about
1243 * @mask: indicates which pages we should clear D-bit
1245 * Used for PML to re-log the dirty GPAs after userspace querying dirty_bitmap.
1247 static void kvm_mmu_clear_dirty_pt_masked(struct kvm *kvm,
1248 struct kvm_memory_slot *slot,
1249 gfn_t gfn_offset, unsigned long mask)
1251 struct kvm_rmap_head *rmap_head;
1253 if (is_tdp_mmu_enabled(kvm))
1254 kvm_tdp_mmu_clear_dirty_pt_masked(kvm, slot,
1255 slot->base_gfn + gfn_offset, mask, false);
1257 if (!kvm_memslots_have_rmaps(kvm))
1261 rmap_head = __gfn_to_rmap(slot->base_gfn + gfn_offset + __ffs(mask),
1263 __rmap_clear_dirty(kvm, rmap_head, slot);
1265 /* clear the first set bit */
1271 * kvm_arch_mmu_enable_log_dirty_pt_masked - enable dirty logging for selected
1274 * It calls kvm_mmu_write_protect_pt_masked to write protect selected pages to
1275 * enable dirty logging for them.
1277 * We need to care about huge page mappings: e.g. during dirty logging we may
1278 * have such mappings.
1280 void kvm_arch_mmu_enable_log_dirty_pt_masked(struct kvm *kvm,
1281 struct kvm_memory_slot *slot,
1282 gfn_t gfn_offset, unsigned long mask)
1285 * Huge pages are NOT write protected when we start dirty logging in
1286 * initially-all-set mode; must write protect them here so that they
1287 * are split to 4K on the first write.
1289 * The gfn_offset is guaranteed to be aligned to 64, but the base_gfn
1290 * of memslot has no such restriction, so the range can cross two large
1293 if (kvm_dirty_log_manual_protect_and_init_set(kvm)) {
1294 gfn_t start = slot->base_gfn + gfn_offset + __ffs(mask);
1295 gfn_t end = slot->base_gfn + gfn_offset + __fls(mask);
1297 kvm_mmu_slot_gfn_write_protect(kvm, slot, start, PG_LEVEL_2M);
1299 /* Cross two large pages? */
1300 if (ALIGN(start << PAGE_SHIFT, PMD_SIZE) !=
1301 ALIGN(end << PAGE_SHIFT, PMD_SIZE))
1302 kvm_mmu_slot_gfn_write_protect(kvm, slot, end,
1306 /* Now handle 4K PTEs. */
1307 if (kvm_x86_ops.cpu_dirty_log_size)
1308 kvm_mmu_clear_dirty_pt_masked(kvm, slot, gfn_offset, mask);
1310 kvm_mmu_write_protect_pt_masked(kvm, slot, gfn_offset, mask);
1313 int kvm_cpu_dirty_log_size(void)
1315 return kvm_x86_ops.cpu_dirty_log_size;
1318 bool kvm_mmu_slot_gfn_write_protect(struct kvm *kvm,
1319 struct kvm_memory_slot *slot, u64 gfn,
1322 struct kvm_rmap_head *rmap_head;
1324 bool write_protected = false;
1326 if (kvm_memslots_have_rmaps(kvm)) {
1327 for (i = min_level; i <= KVM_MAX_HUGEPAGE_LEVEL; ++i) {
1328 rmap_head = __gfn_to_rmap(gfn, i, slot);
1329 write_protected |= __rmap_write_protect(kvm, rmap_head, true);
1333 if (is_tdp_mmu_enabled(kvm))
1335 kvm_tdp_mmu_write_protect_gfn(kvm, slot, gfn, min_level);
1337 return write_protected;
1340 static bool rmap_write_protect(struct kvm_vcpu *vcpu, u64 gfn)
1342 struct kvm_memory_slot *slot;
1344 slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
1345 return kvm_mmu_slot_gfn_write_protect(vcpu->kvm, slot, gfn, PG_LEVEL_4K);
1348 static bool kvm_zap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1349 struct kvm_memory_slot *slot)
1352 struct rmap_iterator iter;
1355 while ((sptep = rmap_get_first(rmap_head, &iter))) {
1356 rmap_printk("spte %p %llx.\n", sptep, *sptep);
1358 pte_list_remove(rmap_head, sptep);
1365 static bool kvm_unmap_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1366 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1369 return kvm_zap_rmapp(kvm, rmap_head, slot);
1372 static bool kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1373 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1377 struct rmap_iterator iter;
1382 WARN_ON(pte_huge(pte));
1383 new_pfn = pte_pfn(pte);
1386 for_each_rmap_spte(rmap_head, &iter, sptep) {
1387 rmap_printk("spte %p %llx gfn %llx (%d)\n",
1388 sptep, *sptep, gfn, level);
1392 if (pte_write(pte)) {
1393 pte_list_remove(rmap_head, sptep);
1396 new_spte = kvm_mmu_changed_pte_notifier_make_spte(
1399 mmu_spte_clear_track_bits(sptep);
1400 mmu_spte_set(sptep, new_spte);
1404 if (need_flush && kvm_available_flush_tlb_with_range()) {
1405 kvm_flush_remote_tlbs_with_address(kvm, gfn, 1);
1412 struct slot_rmap_walk_iterator {
1414 struct kvm_memory_slot *slot;
1420 /* output fields. */
1422 struct kvm_rmap_head *rmap;
1425 /* private field. */
1426 struct kvm_rmap_head *end_rmap;
1430 rmap_walk_init_level(struct slot_rmap_walk_iterator *iterator, int level)
1432 iterator->level = level;
1433 iterator->gfn = iterator->start_gfn;
1434 iterator->rmap = __gfn_to_rmap(iterator->gfn, level, iterator->slot);
1435 iterator->end_rmap = __gfn_to_rmap(iterator->end_gfn, level,
1440 slot_rmap_walk_init(struct slot_rmap_walk_iterator *iterator,
1441 struct kvm_memory_slot *slot, int start_level,
1442 int end_level, gfn_t start_gfn, gfn_t end_gfn)
1444 iterator->slot = slot;
1445 iterator->start_level = start_level;
1446 iterator->end_level = end_level;
1447 iterator->start_gfn = start_gfn;
1448 iterator->end_gfn = end_gfn;
1450 rmap_walk_init_level(iterator, iterator->start_level);
1453 static bool slot_rmap_walk_okay(struct slot_rmap_walk_iterator *iterator)
1455 return !!iterator->rmap;
1458 static void slot_rmap_walk_next(struct slot_rmap_walk_iterator *iterator)
1460 if (++iterator->rmap <= iterator->end_rmap) {
1461 iterator->gfn += (1UL << KVM_HPAGE_GFN_SHIFT(iterator->level));
1465 if (++iterator->level > iterator->end_level) {
1466 iterator->rmap = NULL;
1470 rmap_walk_init_level(iterator, iterator->level);
1473 #define for_each_slot_rmap_range(_slot_, _start_level_, _end_level_, \
1474 _start_gfn, _end_gfn, _iter_) \
1475 for (slot_rmap_walk_init(_iter_, _slot_, _start_level_, \
1476 _end_level_, _start_gfn, _end_gfn); \
1477 slot_rmap_walk_okay(_iter_); \
1478 slot_rmap_walk_next(_iter_))
1480 typedef bool (*rmap_handler_t)(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1481 struct kvm_memory_slot *slot, gfn_t gfn,
1482 int level, pte_t pte);
1484 static __always_inline bool kvm_handle_gfn_range(struct kvm *kvm,
1485 struct kvm_gfn_range *range,
1486 rmap_handler_t handler)
1488 struct slot_rmap_walk_iterator iterator;
1491 for_each_slot_rmap_range(range->slot, PG_LEVEL_4K, KVM_MAX_HUGEPAGE_LEVEL,
1492 range->start, range->end - 1, &iterator)
1493 ret |= handler(kvm, iterator.rmap, range->slot, iterator.gfn,
1494 iterator.level, range->pte);
1499 bool kvm_unmap_gfn_range(struct kvm *kvm, struct kvm_gfn_range *range)
1503 if (kvm_memslots_have_rmaps(kvm))
1504 flush = kvm_handle_gfn_range(kvm, range, kvm_unmap_rmapp);
1506 if (is_tdp_mmu_enabled(kvm))
1507 flush |= kvm_tdp_mmu_unmap_gfn_range(kvm, range, flush);
1512 bool kvm_set_spte_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1516 if (kvm_memslots_have_rmaps(kvm))
1517 flush = kvm_handle_gfn_range(kvm, range, kvm_set_pte_rmapp);
1519 if (is_tdp_mmu_enabled(kvm))
1520 flush |= kvm_tdp_mmu_set_spte_gfn(kvm, range);
1525 static bool kvm_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1526 struct kvm_memory_slot *slot, gfn_t gfn, int level,
1530 struct rmap_iterator iter;
1533 for_each_rmap_spte(rmap_head, &iter, sptep)
1534 young |= mmu_spte_age(sptep);
1539 static bool kvm_test_age_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head,
1540 struct kvm_memory_slot *slot, gfn_t gfn,
1541 int level, pte_t unused)
1544 struct rmap_iterator iter;
1546 for_each_rmap_spte(rmap_head, &iter, sptep)
1547 if (is_accessed_spte(*sptep))
1552 #define RMAP_RECYCLE_THRESHOLD 1000
1554 static void rmap_recycle(struct kvm_vcpu *vcpu, u64 *spte, gfn_t gfn)
1556 struct kvm_rmap_head *rmap_head;
1557 struct kvm_mmu_page *sp;
1559 sp = sptep_to_sp(spte);
1561 rmap_head = gfn_to_rmap(vcpu->kvm, gfn, sp);
1563 kvm_unmap_rmapp(vcpu->kvm, rmap_head, NULL, gfn, sp->role.level, __pte(0));
1564 kvm_flush_remote_tlbs_with_address(vcpu->kvm, sp->gfn,
1565 KVM_PAGES_PER_HPAGE(sp->role.level));
1568 bool kvm_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1572 if (kvm_memslots_have_rmaps(kvm))
1573 young = kvm_handle_gfn_range(kvm, range, kvm_age_rmapp);
1575 if (is_tdp_mmu_enabled(kvm))
1576 young |= kvm_tdp_mmu_age_gfn_range(kvm, range);
1581 bool kvm_test_age_gfn(struct kvm *kvm, struct kvm_gfn_range *range)
1585 if (kvm_memslots_have_rmaps(kvm))
1586 young = kvm_handle_gfn_range(kvm, range, kvm_test_age_rmapp);
1588 if (is_tdp_mmu_enabled(kvm))
1589 young |= kvm_tdp_mmu_test_age_gfn(kvm, range);
1595 static int is_empty_shadow_page(u64 *spt)
1600 for (pos = spt, end = pos + PAGE_SIZE / sizeof(u64); pos != end; pos++)
1601 if (is_shadow_present_pte(*pos)) {
1602 printk(KERN_ERR "%s: %p %llx\n", __func__,
1611 * This value is the sum of all of the kvm instances's
1612 * kvm->arch.n_used_mmu_pages values. We need a global,
1613 * aggregate version in order to make the slab shrinker
1616 static inline void kvm_mod_used_mmu_pages(struct kvm *kvm, unsigned long nr)
1618 kvm->arch.n_used_mmu_pages += nr;
1619 percpu_counter_add(&kvm_total_used_mmu_pages, nr);
1622 static void kvm_mmu_free_page(struct kvm_mmu_page *sp)
1624 MMU_WARN_ON(!is_empty_shadow_page(sp->spt));
1625 hlist_del(&sp->hash_link);
1626 list_del(&sp->link);
1627 free_page((unsigned long)sp->spt);
1628 if (!sp->role.direct)
1629 free_page((unsigned long)sp->gfns);
1630 kmem_cache_free(mmu_page_header_cache, sp);
1633 static unsigned kvm_page_table_hashfn(gfn_t gfn)
1635 return hash_64(gfn, KVM_MMU_HASH_SHIFT);
1638 static void mmu_page_add_parent_pte(struct kvm_vcpu *vcpu,
1639 struct kvm_mmu_page *sp, u64 *parent_pte)
1644 pte_list_add(vcpu, parent_pte, &sp->parent_ptes);
1647 static void mmu_page_remove_parent_pte(struct kvm_mmu_page *sp,
1650 __pte_list_remove(parent_pte, &sp->parent_ptes);
1653 static void drop_parent_pte(struct kvm_mmu_page *sp,
1656 mmu_page_remove_parent_pte(sp, parent_pte);
1657 mmu_spte_clear_no_track(parent_pte);
1660 static struct kvm_mmu_page *kvm_mmu_alloc_page(struct kvm_vcpu *vcpu, int direct)
1662 struct kvm_mmu_page *sp;
1664 sp = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_page_header_cache);
1665 sp->spt = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_shadow_page_cache);
1667 sp->gfns = kvm_mmu_memory_cache_alloc(&vcpu->arch.mmu_gfn_array_cache);
1668 set_page_private(virt_to_page(sp->spt), (unsigned long)sp);
1671 * active_mmu_pages must be a FIFO list, as kvm_zap_obsolete_pages()
1672 * depends on valid pages being added to the head of the list. See
1673 * comments in kvm_zap_obsolete_pages().
1675 sp->mmu_valid_gen = vcpu->kvm->arch.mmu_valid_gen;
1676 list_add(&sp->link, &vcpu->kvm->arch.active_mmu_pages);
1677 kvm_mod_used_mmu_pages(vcpu->kvm, +1);
1681 static void mark_unsync(u64 *spte);
1682 static void kvm_mmu_mark_parents_unsync(struct kvm_mmu_page *sp)
1685 struct rmap_iterator iter;
1687 for_each_rmap_spte(&sp->parent_ptes, &iter, sptep) {
1692 static void mark_unsync(u64 *spte)
1694 struct kvm_mmu_page *sp;
1697 sp = sptep_to_sp(spte);
1698 index = spte - sp->spt;
1699 if (__test_and_set_bit(index, sp->unsync_child_bitmap))
1701 if (sp->unsync_children++)
1703 kvm_mmu_mark_parents_unsync(sp);
1706 static int nonpaging_sync_page(struct kvm_vcpu *vcpu,
1707 struct kvm_mmu_page *sp)
1712 #define KVM_PAGE_ARRAY_NR 16
1714 struct kvm_mmu_pages {
1715 struct mmu_page_and_offset {
1716 struct kvm_mmu_page *sp;
1718 } page[KVM_PAGE_ARRAY_NR];
1722 static int mmu_pages_add(struct kvm_mmu_pages *pvec, struct kvm_mmu_page *sp,
1728 for (i=0; i < pvec->nr; i++)
1729 if (pvec->page[i].sp == sp)
1732 pvec->page[pvec->nr].sp = sp;
1733 pvec->page[pvec->nr].idx = idx;
1735 return (pvec->nr == KVM_PAGE_ARRAY_NR);
1738 static inline void clear_unsync_child_bit(struct kvm_mmu_page *sp, int idx)
1740 --sp->unsync_children;
1741 WARN_ON((int)sp->unsync_children < 0);
1742 __clear_bit(idx, sp->unsync_child_bitmap);
1745 static int __mmu_unsync_walk(struct kvm_mmu_page *sp,
1746 struct kvm_mmu_pages *pvec)
1748 int i, ret, nr_unsync_leaf = 0;
1750 for_each_set_bit(i, sp->unsync_child_bitmap, 512) {
1751 struct kvm_mmu_page *child;
1752 u64 ent = sp->spt[i];
1754 if (!is_shadow_present_pte(ent) || is_large_pte(ent)) {
1755 clear_unsync_child_bit(sp, i);
1759 child = to_shadow_page(ent & PT64_BASE_ADDR_MASK);
1761 if (child->unsync_children) {
1762 if (mmu_pages_add(pvec, child, i))
1765 ret = __mmu_unsync_walk(child, pvec);
1767 clear_unsync_child_bit(sp, i);
1769 } else if (ret > 0) {
1770 nr_unsync_leaf += ret;
1773 } else if (child->unsync) {
1775 if (mmu_pages_add(pvec, child, i))
1778 clear_unsync_child_bit(sp, i);
1781 return nr_unsync_leaf;
1784 #define INVALID_INDEX (-1)
1786 static int mmu_unsync_walk(struct kvm_mmu_page *sp,
1787 struct kvm_mmu_pages *pvec)
1790 if (!sp->unsync_children)
1793 mmu_pages_add(pvec, sp, INVALID_INDEX);
1794 return __mmu_unsync_walk(sp, pvec);
1797 static void kvm_unlink_unsync_page(struct kvm *kvm, struct kvm_mmu_page *sp)
1799 WARN_ON(!sp->unsync);
1800 trace_kvm_mmu_sync_page(sp);
1802 --kvm->stat.mmu_unsync;
1805 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
1806 struct list_head *invalid_list);
1807 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
1808 struct list_head *invalid_list);
1810 #define for_each_valid_sp(_kvm, _sp, _list) \
1811 hlist_for_each_entry(_sp, _list, hash_link) \
1812 if (is_obsolete_sp((_kvm), (_sp))) { \
1815 #define for_each_gfn_indirect_valid_sp(_kvm, _sp, _gfn) \
1816 for_each_valid_sp(_kvm, _sp, \
1817 &(_kvm)->arch.mmu_page_hash[kvm_page_table_hashfn(_gfn)]) \
1818 if ((_sp)->gfn != (_gfn) || (_sp)->role.direct) {} else
1820 static bool kvm_sync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
1821 struct list_head *invalid_list)
1823 if (vcpu->arch.mmu->sync_page(vcpu, sp) == 0) {
1824 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, invalid_list);
1831 static bool kvm_mmu_remote_flush_or_zap(struct kvm *kvm,
1832 struct list_head *invalid_list,
1835 if (!remote_flush && list_empty(invalid_list))
1838 if (!list_empty(invalid_list))
1839 kvm_mmu_commit_zap_page(kvm, invalid_list);
1841 kvm_flush_remote_tlbs(kvm);
1845 static void kvm_mmu_flush_or_zap(struct kvm_vcpu *vcpu,
1846 struct list_head *invalid_list,
1847 bool remote_flush, bool local_flush)
1849 if (kvm_mmu_remote_flush_or_zap(vcpu->kvm, invalid_list, remote_flush))
1853 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
1856 #ifdef CONFIG_KVM_MMU_AUDIT
1857 #include "mmu_audit.c"
1859 static void kvm_mmu_audit(struct kvm_vcpu *vcpu, int point) { }
1860 static void mmu_audit_disable(void) { }
1863 static bool is_obsolete_sp(struct kvm *kvm, struct kvm_mmu_page *sp)
1865 return sp->role.invalid ||
1866 unlikely(sp->mmu_valid_gen != kvm->arch.mmu_valid_gen);
1869 struct mmu_page_path {
1870 struct kvm_mmu_page *parent[PT64_ROOT_MAX_LEVEL];
1871 unsigned int idx[PT64_ROOT_MAX_LEVEL];
1874 #define for_each_sp(pvec, sp, parents, i) \
1875 for (i = mmu_pages_first(&pvec, &parents); \
1876 i < pvec.nr && ({ sp = pvec.page[i].sp; 1;}); \
1877 i = mmu_pages_next(&pvec, &parents, i))
1879 static int mmu_pages_next(struct kvm_mmu_pages *pvec,
1880 struct mmu_page_path *parents,
1885 for (n = i+1; n < pvec->nr; n++) {
1886 struct kvm_mmu_page *sp = pvec->page[n].sp;
1887 unsigned idx = pvec->page[n].idx;
1888 int level = sp->role.level;
1890 parents->idx[level-1] = idx;
1891 if (level == PG_LEVEL_4K)
1894 parents->parent[level-2] = sp;
1900 static int mmu_pages_first(struct kvm_mmu_pages *pvec,
1901 struct mmu_page_path *parents)
1903 struct kvm_mmu_page *sp;
1909 WARN_ON(pvec->page[0].idx != INVALID_INDEX);
1911 sp = pvec->page[0].sp;
1912 level = sp->role.level;
1913 WARN_ON(level == PG_LEVEL_4K);
1915 parents->parent[level-2] = sp;
1917 /* Also set up a sentinel. Further entries in pvec are all
1918 * children of sp, so this element is never overwritten.
1920 parents->parent[level-1] = NULL;
1921 return mmu_pages_next(pvec, parents, 0);
1924 static void mmu_pages_clear_parents(struct mmu_page_path *parents)
1926 struct kvm_mmu_page *sp;
1927 unsigned int level = 0;
1930 unsigned int idx = parents->idx[level];
1931 sp = parents->parent[level];
1935 WARN_ON(idx == INVALID_INDEX);
1936 clear_unsync_child_bit(sp, idx);
1938 } while (!sp->unsync_children);
1941 static void mmu_sync_children(struct kvm_vcpu *vcpu,
1942 struct kvm_mmu_page *parent)
1945 struct kvm_mmu_page *sp;
1946 struct mmu_page_path parents;
1947 struct kvm_mmu_pages pages;
1948 LIST_HEAD(invalid_list);
1951 while (mmu_unsync_walk(parent, &pages)) {
1952 bool protected = false;
1954 for_each_sp(pages, sp, parents, i)
1955 protected |= rmap_write_protect(vcpu, sp->gfn);
1958 kvm_flush_remote_tlbs(vcpu->kvm);
1962 for_each_sp(pages, sp, parents, i) {
1963 kvm_unlink_unsync_page(vcpu->kvm, sp);
1964 flush |= kvm_sync_page(vcpu, sp, &invalid_list);
1965 mmu_pages_clear_parents(&parents);
1967 if (need_resched() || rwlock_needbreak(&vcpu->kvm->mmu_lock)) {
1968 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1969 cond_resched_rwlock_write(&vcpu->kvm->mmu_lock);
1974 kvm_mmu_flush_or_zap(vcpu, &invalid_list, false, flush);
1977 static void __clear_sp_write_flooding_count(struct kvm_mmu_page *sp)
1979 atomic_set(&sp->write_flooding_count, 0);
1982 static void clear_sp_write_flooding_count(u64 *spte)
1984 __clear_sp_write_flooding_count(sptep_to_sp(spte));
1987 static struct kvm_mmu_page *kvm_mmu_get_page(struct kvm_vcpu *vcpu,
1992 unsigned int access)
1994 bool direct_mmu = vcpu->arch.mmu->direct_map;
1995 union kvm_mmu_page_role role;
1996 struct hlist_head *sp_list;
1998 struct kvm_mmu_page *sp;
2000 LIST_HEAD(invalid_list);
2002 role = vcpu->arch.mmu->mmu_role.base;
2004 role.direct = direct;
2006 role.gpte_is_8_bytes = true;
2007 role.access = access;
2008 if (!direct_mmu && vcpu->arch.mmu->root_level <= PT32_ROOT_LEVEL) {
2009 quadrant = gaddr >> (PAGE_SHIFT + (PT64_PT_BITS * level));
2010 quadrant &= (1 << ((PT32_PT_BITS - PT64_PT_BITS) * level)) - 1;
2011 role.quadrant = quadrant;
2014 sp_list = &vcpu->kvm->arch.mmu_page_hash[kvm_page_table_hashfn(gfn)];
2015 for_each_valid_sp(vcpu->kvm, sp, sp_list) {
2016 if (sp->gfn != gfn) {
2021 if (sp->role.word != role.word) {
2023 * If the guest is creating an upper-level page, zap
2024 * unsync pages for the same gfn. While it's possible
2025 * the guest is using recursive page tables, in all
2026 * likelihood the guest has stopped using the unsync
2027 * page and is installing a completely unrelated page.
2028 * Unsync pages must not be left as is, because the new
2029 * upper-level page will be write-protected.
2031 if (level > PG_LEVEL_4K && sp->unsync)
2032 kvm_mmu_prepare_zap_page(vcpu->kvm, sp,
2038 goto trace_get_page;
2042 * The page is good, but is stale. kvm_sync_page does
2043 * get the latest guest state, but (unlike mmu_unsync_children)
2044 * it doesn't write-protect the page or mark it synchronized!
2045 * This way the validity of the mapping is ensured, but the
2046 * overhead of write protection is not incurred until the
2047 * guest invalidates the TLB mapping. This allows multiple
2048 * SPs for a single gfn to be unsync.
2050 * If the sync fails, the page is zapped. If so, break
2051 * in order to rebuild it.
2053 if (!kvm_sync_page(vcpu, sp, &invalid_list))
2056 WARN_ON(!list_empty(&invalid_list));
2057 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2060 if (sp->unsync_children)
2061 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
2063 __clear_sp_write_flooding_count(sp);
2066 trace_kvm_mmu_get_page(sp, false);
2070 ++vcpu->kvm->stat.mmu_cache_miss;
2072 sp = kvm_mmu_alloc_page(vcpu, direct);
2076 hlist_add_head(&sp->hash_link, sp_list);
2078 account_shadowed(vcpu->kvm, sp);
2079 if (level == PG_LEVEL_4K && rmap_write_protect(vcpu, gfn))
2080 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn, 1);
2082 trace_kvm_mmu_get_page(sp, true);
2084 kvm_mmu_commit_zap_page(vcpu->kvm, &invalid_list);
2086 if (collisions > vcpu->kvm->stat.max_mmu_page_hash_collisions)
2087 vcpu->kvm->stat.max_mmu_page_hash_collisions = collisions;
2091 static void shadow_walk_init_using_root(struct kvm_shadow_walk_iterator *iterator,
2092 struct kvm_vcpu *vcpu, hpa_t root,
2095 iterator->addr = addr;
2096 iterator->shadow_addr = root;
2097 iterator->level = vcpu->arch.mmu->shadow_root_level;
2099 if (iterator->level == PT64_ROOT_4LEVEL &&
2100 vcpu->arch.mmu->root_level < PT64_ROOT_4LEVEL &&
2101 !vcpu->arch.mmu->direct_map)
2104 if (iterator->level == PT32E_ROOT_LEVEL) {
2106 * prev_root is currently only used for 64-bit hosts. So only
2107 * the active root_hpa is valid here.
2109 BUG_ON(root != vcpu->arch.mmu->root_hpa);
2111 iterator->shadow_addr
2112 = vcpu->arch.mmu->pae_root[(addr >> 30) & 3];
2113 iterator->shadow_addr &= PT64_BASE_ADDR_MASK;
2115 if (!iterator->shadow_addr)
2116 iterator->level = 0;
2120 static void shadow_walk_init(struct kvm_shadow_walk_iterator *iterator,
2121 struct kvm_vcpu *vcpu, u64 addr)
2123 shadow_walk_init_using_root(iterator, vcpu, vcpu->arch.mmu->root_hpa,
2127 static bool shadow_walk_okay(struct kvm_shadow_walk_iterator *iterator)
2129 if (iterator->level < PG_LEVEL_4K)
2132 iterator->index = SHADOW_PT_INDEX(iterator->addr, iterator->level);
2133 iterator->sptep = ((u64 *)__va(iterator->shadow_addr)) + iterator->index;
2137 static void __shadow_walk_next(struct kvm_shadow_walk_iterator *iterator,
2140 if (is_last_spte(spte, iterator->level)) {
2141 iterator->level = 0;
2145 iterator->shadow_addr = spte & PT64_BASE_ADDR_MASK;
2149 static void shadow_walk_next(struct kvm_shadow_walk_iterator *iterator)
2151 __shadow_walk_next(iterator, *iterator->sptep);
2154 static void link_shadow_page(struct kvm_vcpu *vcpu, u64 *sptep,
2155 struct kvm_mmu_page *sp)
2159 BUILD_BUG_ON(VMX_EPT_WRITABLE_MASK != PT_WRITABLE_MASK);
2161 spte = make_nonleaf_spte(sp->spt, sp_ad_disabled(sp));
2163 mmu_spte_set(sptep, spte);
2165 mmu_page_add_parent_pte(vcpu, sp, sptep);
2167 if (sp->unsync_children || sp->unsync)
2171 static void validate_direct_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2172 unsigned direct_access)
2174 if (is_shadow_present_pte(*sptep) && !is_large_pte(*sptep)) {
2175 struct kvm_mmu_page *child;
2178 * For the direct sp, if the guest pte's dirty bit
2179 * changed form clean to dirty, it will corrupt the
2180 * sp's access: allow writable in the read-only sp,
2181 * so we should update the spte at this point to get
2182 * a new sp with the correct access.
2184 child = to_shadow_page(*sptep & PT64_BASE_ADDR_MASK);
2185 if (child->role.access == direct_access)
2188 drop_parent_pte(child, sptep);
2189 kvm_flush_remote_tlbs_with_address(vcpu->kvm, child->gfn, 1);
2193 /* Returns the number of zapped non-leaf child shadow pages. */
2194 static int mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp,
2195 u64 *spte, struct list_head *invalid_list)
2198 struct kvm_mmu_page *child;
2201 if (is_shadow_present_pte(pte)) {
2202 if (is_last_spte(pte, sp->role.level)) {
2203 drop_spte(kvm, spte);
2204 if (is_large_pte(pte))
2207 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2208 drop_parent_pte(child, spte);
2211 * Recursively zap nested TDP SPs, parentless SPs are
2212 * unlikely to be used again in the near future. This
2213 * avoids retaining a large number of stale nested SPs.
2215 if (tdp_enabled && invalid_list &&
2216 child->role.guest_mode && !child->parent_ptes.val)
2217 return kvm_mmu_prepare_zap_page(kvm, child,
2220 } else if (is_mmio_spte(pte)) {
2221 mmu_spte_clear_no_track(spte);
2226 static int kvm_mmu_page_unlink_children(struct kvm *kvm,
2227 struct kvm_mmu_page *sp,
2228 struct list_head *invalid_list)
2233 for (i = 0; i < PT64_ENT_PER_PAGE; ++i)
2234 zapped += mmu_page_zap_pte(kvm, sp, sp->spt + i, invalid_list);
2239 static void kvm_mmu_unlink_parents(struct kvm *kvm, struct kvm_mmu_page *sp)
2242 struct rmap_iterator iter;
2244 while ((sptep = rmap_get_first(&sp->parent_ptes, &iter)))
2245 drop_parent_pte(sp, sptep);
2248 static int mmu_zap_unsync_children(struct kvm *kvm,
2249 struct kvm_mmu_page *parent,
2250 struct list_head *invalid_list)
2253 struct mmu_page_path parents;
2254 struct kvm_mmu_pages pages;
2256 if (parent->role.level == PG_LEVEL_4K)
2259 while (mmu_unsync_walk(parent, &pages)) {
2260 struct kvm_mmu_page *sp;
2262 for_each_sp(pages, sp, parents, i) {
2263 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
2264 mmu_pages_clear_parents(&parents);
2272 static bool __kvm_mmu_prepare_zap_page(struct kvm *kvm,
2273 struct kvm_mmu_page *sp,
2274 struct list_head *invalid_list,
2279 trace_kvm_mmu_prepare_zap_page(sp);
2280 ++kvm->stat.mmu_shadow_zapped;
2281 *nr_zapped = mmu_zap_unsync_children(kvm, sp, invalid_list);
2282 *nr_zapped += kvm_mmu_page_unlink_children(kvm, sp, invalid_list);
2283 kvm_mmu_unlink_parents(kvm, sp);
2285 /* Zapping children means active_mmu_pages has become unstable. */
2286 list_unstable = *nr_zapped;
2288 if (!sp->role.invalid && !sp->role.direct)
2289 unaccount_shadowed(kvm, sp);
2292 kvm_unlink_unsync_page(kvm, sp);
2293 if (!sp->root_count) {
2298 * Already invalid pages (previously active roots) are not on
2299 * the active page list. See list_del() in the "else" case of
2302 if (sp->role.invalid)
2303 list_add(&sp->link, invalid_list);
2305 list_move(&sp->link, invalid_list);
2306 kvm_mod_used_mmu_pages(kvm, -1);
2309 * Remove the active root from the active page list, the root
2310 * will be explicitly freed when the root_count hits zero.
2312 list_del(&sp->link);
2315 * Obsolete pages cannot be used on any vCPUs, see the comment
2316 * in kvm_mmu_zap_all_fast(). Note, is_obsolete_sp() also
2317 * treats invalid shadow pages as being obsolete.
2319 if (!is_obsolete_sp(kvm, sp))
2320 kvm_reload_remote_mmus(kvm);
2323 if (sp->lpage_disallowed)
2324 unaccount_huge_nx_page(kvm, sp);
2326 sp->role.invalid = 1;
2327 return list_unstable;
2330 static bool kvm_mmu_prepare_zap_page(struct kvm *kvm, struct kvm_mmu_page *sp,
2331 struct list_head *invalid_list)
2335 __kvm_mmu_prepare_zap_page(kvm, sp, invalid_list, &nr_zapped);
2339 static void kvm_mmu_commit_zap_page(struct kvm *kvm,
2340 struct list_head *invalid_list)
2342 struct kvm_mmu_page *sp, *nsp;
2344 if (list_empty(invalid_list))
2348 * We need to make sure everyone sees our modifications to
2349 * the page tables and see changes to vcpu->mode here. The barrier
2350 * in the kvm_flush_remote_tlbs() achieves this. This pairs
2351 * with vcpu_enter_guest and walk_shadow_page_lockless_begin/end.
2353 * In addition, kvm_flush_remote_tlbs waits for all vcpus to exit
2354 * guest mode and/or lockless shadow page table walks.
2356 kvm_flush_remote_tlbs(kvm);
2358 list_for_each_entry_safe(sp, nsp, invalid_list, link) {
2359 WARN_ON(!sp->role.invalid || sp->root_count);
2360 kvm_mmu_free_page(sp);
2364 static unsigned long kvm_mmu_zap_oldest_mmu_pages(struct kvm *kvm,
2365 unsigned long nr_to_zap)
2367 unsigned long total_zapped = 0;
2368 struct kvm_mmu_page *sp, *tmp;
2369 LIST_HEAD(invalid_list);
2373 if (list_empty(&kvm->arch.active_mmu_pages))
2377 list_for_each_entry_safe_reverse(sp, tmp, &kvm->arch.active_mmu_pages, link) {
2379 * Don't zap active root pages, the page itself can't be freed
2380 * and zapping it will just force vCPUs to realloc and reload.
2385 unstable = __kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list,
2387 total_zapped += nr_zapped;
2388 if (total_zapped >= nr_to_zap)
2395 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2397 kvm->stat.mmu_recycled += total_zapped;
2398 return total_zapped;
2401 static inline unsigned long kvm_mmu_available_pages(struct kvm *kvm)
2403 if (kvm->arch.n_max_mmu_pages > kvm->arch.n_used_mmu_pages)
2404 return kvm->arch.n_max_mmu_pages -
2405 kvm->arch.n_used_mmu_pages;
2410 static int make_mmu_pages_available(struct kvm_vcpu *vcpu)
2412 unsigned long avail = kvm_mmu_available_pages(vcpu->kvm);
2414 if (likely(avail >= KVM_MIN_FREE_MMU_PAGES))
2417 kvm_mmu_zap_oldest_mmu_pages(vcpu->kvm, KVM_REFILL_PAGES - avail);
2420 * Note, this check is intentionally soft, it only guarantees that one
2421 * page is available, while the caller may end up allocating as many as
2422 * four pages, e.g. for PAE roots or for 5-level paging. Temporarily
2423 * exceeding the (arbitrary by default) limit will not harm the host,
2424 * being too agressive may unnecessarily kill the guest, and getting an
2425 * exact count is far more trouble than it's worth, especially in the
2428 if (!kvm_mmu_available_pages(vcpu->kvm))
2434 * Changing the number of mmu pages allocated to the vm
2435 * Note: if goal_nr_mmu_pages is too small, you will get dead lock
2437 void kvm_mmu_change_mmu_pages(struct kvm *kvm, unsigned long goal_nr_mmu_pages)
2439 write_lock(&kvm->mmu_lock);
2441 if (kvm->arch.n_used_mmu_pages > goal_nr_mmu_pages) {
2442 kvm_mmu_zap_oldest_mmu_pages(kvm, kvm->arch.n_used_mmu_pages -
2445 goal_nr_mmu_pages = kvm->arch.n_used_mmu_pages;
2448 kvm->arch.n_max_mmu_pages = goal_nr_mmu_pages;
2450 write_unlock(&kvm->mmu_lock);
2453 int kvm_mmu_unprotect_page(struct kvm *kvm, gfn_t gfn)
2455 struct kvm_mmu_page *sp;
2456 LIST_HEAD(invalid_list);
2459 pgprintk("%s: looking for gfn %llx\n", __func__, gfn);
2461 write_lock(&kvm->mmu_lock);
2462 for_each_gfn_indirect_valid_sp(kvm, sp, gfn) {
2463 pgprintk("%s: gfn %llx role %x\n", __func__, gfn,
2466 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
2468 kvm_mmu_commit_zap_page(kvm, &invalid_list);
2469 write_unlock(&kvm->mmu_lock);
2474 static int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva)
2479 if (vcpu->arch.mmu->direct_map)
2482 gpa = kvm_mmu_gva_to_gpa_read(vcpu, gva, NULL);
2484 r = kvm_mmu_unprotect_page(vcpu->kvm, gpa >> PAGE_SHIFT);
2489 static void kvm_unsync_page(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp)
2491 trace_kvm_mmu_unsync_page(sp);
2492 ++vcpu->kvm->stat.mmu_unsync;
2495 kvm_mmu_mark_parents_unsync(sp);
2499 * Attempt to unsync any shadow pages that can be reached by the specified gfn,
2500 * KVM is creating a writable mapping for said gfn. Returns 0 if all pages
2501 * were marked unsync (or if there is no shadow page), -EPERM if the SPTE must
2502 * be write-protected.
2504 int mmu_try_to_unsync_pages(struct kvm_vcpu *vcpu, gfn_t gfn, bool can_unsync)
2506 struct kvm_mmu_page *sp;
2509 * Force write-protection if the page is being tracked. Note, the page
2510 * track machinery is used to write-protect upper-level shadow pages,
2511 * i.e. this guards the role.level == 4K assertion below!
2513 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
2517 * The page is not write-tracked, mark existing shadow pages unsync
2518 * unless KVM is synchronizing an unsync SP (can_unsync = false). In
2519 * that case, KVM must complete emulation of the guest TLB flush before
2520 * allowing shadow pages to become unsync (writable by the guest).
2522 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
2529 WARN_ON(sp->role.level != PG_LEVEL_4K);
2530 kvm_unsync_page(vcpu, sp);
2534 * We need to ensure that the marking of unsync pages is visible
2535 * before the SPTE is updated to allow writes because
2536 * kvm_mmu_sync_roots() checks the unsync flags without holding
2537 * the MMU lock and so can race with this. If the SPTE was updated
2538 * before the page had been marked as unsync-ed, something like the
2539 * following could happen:
2542 * ---------------------------------------------------------------------
2543 * 1.2 Host updates SPTE
2545 * 2.1 Guest writes a GPTE for GVA X.
2546 * (GPTE being in the guest page table shadowed
2547 * by the SP from CPU 1.)
2548 * This reads SPTE during the page table walk.
2549 * Since SPTE.W is read as 1, there is no
2552 * 2.2 Guest issues TLB flush.
2553 * That causes a VM Exit.
2555 * 2.3 Walking of unsync pages sees sp->unsync is
2556 * false and skips the page.
2558 * 2.4 Guest accesses GVA X.
2559 * Since the mapping in the SP was not updated,
2560 * so the old mapping for GVA X incorrectly
2564 * (sp->unsync = true)
2566 * The write barrier below ensures that 1.1 happens before 1.2 and thus
2567 * the situation in 2.4 does not arise. The implicit barrier in 2.2
2568 * pairs with this write barrier.
2575 static int set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2576 unsigned int pte_access, int level,
2577 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2578 bool can_unsync, bool host_writable)
2581 struct kvm_mmu_page *sp;
2584 sp = sptep_to_sp(sptep);
2586 ret = make_spte(vcpu, pte_access, level, gfn, pfn, *sptep, speculative,
2587 can_unsync, host_writable, sp_ad_disabled(sp), &spte);
2589 if (spte & PT_WRITABLE_MASK)
2590 kvm_vcpu_mark_page_dirty(vcpu, gfn);
2593 ret |= SET_SPTE_SPURIOUS;
2594 else if (mmu_spte_update(sptep, spte))
2595 ret |= SET_SPTE_NEED_REMOTE_TLB_FLUSH;
2599 static int mmu_set_spte(struct kvm_vcpu *vcpu, u64 *sptep,
2600 unsigned int pte_access, bool write_fault, int level,
2601 gfn_t gfn, kvm_pfn_t pfn, bool speculative,
2604 int was_rmapped = 0;
2607 int ret = RET_PF_FIXED;
2610 pgprintk("%s: spte %llx write_fault %d gfn %llx\n", __func__,
2611 *sptep, write_fault, gfn);
2613 if (unlikely(is_noslot_pfn(pfn))) {
2614 mark_mmio_spte(vcpu, sptep, gfn, pte_access);
2615 return RET_PF_EMULATE;
2618 if (is_shadow_present_pte(*sptep)) {
2620 * If we overwrite a PTE page pointer with a 2MB PMD, unlink
2621 * the parent of the now unreachable PTE.
2623 if (level > PG_LEVEL_4K && !is_large_pte(*sptep)) {
2624 struct kvm_mmu_page *child;
2627 child = to_shadow_page(pte & PT64_BASE_ADDR_MASK);
2628 drop_parent_pte(child, sptep);
2630 } else if (pfn != spte_to_pfn(*sptep)) {
2631 pgprintk("hfn old %llx new %llx\n",
2632 spte_to_pfn(*sptep), pfn);
2633 drop_spte(vcpu->kvm, sptep);
2639 set_spte_ret = set_spte(vcpu, sptep, pte_access, level, gfn, pfn,
2640 speculative, true, host_writable);
2641 if (set_spte_ret & SET_SPTE_WRITE_PROTECTED_PT) {
2643 ret = RET_PF_EMULATE;
2644 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
2647 if (set_spte_ret & SET_SPTE_NEED_REMOTE_TLB_FLUSH || flush)
2648 kvm_flush_remote_tlbs_with_address(vcpu->kvm, gfn,
2649 KVM_PAGES_PER_HPAGE(level));
2652 * The fault is fully spurious if and only if the new SPTE and old SPTE
2653 * are identical, and emulation is not required.
2655 if ((set_spte_ret & SET_SPTE_SPURIOUS) && ret == RET_PF_FIXED) {
2656 WARN_ON_ONCE(!was_rmapped);
2657 return RET_PF_SPURIOUS;
2660 pgprintk("%s: setting spte %llx\n", __func__, *sptep);
2661 trace_kvm_mmu_set_spte(level, gfn, sptep);
2662 if (!was_rmapped && is_large_pte(*sptep))
2663 ++vcpu->kvm->stat.lpages;
2665 if (is_shadow_present_pte(*sptep)) {
2667 rmap_count = rmap_add(vcpu, sptep, gfn);
2668 if (rmap_count > RMAP_RECYCLE_THRESHOLD)
2669 rmap_recycle(vcpu, sptep, gfn);
2676 static kvm_pfn_t pte_prefetch_gfn_to_pfn(struct kvm_vcpu *vcpu, gfn_t gfn,
2679 struct kvm_memory_slot *slot;
2681 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, no_dirty_log);
2683 return KVM_PFN_ERR_FAULT;
2685 return gfn_to_pfn_memslot_atomic(slot, gfn);
2688 static int direct_pte_prefetch_many(struct kvm_vcpu *vcpu,
2689 struct kvm_mmu_page *sp,
2690 u64 *start, u64 *end)
2692 struct page *pages[PTE_PREFETCH_NUM];
2693 struct kvm_memory_slot *slot;
2694 unsigned int access = sp->role.access;
2698 gfn = kvm_mmu_page_get_gfn(sp, start - sp->spt);
2699 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, access & ACC_WRITE_MASK);
2703 ret = gfn_to_page_many_atomic(slot, gfn, pages, end - start);
2707 for (i = 0; i < ret; i++, gfn++, start++) {
2708 mmu_set_spte(vcpu, start, access, false, sp->role.level, gfn,
2709 page_to_pfn(pages[i]), true, true);
2716 static void __direct_pte_prefetch(struct kvm_vcpu *vcpu,
2717 struct kvm_mmu_page *sp, u64 *sptep)
2719 u64 *spte, *start = NULL;
2722 WARN_ON(!sp->role.direct);
2724 i = (sptep - sp->spt) & ~(PTE_PREFETCH_NUM - 1);
2727 for (i = 0; i < PTE_PREFETCH_NUM; i++, spte++) {
2728 if (is_shadow_present_pte(*spte) || spte == sptep) {
2731 if (direct_pte_prefetch_many(vcpu, sp, start, spte) < 0)
2739 static void direct_pte_prefetch(struct kvm_vcpu *vcpu, u64 *sptep)
2741 struct kvm_mmu_page *sp;
2743 sp = sptep_to_sp(sptep);
2746 * Without accessed bits, there's no way to distinguish between
2747 * actually accessed translations and prefetched, so disable pte
2748 * prefetch if accessed bits aren't available.
2750 if (sp_ad_disabled(sp))
2753 if (sp->role.level > PG_LEVEL_4K)
2757 * If addresses are being invalidated, skip prefetching to avoid
2758 * accidentally prefetching those addresses.
2760 if (unlikely(vcpu->kvm->mmu_notifier_count))
2763 __direct_pte_prefetch(vcpu, sp, sptep);
2766 static int host_pfn_mapping_level(struct kvm *kvm, gfn_t gfn, kvm_pfn_t pfn,
2767 const struct kvm_memory_slot *slot)
2773 if (!PageCompound(pfn_to_page(pfn)) && !kvm_is_zone_device_pfn(pfn))
2777 * Note, using the already-retrieved memslot and __gfn_to_hva_memslot()
2778 * is not solely for performance, it's also necessary to avoid the
2779 * "writable" check in __gfn_to_hva_many(), which will always fail on
2780 * read-only memslots due to gfn_to_hva() assuming writes. Earlier
2781 * page fault steps have already verified the guest isn't writing a
2782 * read-only memslot.
2784 hva = __gfn_to_hva_memslot(slot, gfn);
2786 pte = lookup_address_in_mm(kvm->mm, hva, &level);
2793 int kvm_mmu_max_mapping_level(struct kvm *kvm,
2794 const struct kvm_memory_slot *slot, gfn_t gfn,
2795 kvm_pfn_t pfn, int max_level)
2797 struct kvm_lpage_info *linfo;
2799 max_level = min(max_level, max_huge_page_level);
2800 for ( ; max_level > PG_LEVEL_4K; max_level--) {
2801 linfo = lpage_info_slot(gfn, slot, max_level);
2802 if (!linfo->disallow_lpage)
2806 if (max_level == PG_LEVEL_4K)
2809 return host_pfn_mapping_level(kvm, gfn, pfn, slot);
2812 int kvm_mmu_hugepage_adjust(struct kvm_vcpu *vcpu, gfn_t gfn,
2813 int max_level, kvm_pfn_t *pfnp,
2814 bool huge_page_disallowed, int *req_level)
2816 struct kvm_memory_slot *slot;
2817 kvm_pfn_t pfn = *pfnp;
2821 *req_level = PG_LEVEL_4K;
2823 if (unlikely(max_level == PG_LEVEL_4K))
2826 if (is_error_noslot_pfn(pfn) || kvm_is_reserved_pfn(pfn))
2829 slot = gfn_to_memslot_dirty_bitmap(vcpu, gfn, true);
2833 level = kvm_mmu_max_mapping_level(vcpu->kvm, slot, gfn, pfn, max_level);
2834 if (level == PG_LEVEL_4K)
2837 *req_level = level = min(level, max_level);
2840 * Enforce the iTLB multihit workaround after capturing the requested
2841 * level, which will be used to do precise, accurate accounting.
2843 if (huge_page_disallowed)
2847 * mmu_notifier_retry() was successful and mmu_lock is held, so
2848 * the pmd can't be split from under us.
2850 mask = KVM_PAGES_PER_HPAGE(level) - 1;
2851 VM_BUG_ON((gfn & mask) != (pfn & mask));
2852 *pfnp = pfn & ~mask;
2857 void disallowed_hugepage_adjust(u64 spte, gfn_t gfn, int cur_level,
2858 kvm_pfn_t *pfnp, int *goal_levelp)
2860 int level = *goal_levelp;
2862 if (cur_level == level && level > PG_LEVEL_4K &&
2863 is_shadow_present_pte(spte) &&
2864 !is_large_pte(spte)) {
2866 * A small SPTE exists for this pfn, but FNAME(fetch)
2867 * and __direct_map would like to create a large PTE
2868 * instead: just force them to go down another level,
2869 * patching back for them into pfn the next 9 bits of
2872 u64 page_mask = KVM_PAGES_PER_HPAGE(level) -
2873 KVM_PAGES_PER_HPAGE(level - 1);
2874 *pfnp |= gfn & page_mask;
2879 static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
2880 int map_writable, int max_level, kvm_pfn_t pfn,
2881 bool prefault, bool is_tdp)
2883 bool nx_huge_page_workaround_enabled = is_nx_huge_page_enabled();
2884 bool write = error_code & PFERR_WRITE_MASK;
2885 bool exec = error_code & PFERR_FETCH_MASK;
2886 bool huge_page_disallowed = exec && nx_huge_page_workaround_enabled;
2887 struct kvm_shadow_walk_iterator it;
2888 struct kvm_mmu_page *sp;
2889 int level, req_level, ret;
2890 gfn_t gfn = gpa >> PAGE_SHIFT;
2891 gfn_t base_gfn = gfn;
2893 level = kvm_mmu_hugepage_adjust(vcpu, gfn, max_level, &pfn,
2894 huge_page_disallowed, &req_level);
2896 trace_kvm_mmu_spte_requested(gpa, level, pfn);
2897 for_each_shadow_entry(vcpu, gpa, it) {
2899 * We cannot overwrite existing page tables with an NX
2900 * large page, as the leaf could be executable.
2902 if (nx_huge_page_workaround_enabled)
2903 disallowed_hugepage_adjust(*it.sptep, gfn, it.level,
2906 base_gfn = gfn & ~(KVM_PAGES_PER_HPAGE(it.level) - 1);
2907 if (it.level == level)
2910 drop_large_spte(vcpu, it.sptep);
2911 if (!is_shadow_present_pte(*it.sptep)) {
2912 sp = kvm_mmu_get_page(vcpu, base_gfn, it.addr,
2913 it.level - 1, true, ACC_ALL);
2915 link_shadow_page(vcpu, it.sptep, sp);
2916 if (is_tdp && huge_page_disallowed &&
2917 req_level >= it.level)
2918 account_huge_nx_page(vcpu->kvm, sp);
2922 ret = mmu_set_spte(vcpu, it.sptep, ACC_ALL,
2923 write, level, base_gfn, pfn, prefault,
2925 if (ret == RET_PF_SPURIOUS)
2928 direct_pte_prefetch(vcpu, it.sptep);
2929 ++vcpu->stat.pf_fixed;
2933 static void kvm_send_hwpoison_signal(unsigned long address, struct task_struct *tsk)
2935 send_sig_mceerr(BUS_MCEERR_AR, (void __user *)address, PAGE_SHIFT, tsk);
2938 static int kvm_handle_bad_page(struct kvm_vcpu *vcpu, gfn_t gfn, kvm_pfn_t pfn)
2941 * Do not cache the mmio info caused by writing the readonly gfn
2942 * into the spte otherwise read access on readonly gfn also can
2943 * caused mmio page fault and treat it as mmio access.
2945 if (pfn == KVM_PFN_ERR_RO_FAULT)
2946 return RET_PF_EMULATE;
2948 if (pfn == KVM_PFN_ERR_HWPOISON) {
2949 kvm_send_hwpoison_signal(kvm_vcpu_gfn_to_hva(vcpu, gfn), current);
2950 return RET_PF_RETRY;
2956 static bool handle_abnormal_pfn(struct kvm_vcpu *vcpu, gva_t gva, gfn_t gfn,
2957 kvm_pfn_t pfn, unsigned int access,
2960 /* The pfn is invalid, report the error! */
2961 if (unlikely(is_error_pfn(pfn))) {
2962 *ret_val = kvm_handle_bad_page(vcpu, gfn, pfn);
2966 if (unlikely(is_noslot_pfn(pfn))) {
2967 vcpu_cache_mmio_info(vcpu, gva, gfn,
2968 access & shadow_mmio_access_mask);
2970 * If MMIO caching is disabled, emulate immediately without
2971 * touching the shadow page tables as attempting to install an
2972 * MMIO SPTE will just be an expensive nop.
2974 if (unlikely(!shadow_mmio_value)) {
2975 *ret_val = RET_PF_EMULATE;
2983 static bool page_fault_can_be_fast(u32 error_code)
2986 * Do not fix the mmio spte with invalid generation number which
2987 * need to be updated by slow page fault path.
2989 if (unlikely(error_code & PFERR_RSVD_MASK))
2992 /* See if the page fault is due to an NX violation */
2993 if (unlikely(((error_code & (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))
2994 == (PFERR_FETCH_MASK | PFERR_PRESENT_MASK))))
2998 * #PF can be fast if:
2999 * 1. The shadow page table entry is not present, which could mean that
3000 * the fault is potentially caused by access tracking (if enabled).
3001 * 2. The shadow page table entry is present and the fault
3002 * is caused by write-protect, that means we just need change the W
3003 * bit of the spte which can be done out of mmu-lock.
3005 * However, if access tracking is disabled we know that a non-present
3006 * page must be a genuine page fault where we have to create a new SPTE.
3007 * So, if access tracking is disabled, we return true only for write
3008 * accesses to a present page.
3011 return shadow_acc_track_mask != 0 ||
3012 ((error_code & (PFERR_WRITE_MASK | PFERR_PRESENT_MASK))
3013 == (PFERR_WRITE_MASK | PFERR_PRESENT_MASK));
3017 * Returns true if the SPTE was fixed successfully. Otherwise,
3018 * someone else modified the SPTE from its original value.
3021 fast_pf_fix_direct_spte(struct kvm_vcpu *vcpu, struct kvm_mmu_page *sp,
3022 u64 *sptep, u64 old_spte, u64 new_spte)
3026 WARN_ON(!sp->role.direct);
3029 * Theoretically we could also set dirty bit (and flush TLB) here in
3030 * order to eliminate unnecessary PML logging. See comments in
3031 * set_spte. But fast_page_fault is very unlikely to happen with PML
3032 * enabled, so we do not do this. This might result in the same GPA
3033 * to be logged in PML buffer again when the write really happens, and
3034 * eventually to be called by mark_page_dirty twice. But it's also no
3035 * harm. This also avoids the TLB flush needed after setting dirty bit
3036 * so non-PML cases won't be impacted.
3038 * Compare with set_spte where instead shadow_dirty_mask is set.
3040 if (cmpxchg64(sptep, old_spte, new_spte) != old_spte)
3043 if (is_writable_pte(new_spte) && !is_writable_pte(old_spte)) {
3045 * The gfn of direct spte is stable since it is
3046 * calculated by sp->gfn.
3048 gfn = kvm_mmu_page_get_gfn(sp, sptep - sp->spt);
3049 kvm_vcpu_mark_page_dirty(vcpu, gfn);
3055 static bool is_access_allowed(u32 fault_err_code, u64 spte)
3057 if (fault_err_code & PFERR_FETCH_MASK)
3058 return is_executable_pte(spte);
3060 if (fault_err_code & PFERR_WRITE_MASK)
3061 return is_writable_pte(spte);
3063 /* Fault was on Read access */
3064 return spte & PT_PRESENT_MASK;
3068 * Returns one of RET_PF_INVALID, RET_PF_FIXED or RET_PF_SPURIOUS.
3070 static int fast_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3073 struct kvm_shadow_walk_iterator iterator;
3074 struct kvm_mmu_page *sp;
3075 int ret = RET_PF_INVALID;
3077 uint retry_count = 0;
3079 if (!page_fault_can_be_fast(error_code))
3082 walk_shadow_page_lockless_begin(vcpu);
3087 for_each_shadow_entry_lockless(vcpu, cr2_or_gpa, iterator, spte)
3088 if (!is_shadow_present_pte(spte))
3091 if (!is_shadow_present_pte(spte))
3094 sp = sptep_to_sp(iterator.sptep);
3095 if (!is_last_spte(spte, sp->role.level))
3099 * Check whether the memory access that caused the fault would
3100 * still cause it if it were to be performed right now. If not,
3101 * then this is a spurious fault caused by TLB lazily flushed,
3102 * or some other CPU has already fixed the PTE after the
3103 * current CPU took the fault.
3105 * Need not check the access of upper level table entries since
3106 * they are always ACC_ALL.
3108 if (is_access_allowed(error_code, spte)) {
3109 ret = RET_PF_SPURIOUS;
3115 if (is_access_track_spte(spte))
3116 new_spte = restore_acc_track_spte(new_spte);
3119 * Currently, to simplify the code, write-protection can
3120 * be removed in the fast path only if the SPTE was
3121 * write-protected for dirty-logging or access tracking.
3123 if ((error_code & PFERR_WRITE_MASK) &&
3124 spte_can_locklessly_be_made_writable(spte)) {
3125 new_spte |= PT_WRITABLE_MASK;
3128 * Do not fix write-permission on the large spte. Since
3129 * we only dirty the first page into the dirty-bitmap in
3130 * fast_pf_fix_direct_spte(), other pages are missed
3131 * if its slot has dirty logging enabled.
3133 * Instead, we let the slow page fault path create a
3134 * normal spte to fix the access.
3136 * See the comments in kvm_arch_commit_memory_region().
3138 if (sp->role.level > PG_LEVEL_4K)
3142 /* Verify that the fault can be handled in the fast path */
3143 if (new_spte == spte ||
3144 !is_access_allowed(error_code, new_spte))
3148 * Currently, fast page fault only works for direct mapping
3149 * since the gfn is not stable for indirect shadow page. See
3150 * Documentation/virt/kvm/locking.rst to get more detail.
3152 if (fast_pf_fix_direct_spte(vcpu, sp, iterator.sptep, spte,
3158 if (++retry_count > 4) {
3159 printk_once(KERN_WARNING
3160 "kvm: Fast #PF retrying more than 4 times.\n");
3166 trace_fast_page_fault(vcpu, cr2_or_gpa, error_code, iterator.sptep,
3168 walk_shadow_page_lockless_end(vcpu);
3173 static void mmu_free_root_page(struct kvm *kvm, hpa_t *root_hpa,
3174 struct list_head *invalid_list)
3176 struct kvm_mmu_page *sp;
3178 if (!VALID_PAGE(*root_hpa))
3181 sp = to_shadow_page(*root_hpa & PT64_BASE_ADDR_MASK);
3183 if (is_tdp_mmu_page(sp))
3184 kvm_tdp_mmu_put_root(kvm, sp, false);
3185 else if (!--sp->root_count && sp->role.invalid)
3186 kvm_mmu_prepare_zap_page(kvm, sp, invalid_list);
3188 *root_hpa = INVALID_PAGE;
3191 /* roots_to_free must be some combination of the KVM_MMU_ROOT_* flags */
3192 void kvm_mmu_free_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
3193 ulong roots_to_free)
3195 struct kvm *kvm = vcpu->kvm;
3197 LIST_HEAD(invalid_list);
3198 bool free_active_root = roots_to_free & KVM_MMU_ROOT_CURRENT;
3200 BUILD_BUG_ON(KVM_MMU_NUM_PREV_ROOTS >= BITS_PER_LONG);
3202 /* Before acquiring the MMU lock, see if we need to do any real work. */
3203 if (!(free_active_root && VALID_PAGE(mmu->root_hpa))) {
3204 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3205 if ((roots_to_free & KVM_MMU_ROOT_PREVIOUS(i)) &&
3206 VALID_PAGE(mmu->prev_roots[i].hpa))
3209 if (i == KVM_MMU_NUM_PREV_ROOTS)
3213 write_lock(&kvm->mmu_lock);
3215 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
3216 if (roots_to_free & KVM_MMU_ROOT_PREVIOUS(i))
3217 mmu_free_root_page(kvm, &mmu->prev_roots[i].hpa,
3220 if (free_active_root) {
3221 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3222 (mmu->root_level >= PT64_ROOT_4LEVEL || mmu->direct_map)) {
3223 mmu_free_root_page(kvm, &mmu->root_hpa, &invalid_list);
3224 } else if (mmu->pae_root) {
3225 for (i = 0; i < 4; ++i) {
3226 if (!IS_VALID_PAE_ROOT(mmu->pae_root[i]))
3229 mmu_free_root_page(kvm, &mmu->pae_root[i],
3231 mmu->pae_root[i] = INVALID_PAE_ROOT;
3234 mmu->root_hpa = INVALID_PAGE;
3238 kvm_mmu_commit_zap_page(kvm, &invalid_list);
3239 write_unlock(&kvm->mmu_lock);
3241 EXPORT_SYMBOL_GPL(kvm_mmu_free_roots);
3243 void kvm_mmu_free_guest_mode_roots(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
3245 unsigned long roots_to_free = 0;
3250 * This should not be called while L2 is active, L2 can't invalidate
3251 * _only_ its own roots, e.g. INVVPID unconditionally exits.
3253 WARN_ON_ONCE(mmu->mmu_role.base.guest_mode);
3255 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3256 root_hpa = mmu->prev_roots[i].hpa;
3257 if (!VALID_PAGE(root_hpa))
3260 if (!to_shadow_page(root_hpa) ||
3261 to_shadow_page(root_hpa)->role.guest_mode)
3262 roots_to_free |= KVM_MMU_ROOT_PREVIOUS(i);
3265 kvm_mmu_free_roots(vcpu, mmu, roots_to_free);
3267 EXPORT_SYMBOL_GPL(kvm_mmu_free_guest_mode_roots);
3270 static int mmu_check_root(struct kvm_vcpu *vcpu, gfn_t root_gfn)
3274 if (!kvm_vcpu_is_visible_gfn(vcpu, root_gfn)) {
3275 kvm_make_request(KVM_REQ_TRIPLE_FAULT, vcpu);
3282 static hpa_t mmu_alloc_root(struct kvm_vcpu *vcpu, gfn_t gfn, gva_t gva,
3283 u8 level, bool direct)
3285 struct kvm_mmu_page *sp;
3287 sp = kvm_mmu_get_page(vcpu, gfn, gva, level, direct, ACC_ALL);
3290 return __pa(sp->spt);
3293 static int mmu_alloc_direct_roots(struct kvm_vcpu *vcpu)
3295 struct kvm_mmu *mmu = vcpu->arch.mmu;
3296 u8 shadow_root_level = mmu->shadow_root_level;
3301 write_lock(&vcpu->kvm->mmu_lock);
3302 r = make_mmu_pages_available(vcpu);
3306 if (is_tdp_mmu_enabled(vcpu->kvm)) {
3307 root = kvm_tdp_mmu_get_vcpu_root_hpa(vcpu);
3308 mmu->root_hpa = root;
3309 } else if (shadow_root_level >= PT64_ROOT_4LEVEL) {
3310 root = mmu_alloc_root(vcpu, 0, 0, shadow_root_level, true);
3311 mmu->root_hpa = root;
3312 } else if (shadow_root_level == PT32E_ROOT_LEVEL) {
3313 if (WARN_ON_ONCE(!mmu->pae_root)) {
3318 for (i = 0; i < 4; ++i) {
3319 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3321 root = mmu_alloc_root(vcpu, i << (30 - PAGE_SHIFT),
3322 i << 30, PT32_ROOT_LEVEL, true);
3323 mmu->pae_root[i] = root | PT_PRESENT_MASK |
3326 mmu->root_hpa = __pa(mmu->pae_root);
3328 WARN_ONCE(1, "Bad TDP root level = %d\n", shadow_root_level);
3333 /* root_pgd is ignored for direct MMUs. */
3336 write_unlock(&vcpu->kvm->mmu_lock);
3340 static int mmu_alloc_shadow_roots(struct kvm_vcpu *vcpu)
3342 struct kvm_mmu *mmu = vcpu->arch.mmu;
3343 u64 pdptrs[4], pm_mask;
3344 gfn_t root_gfn, root_pgd;
3349 root_pgd = mmu->get_guest_pgd(vcpu);
3350 root_gfn = root_pgd >> PAGE_SHIFT;
3352 if (mmu_check_root(vcpu, root_gfn))
3356 * On SVM, reading PDPTRs might access guest memory, which might fault
3357 * and thus might sleep. Grab the PDPTRs before acquiring mmu_lock.
3359 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3360 for (i = 0; i < 4; ++i) {
3361 pdptrs[i] = mmu->get_pdptr(vcpu, i);
3362 if (!(pdptrs[i] & PT_PRESENT_MASK))
3365 if (mmu_check_root(vcpu, pdptrs[i] >> PAGE_SHIFT))
3370 r = alloc_all_memslots_rmaps(vcpu->kvm);
3374 write_lock(&vcpu->kvm->mmu_lock);
3375 r = make_mmu_pages_available(vcpu);
3380 * Do we shadow a long mode page table? If so we need to
3381 * write-protect the guests page table root.
3383 if (mmu->root_level >= PT64_ROOT_4LEVEL) {
3384 root = mmu_alloc_root(vcpu, root_gfn, 0,
3385 mmu->shadow_root_level, false);
3386 mmu->root_hpa = root;
3390 if (WARN_ON_ONCE(!mmu->pae_root)) {
3396 * We shadow a 32 bit page table. This may be a legacy 2-level
3397 * or a PAE 3-level page table. In either case we need to be aware that
3398 * the shadow page table may be a PAE or a long mode page table.
3400 pm_mask = PT_PRESENT_MASK | shadow_me_mask;
3401 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL) {
3402 pm_mask |= PT_ACCESSED_MASK | PT_WRITABLE_MASK | PT_USER_MASK;
3404 if (WARN_ON_ONCE(!mmu->pml4_root)) {
3409 mmu->pml4_root[0] = __pa(mmu->pae_root) | pm_mask;
3412 for (i = 0; i < 4; ++i) {
3413 WARN_ON_ONCE(IS_VALID_PAE_ROOT(mmu->pae_root[i]));
3415 if (mmu->root_level == PT32E_ROOT_LEVEL) {
3416 if (!(pdptrs[i] & PT_PRESENT_MASK)) {
3417 mmu->pae_root[i] = INVALID_PAE_ROOT;
3420 root_gfn = pdptrs[i] >> PAGE_SHIFT;
3423 root = mmu_alloc_root(vcpu, root_gfn, i << 30,
3424 PT32_ROOT_LEVEL, false);
3425 mmu->pae_root[i] = root | pm_mask;
3428 if (mmu->shadow_root_level == PT64_ROOT_4LEVEL)
3429 mmu->root_hpa = __pa(mmu->pml4_root);
3431 mmu->root_hpa = __pa(mmu->pae_root);
3434 mmu->root_pgd = root_pgd;
3436 write_unlock(&vcpu->kvm->mmu_lock);
3441 static int mmu_alloc_special_roots(struct kvm_vcpu *vcpu)
3443 struct kvm_mmu *mmu = vcpu->arch.mmu;
3444 u64 *pml4_root, *pae_root;
3447 * When shadowing 32-bit or PAE NPT with 64-bit NPT, the PML4 and PDP
3448 * tables are allocated and initialized at root creation as there is no
3449 * equivalent level in the guest's NPT to shadow. Allocate the tables
3450 * on demand, as running a 32-bit L1 VMM on 64-bit KVM is very rare.
3452 if (mmu->direct_map || mmu->root_level >= PT64_ROOT_4LEVEL ||
3453 mmu->shadow_root_level < PT64_ROOT_4LEVEL)
3457 * This mess only works with 4-level paging and needs to be updated to
3458 * work with 5-level paging.
3460 if (WARN_ON_ONCE(mmu->shadow_root_level != PT64_ROOT_4LEVEL))
3463 if (mmu->pae_root && mmu->pml4_root)
3467 * The special roots should always be allocated in concert. Yell and
3468 * bail if KVM ends up in a state where only one of the roots is valid.
3470 if (WARN_ON_ONCE(!tdp_enabled || mmu->pae_root || mmu->pml4_root))
3474 * Unlike 32-bit NPT, the PDP table doesn't need to be in low mem, and
3475 * doesn't need to be decrypted.
3477 pae_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3481 pml4_root = (void *)get_zeroed_page(GFP_KERNEL_ACCOUNT);
3483 free_page((unsigned long)pae_root);
3487 mmu->pae_root = pae_root;
3488 mmu->pml4_root = pml4_root;
3493 void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu)
3496 struct kvm_mmu_page *sp;
3498 if (vcpu->arch.mmu->direct_map)
3501 if (!VALID_PAGE(vcpu->arch.mmu->root_hpa))
3504 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
3506 if (vcpu->arch.mmu->root_level >= PT64_ROOT_4LEVEL) {
3507 hpa_t root = vcpu->arch.mmu->root_hpa;
3508 sp = to_shadow_page(root);
3511 * Even if another CPU was marking the SP as unsync-ed
3512 * simultaneously, any guest page table changes are not
3513 * guaranteed to be visible anyway until this VCPU issues a TLB
3514 * flush strictly after those changes are made. We only need to
3515 * ensure that the other CPU sets these flags before any actual
3516 * changes to the page tables are made. The comments in
3517 * mmu_try_to_unsync_pages() describe what could go wrong if
3518 * this requirement isn't satisfied.
3520 if (!smp_load_acquire(&sp->unsync) &&
3521 !smp_load_acquire(&sp->unsync_children))
3524 write_lock(&vcpu->kvm->mmu_lock);
3525 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3527 mmu_sync_children(vcpu, sp);
3529 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3530 write_unlock(&vcpu->kvm->mmu_lock);
3534 write_lock(&vcpu->kvm->mmu_lock);
3535 kvm_mmu_audit(vcpu, AUDIT_PRE_SYNC);
3537 for (i = 0; i < 4; ++i) {
3538 hpa_t root = vcpu->arch.mmu->pae_root[i];
3540 if (IS_VALID_PAE_ROOT(root)) {
3541 root &= PT64_BASE_ADDR_MASK;
3542 sp = to_shadow_page(root);
3543 mmu_sync_children(vcpu, sp);
3547 kvm_mmu_audit(vcpu, AUDIT_POST_SYNC);
3548 write_unlock(&vcpu->kvm->mmu_lock);
3551 static gpa_t nonpaging_gva_to_gpa(struct kvm_vcpu *vcpu, gpa_t vaddr,
3552 u32 access, struct x86_exception *exception)
3555 exception->error_code = 0;
3559 static gpa_t nonpaging_gva_to_gpa_nested(struct kvm_vcpu *vcpu, gpa_t vaddr,
3561 struct x86_exception *exception)
3564 exception->error_code = 0;
3565 return vcpu->arch.nested_mmu.translate_gpa(vcpu, vaddr, access, exception);
3569 __is_rsvd_bits_set(struct rsvd_bits_validate *rsvd_check, u64 pte, int level)
3571 int bit7 = (pte >> 7) & 1;
3573 return pte & rsvd_check->rsvd_bits_mask[bit7][level-1];
3576 static bool __is_bad_mt_xwr(struct rsvd_bits_validate *rsvd_check, u64 pte)
3578 return rsvd_check->bad_mt_xwr & BIT_ULL(pte & 0x3f);
3581 static bool mmio_info_in_cache(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3584 * A nested guest cannot use the MMIO cache if it is using nested
3585 * page tables, because cr2 is a nGPA while the cache stores GPAs.
3587 if (mmu_is_nested(vcpu))
3591 return vcpu_match_mmio_gpa(vcpu, addr);
3593 return vcpu_match_mmio_gva(vcpu, addr);
3597 * Return the level of the lowest level SPTE added to sptes.
3598 * That SPTE may be non-present.
3600 static int get_walk(struct kvm_vcpu *vcpu, u64 addr, u64 *sptes, int *root_level)
3602 struct kvm_shadow_walk_iterator iterator;
3606 walk_shadow_page_lockless_begin(vcpu);
3608 for (shadow_walk_init(&iterator, vcpu, addr),
3609 *root_level = iterator.level;
3610 shadow_walk_okay(&iterator);
3611 __shadow_walk_next(&iterator, spte)) {
3612 leaf = iterator.level;
3613 spte = mmu_spte_get_lockless(iterator.sptep);
3617 if (!is_shadow_present_pte(spte))
3621 walk_shadow_page_lockless_end(vcpu);
3626 /* return true if reserved bit(s) are detected on a valid, non-MMIO SPTE. */
3627 static bool get_mmio_spte(struct kvm_vcpu *vcpu, u64 addr, u64 *sptep)
3629 u64 sptes[PT64_ROOT_MAX_LEVEL + 1];
3630 struct rsvd_bits_validate *rsvd_check;
3631 int root, leaf, level;
3632 bool reserved = false;
3634 if (is_tdp_mmu(vcpu->arch.mmu))
3635 leaf = kvm_tdp_mmu_get_walk(vcpu, addr, sptes, &root);
3637 leaf = get_walk(vcpu, addr, sptes, &root);
3639 if (unlikely(leaf < 0)) {
3644 *sptep = sptes[leaf];
3647 * Skip reserved bits checks on the terminal leaf if it's not a valid
3648 * SPTE. Note, this also (intentionally) skips MMIO SPTEs, which, by
3649 * design, always have reserved bits set. The purpose of the checks is
3650 * to detect reserved bits on non-MMIO SPTEs. i.e. buggy SPTEs.
3652 if (!is_shadow_present_pte(sptes[leaf]))
3655 rsvd_check = &vcpu->arch.mmu->shadow_zero_check;
3657 for (level = root; level >= leaf; level--)
3659 * Use a bitwise-OR instead of a logical-OR to aggregate the
3660 * reserved bit and EPT's invalid memtype/XWR checks to avoid
3661 * adding a Jcc in the loop.
3663 reserved |= __is_bad_mt_xwr(rsvd_check, sptes[level]) |
3664 __is_rsvd_bits_set(rsvd_check, sptes[level], level);
3667 pr_err("%s: reserved bits set on MMU-present spte, addr 0x%llx, hierarchy:\n",
3669 for (level = root; level >= leaf; level--)
3670 pr_err("------ spte = 0x%llx level = %d, rsvd bits = 0x%llx",
3671 sptes[level], level,
3672 rsvd_check->rsvd_bits_mask[(sptes[level] >> 7) & 1][level-1]);
3678 static int handle_mmio_page_fault(struct kvm_vcpu *vcpu, u64 addr, bool direct)
3683 if (mmio_info_in_cache(vcpu, addr, direct))
3684 return RET_PF_EMULATE;
3686 reserved = get_mmio_spte(vcpu, addr, &spte);
3687 if (WARN_ON(reserved))
3690 if (is_mmio_spte(spte)) {
3691 gfn_t gfn = get_mmio_spte_gfn(spte);
3692 unsigned int access = get_mmio_spte_access(spte);
3694 if (!check_mmio_spte(vcpu, spte))
3695 return RET_PF_INVALID;
3700 trace_handle_mmio_page_fault(addr, gfn, access);
3701 vcpu_cache_mmio_info(vcpu, addr, gfn, access);
3702 return RET_PF_EMULATE;
3706 * If the page table is zapped by other cpus, let CPU fault again on
3709 return RET_PF_RETRY;
3712 static bool page_fault_handle_page_track(struct kvm_vcpu *vcpu,
3713 u32 error_code, gfn_t gfn)
3715 if (unlikely(error_code & PFERR_RSVD_MASK))
3718 if (!(error_code & PFERR_PRESENT_MASK) ||
3719 !(error_code & PFERR_WRITE_MASK))
3723 * guest is writing the page which is write tracked which can
3724 * not be fixed by page fault handler.
3726 if (kvm_page_track_is_active(vcpu, gfn, KVM_PAGE_TRACK_WRITE))
3732 static void shadow_page_table_clear_flood(struct kvm_vcpu *vcpu, gva_t addr)
3734 struct kvm_shadow_walk_iterator iterator;
3737 walk_shadow_page_lockless_begin(vcpu);
3738 for_each_shadow_entry_lockless(vcpu, addr, iterator, spte) {
3739 clear_sp_write_flooding_count(iterator.sptep);
3740 if (!is_shadow_present_pte(spte))
3743 walk_shadow_page_lockless_end(vcpu);
3746 static bool kvm_arch_setup_async_pf(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa,
3749 struct kvm_arch_async_pf arch;
3751 arch.token = (vcpu->arch.apf.id++ << 12) | vcpu->vcpu_id;
3753 arch.direct_map = vcpu->arch.mmu->direct_map;
3754 arch.cr3 = vcpu->arch.mmu->get_guest_pgd(vcpu);
3756 return kvm_setup_async_pf(vcpu, cr2_or_gpa,
3757 kvm_vcpu_gfn_to_hva(vcpu, gfn), &arch);
3760 static bool try_async_pf(struct kvm_vcpu *vcpu, bool prefault, gfn_t gfn,
3761 gpa_t cr2_or_gpa, kvm_pfn_t *pfn, hva_t *hva,
3762 bool write, bool *writable)
3764 struct kvm_memory_slot *slot = kvm_vcpu_gfn_to_memslot(vcpu, gfn);
3768 * Retry the page fault if the gfn hit a memslot that is being deleted
3769 * or moved. This ensures any existing SPTEs for the old memslot will
3770 * be zapped before KVM inserts a new MMIO SPTE for the gfn.
3772 if (slot && (slot->flags & KVM_MEMSLOT_INVALID))
3775 /* Don't expose private memslots to L2. */
3776 if (is_guest_mode(vcpu) && !kvm_is_visible_memslot(slot)) {
3777 *pfn = KVM_PFN_NOSLOT;
3783 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, &async,
3784 write, writable, hva);
3786 return false; /* *pfn has correct page already */
3788 if (!prefault && kvm_can_do_async_pf(vcpu)) {
3789 trace_kvm_try_async_get_page(cr2_or_gpa, gfn);
3790 if (kvm_find_async_pf_gfn(vcpu, gfn)) {
3791 trace_kvm_async_pf_doublefault(cr2_or_gpa, gfn);
3792 kvm_make_request(KVM_REQ_APF_HALT, vcpu);
3794 } else if (kvm_arch_setup_async_pf(vcpu, cr2_or_gpa, gfn))
3798 *pfn = __gfn_to_pfn_memslot(slot, gfn, false, NULL,
3799 write, writable, hva);
3803 static int direct_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3804 bool prefault, int max_level, bool is_tdp)
3806 bool is_tdp_mmu_fault = is_tdp_mmu(vcpu->arch.mmu);
3807 bool write = error_code & PFERR_WRITE_MASK;
3810 gfn_t gfn = gpa >> PAGE_SHIFT;
3811 unsigned long mmu_seq;
3816 if (page_fault_handle_page_track(vcpu, error_code, gfn))
3817 return RET_PF_EMULATE;
3819 if (!is_tdp_mmu_fault) {
3820 r = fast_page_fault(vcpu, gpa, error_code);
3821 if (r != RET_PF_INVALID)
3825 r = mmu_topup_memory_caches(vcpu, false);
3829 mmu_seq = vcpu->kvm->mmu_notifier_seq;
3832 if (try_async_pf(vcpu, prefault, gfn, gpa, &pfn, &hva,
3833 write, &map_writable))
3834 return RET_PF_RETRY;
3836 if (handle_abnormal_pfn(vcpu, is_tdp ? 0 : gpa, gfn, pfn, ACC_ALL, &r))
3841 if (is_tdp_mmu_fault)
3842 read_lock(&vcpu->kvm->mmu_lock);
3844 write_lock(&vcpu->kvm->mmu_lock);
3846 if (!is_noslot_pfn(pfn) && mmu_notifier_retry_hva(vcpu->kvm, mmu_seq, hva))
3848 r = make_mmu_pages_available(vcpu);
3852 if (is_tdp_mmu_fault)
3853 r = kvm_tdp_mmu_map(vcpu, gpa, error_code, map_writable, max_level,
3856 r = __direct_map(vcpu, gpa, error_code, map_writable, max_level, pfn,
3860 if (is_tdp_mmu_fault)
3861 read_unlock(&vcpu->kvm->mmu_lock);
3863 write_unlock(&vcpu->kvm->mmu_lock);
3864 kvm_release_pfn_clean(pfn);
3868 static int nonpaging_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa,
3869 u32 error_code, bool prefault)
3871 pgprintk("%s: gva %lx error %x\n", __func__, gpa, error_code);
3873 /* This path builds a PAE pagetable, we can map 2mb pages at maximum. */
3874 return direct_page_fault(vcpu, gpa & PAGE_MASK, error_code, prefault,
3875 PG_LEVEL_2M, false);
3878 int kvm_handle_page_fault(struct kvm_vcpu *vcpu, u64 error_code,
3879 u64 fault_address, char *insn, int insn_len)
3882 u32 flags = vcpu->arch.apf.host_apf_flags;
3884 #ifndef CONFIG_X86_64
3885 /* A 64-bit CR2 should be impossible on 32-bit KVM. */
3886 if (WARN_ON_ONCE(fault_address >> 32))
3890 vcpu->arch.l1tf_flush_l1d = true;
3892 trace_kvm_page_fault(fault_address, error_code);
3894 if (kvm_event_needs_reinjection(vcpu))
3895 kvm_mmu_unprotect_page_virt(vcpu, fault_address);
3896 r = kvm_mmu_page_fault(vcpu, fault_address, error_code, insn,
3898 } else if (flags & KVM_PV_REASON_PAGE_NOT_PRESENT) {
3899 vcpu->arch.apf.host_apf_flags = 0;
3900 local_irq_disable();
3901 kvm_async_pf_task_wait_schedule(fault_address);
3904 WARN_ONCE(1, "Unexpected host async PF flags: %x\n", flags);
3909 EXPORT_SYMBOL_GPL(kvm_handle_page_fault);
3911 int kvm_tdp_page_fault(struct kvm_vcpu *vcpu, gpa_t gpa, u32 error_code,
3916 for (max_level = KVM_MAX_HUGEPAGE_LEVEL;
3917 max_level > PG_LEVEL_4K;
3919 int page_num = KVM_PAGES_PER_HPAGE(max_level);
3920 gfn_t base = (gpa >> PAGE_SHIFT) & ~(page_num - 1);
3922 if (kvm_mtrr_check_gfn_range_consistency(vcpu, base, page_num))
3926 return direct_page_fault(vcpu, gpa, error_code, prefault,
3930 static void nonpaging_init_context(struct kvm_vcpu *vcpu,
3931 struct kvm_mmu *context)
3933 context->page_fault = nonpaging_page_fault;
3934 context->gva_to_gpa = nonpaging_gva_to_gpa;
3935 context->sync_page = nonpaging_sync_page;
3936 context->invlpg = NULL;
3937 context->root_level = 0;
3938 context->direct_map = true;
3939 context->nx = false;
3942 static inline bool is_root_usable(struct kvm_mmu_root_info *root, gpa_t pgd,
3943 union kvm_mmu_page_role role)
3945 return (role.direct || pgd == root->pgd) &&
3946 VALID_PAGE(root->hpa) && to_shadow_page(root->hpa) &&
3947 role.word == to_shadow_page(root->hpa)->role.word;
3951 * Find out if a previously cached root matching the new pgd/role is available.
3952 * The current root is also inserted into the cache.
3953 * If a matching root was found, it is assigned to kvm_mmu->root_hpa and true is
3955 * Otherwise, the LRU root from the cache is assigned to kvm_mmu->root_hpa and
3956 * false is returned. This root should now be freed by the caller.
3958 static bool cached_root_available(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3959 union kvm_mmu_page_role new_role)
3962 struct kvm_mmu_root_info root;
3963 struct kvm_mmu *mmu = vcpu->arch.mmu;
3965 root.pgd = mmu->root_pgd;
3966 root.hpa = mmu->root_hpa;
3968 if (is_root_usable(&root, new_pgd, new_role))
3971 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
3972 swap(root, mmu->prev_roots[i]);
3974 if (is_root_usable(&root, new_pgd, new_role))
3978 mmu->root_hpa = root.hpa;
3979 mmu->root_pgd = root.pgd;
3981 return i < KVM_MMU_NUM_PREV_ROOTS;
3984 static bool fast_pgd_switch(struct kvm_vcpu *vcpu, gpa_t new_pgd,
3985 union kvm_mmu_page_role new_role)
3987 struct kvm_mmu *mmu = vcpu->arch.mmu;
3990 * For now, limit the fast switch to 64-bit hosts+VMs in order to avoid
3991 * having to deal with PDPTEs. We may add support for 32-bit hosts/VMs
3992 * later if necessary.
3994 if (mmu->shadow_root_level >= PT64_ROOT_4LEVEL &&
3995 mmu->root_level >= PT64_ROOT_4LEVEL)
3996 return cached_root_available(vcpu, new_pgd, new_role);
4001 static void __kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd,
4002 union kvm_mmu_page_role new_role)
4004 if (!fast_pgd_switch(vcpu, new_pgd, new_role)) {
4005 kvm_mmu_free_roots(vcpu, vcpu->arch.mmu, KVM_MMU_ROOT_CURRENT);
4010 * It's possible that the cached previous root page is obsolete because
4011 * of a change in the MMU generation number. However, changing the
4012 * generation number is accompanied by KVM_REQ_MMU_RELOAD, which will
4013 * free the root set here and allocate a new one.
4015 kvm_make_request(KVM_REQ_LOAD_MMU_PGD, vcpu);
4017 if (force_flush_and_sync_on_reuse) {
4018 kvm_make_request(KVM_REQ_MMU_SYNC, vcpu);
4019 kvm_make_request(KVM_REQ_TLB_FLUSH_CURRENT, vcpu);
4023 * The last MMIO access's GVA and GPA are cached in the VCPU. When
4024 * switching to a new CR3, that GVA->GPA mapping may no longer be
4025 * valid. So clear any cached MMIO info even when we don't need to sync
4026 * the shadow page tables.
4028 vcpu_clear_mmio_info(vcpu, MMIO_GVA_ANY);
4031 * If this is a direct root page, it doesn't have a write flooding
4032 * count. Otherwise, clear the write flooding count.
4034 if (!new_role.direct)
4035 __clear_sp_write_flooding_count(
4036 to_shadow_page(vcpu->arch.mmu->root_hpa));
4039 void kvm_mmu_new_pgd(struct kvm_vcpu *vcpu, gpa_t new_pgd)
4041 __kvm_mmu_new_pgd(vcpu, new_pgd, kvm_mmu_calc_root_page_role(vcpu));
4043 EXPORT_SYMBOL_GPL(kvm_mmu_new_pgd);
4045 static unsigned long get_cr3(struct kvm_vcpu *vcpu)
4047 return kvm_read_cr3(vcpu);
4050 static bool sync_mmio_spte(struct kvm_vcpu *vcpu, u64 *sptep, gfn_t gfn,
4051 unsigned int access, int *nr_present)
4053 if (unlikely(is_mmio_spte(*sptep))) {
4054 if (gfn != get_mmio_spte_gfn(*sptep)) {
4055 mmu_spte_clear_no_track(sptep);
4060 mark_mmio_spte(vcpu, sptep, gfn, access);
4067 static inline bool is_last_gpte(struct kvm_mmu *mmu,
4068 unsigned level, unsigned gpte)
4071 * The RHS has bit 7 set iff level < mmu->last_nonleaf_level.
4072 * If it is clear, there are no large pages at this level, so clear
4073 * PT_PAGE_SIZE_MASK in gpte if that is the case.
4075 gpte &= level - mmu->last_nonleaf_level;
4078 * PG_LEVEL_4K always terminates. The RHS has bit 7 set
4079 * iff level <= PG_LEVEL_4K, which for our purpose means
4080 * level == PG_LEVEL_4K; set PT_PAGE_SIZE_MASK in gpte then.
4082 gpte |= level - PG_LEVEL_4K - 1;
4084 return gpte & PT_PAGE_SIZE_MASK;
4087 #define PTTYPE_EPT 18 /* arbitrary */
4088 #define PTTYPE PTTYPE_EPT
4089 #include "paging_tmpl.h"
4093 #include "paging_tmpl.h"
4097 #include "paging_tmpl.h"
4101 __reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4102 struct rsvd_bits_validate *rsvd_check,
4103 u64 pa_bits_rsvd, int level, bool nx, bool gbpages,
4106 u64 gbpages_bit_rsvd = 0;
4107 u64 nonleaf_bit8_rsvd = 0;
4110 rsvd_check->bad_mt_xwr = 0;
4113 gbpages_bit_rsvd = rsvd_bits(7, 7);
4115 if (level == PT32E_ROOT_LEVEL)
4116 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 62);
4118 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4120 /* Note, NX doesn't exist in PDPTEs, this is handled below. */
4122 high_bits_rsvd |= rsvd_bits(63, 63);
4125 * Non-leaf PML4Es and PDPEs reserve bit 8 (which would be the G bit for
4126 * leaf entries) on AMD CPUs only.
4129 nonleaf_bit8_rsvd = rsvd_bits(8, 8);
4132 case PT32_ROOT_LEVEL:
4133 /* no rsvd bits for 2 level 4K page table entries */
4134 rsvd_check->rsvd_bits_mask[0][1] = 0;
4135 rsvd_check->rsvd_bits_mask[0][0] = 0;
4136 rsvd_check->rsvd_bits_mask[1][0] =
4137 rsvd_check->rsvd_bits_mask[0][0];
4140 rsvd_check->rsvd_bits_mask[1][1] = 0;
4144 if (is_cpuid_PSE36())
4145 /* 36bits PSE 4MB page */
4146 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(17, 21);
4148 /* 32 bits PSE 4MB page */
4149 rsvd_check->rsvd_bits_mask[1][1] = rsvd_bits(13, 21);
4151 case PT32E_ROOT_LEVEL:
4152 rsvd_check->rsvd_bits_mask[0][2] = rsvd_bits(63, 63) |
4155 rsvd_bits(1, 2); /* PDPTE */
4156 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd; /* PDE */
4157 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd; /* PTE */
4158 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4159 rsvd_bits(13, 20); /* large page */
4160 rsvd_check->rsvd_bits_mask[1][0] =
4161 rsvd_check->rsvd_bits_mask[0][0];
4163 case PT64_ROOT_5LEVEL:
4164 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd |
4167 rsvd_check->rsvd_bits_mask[1][4] =
4168 rsvd_check->rsvd_bits_mask[0][4];
4170 case PT64_ROOT_4LEVEL:
4171 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd |
4174 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd |
4176 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd;
4177 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4178 rsvd_check->rsvd_bits_mask[1][3] =
4179 rsvd_check->rsvd_bits_mask[0][3];
4180 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd |
4183 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd |
4184 rsvd_bits(13, 20); /* large page */
4185 rsvd_check->rsvd_bits_mask[1][0] =
4186 rsvd_check->rsvd_bits_mask[0][0];
4191 static void reset_rsvds_bits_mask(struct kvm_vcpu *vcpu,
4192 struct kvm_mmu *context)
4194 __reset_rsvds_bits_mask(vcpu, &context->guest_rsvd_check,
4195 vcpu->arch.reserved_gpa_bits,
4196 context->root_level, context->nx,
4197 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4199 guest_cpuid_is_amd_or_hygon(vcpu));
4203 __reset_rsvds_bits_mask_ept(struct rsvd_bits_validate *rsvd_check,
4204 u64 pa_bits_rsvd, bool execonly)
4206 u64 high_bits_rsvd = pa_bits_rsvd & rsvd_bits(0, 51);
4209 rsvd_check->rsvd_bits_mask[0][4] = high_bits_rsvd | rsvd_bits(3, 7);
4210 rsvd_check->rsvd_bits_mask[0][3] = high_bits_rsvd | rsvd_bits(3, 7);
4211 rsvd_check->rsvd_bits_mask[0][2] = high_bits_rsvd | rsvd_bits(3, 6);
4212 rsvd_check->rsvd_bits_mask[0][1] = high_bits_rsvd | rsvd_bits(3, 6);
4213 rsvd_check->rsvd_bits_mask[0][0] = high_bits_rsvd;
4216 rsvd_check->rsvd_bits_mask[1][4] = rsvd_check->rsvd_bits_mask[0][4];
4217 rsvd_check->rsvd_bits_mask[1][3] = rsvd_check->rsvd_bits_mask[0][3];
4218 rsvd_check->rsvd_bits_mask[1][2] = high_bits_rsvd | rsvd_bits(12, 29);
4219 rsvd_check->rsvd_bits_mask[1][1] = high_bits_rsvd | rsvd_bits(12, 20);
4220 rsvd_check->rsvd_bits_mask[1][0] = rsvd_check->rsvd_bits_mask[0][0];
4222 bad_mt_xwr = 0xFFull << (2 * 8); /* bits 3..5 must not be 2 */
4223 bad_mt_xwr |= 0xFFull << (3 * 8); /* bits 3..5 must not be 3 */
4224 bad_mt_xwr |= 0xFFull << (7 * 8); /* bits 3..5 must not be 7 */
4225 bad_mt_xwr |= REPEAT_BYTE(1ull << 2); /* bits 0..2 must not be 010 */
4226 bad_mt_xwr |= REPEAT_BYTE(1ull << 6); /* bits 0..2 must not be 110 */
4228 /* bits 0..2 must not be 100 unless VMX capabilities allow it */
4229 bad_mt_xwr |= REPEAT_BYTE(1ull << 4);
4231 rsvd_check->bad_mt_xwr = bad_mt_xwr;
4234 static void reset_rsvds_bits_mask_ept(struct kvm_vcpu *vcpu,
4235 struct kvm_mmu *context, bool execonly)
4237 __reset_rsvds_bits_mask_ept(&context->guest_rsvd_check,
4238 vcpu->arch.reserved_gpa_bits, execonly);
4241 static inline u64 reserved_hpa_bits(void)
4243 return rsvd_bits(shadow_phys_bits, 63);
4247 * the page table on host is the shadow page table for the page
4248 * table in guest or amd nested guest, its mmu features completely
4249 * follow the features in guest.
4251 static void reset_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4252 struct kvm_mmu *context)
4255 * KVM uses NX when TDP is disabled to handle a variety of scenarios,
4256 * notably for huge SPTEs if iTLB multi-hit mitigation is enabled and
4257 * to generate correct permissions for CR0.WP=0/CR4.SMEP=1/EFER.NX=0.
4258 * The iTLB multi-hit workaround can be toggled at any time, so assume
4259 * NX can be used by any non-nested shadow MMU to avoid having to reset
4260 * MMU contexts. Note, KVM forces EFER.NX=1 when TDP is disabled.
4262 bool uses_nx = context->nx || !tdp_enabled;
4263 struct rsvd_bits_validate *shadow_zero_check;
4267 * Passing "true" to the last argument is okay; it adds a check
4268 * on bit 8 of the SPTEs which KVM doesn't use anyway.
4270 shadow_zero_check = &context->shadow_zero_check;
4271 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4272 reserved_hpa_bits(),
4273 context->shadow_root_level, uses_nx,
4274 guest_cpuid_has(vcpu, X86_FEATURE_GBPAGES),
4275 is_pse(vcpu), true);
4277 if (!shadow_me_mask)
4280 for (i = context->shadow_root_level; --i >= 0;) {
4281 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4282 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4287 static inline bool boot_cpu_is_amd(void)
4289 WARN_ON_ONCE(!tdp_enabled);
4290 return shadow_x_mask == 0;
4294 * the direct page table on host, use as much mmu features as
4295 * possible, however, kvm currently does not do execution-protection.
4298 reset_tdp_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4299 struct kvm_mmu *context)
4301 struct rsvd_bits_validate *shadow_zero_check;
4304 shadow_zero_check = &context->shadow_zero_check;
4306 if (boot_cpu_is_amd())
4307 __reset_rsvds_bits_mask(vcpu, shadow_zero_check,
4308 reserved_hpa_bits(),
4309 context->shadow_root_level, false,
4310 boot_cpu_has(X86_FEATURE_GBPAGES),
4313 __reset_rsvds_bits_mask_ept(shadow_zero_check,
4314 reserved_hpa_bits(), false);
4316 if (!shadow_me_mask)
4319 for (i = context->shadow_root_level; --i >= 0;) {
4320 shadow_zero_check->rsvd_bits_mask[0][i] &= ~shadow_me_mask;
4321 shadow_zero_check->rsvd_bits_mask[1][i] &= ~shadow_me_mask;
4326 * as the comments in reset_shadow_zero_bits_mask() except it
4327 * is the shadow page table for intel nested guest.
4330 reset_ept_shadow_zero_bits_mask(struct kvm_vcpu *vcpu,
4331 struct kvm_mmu *context, bool execonly)
4333 __reset_rsvds_bits_mask_ept(&context->shadow_zero_check,
4334 reserved_hpa_bits(), execonly);
4337 #define BYTE_MASK(access) \
4338 ((1 & (access) ? 2 : 0) | \
4339 (2 & (access) ? 4 : 0) | \
4340 (3 & (access) ? 8 : 0) | \
4341 (4 & (access) ? 16 : 0) | \
4342 (5 & (access) ? 32 : 0) | \
4343 (6 & (access) ? 64 : 0) | \
4344 (7 & (access) ? 128 : 0))
4347 static void update_permission_bitmask(struct kvm_vcpu *vcpu,
4348 struct kvm_mmu *mmu, bool ept)
4352 const u8 x = BYTE_MASK(ACC_EXEC_MASK);
4353 const u8 w = BYTE_MASK(ACC_WRITE_MASK);
4354 const u8 u = BYTE_MASK(ACC_USER_MASK);
4356 bool cr4_smep = kvm_read_cr4_bits(vcpu, X86_CR4_SMEP) != 0;
4357 bool cr4_smap = kvm_read_cr4_bits(vcpu, X86_CR4_SMAP) != 0;
4358 bool cr0_wp = is_write_protection(vcpu);
4360 for (byte = 0; byte < ARRAY_SIZE(mmu->permissions); ++byte) {
4361 unsigned pfec = byte << 1;
4364 * Each "*f" variable has a 1 bit for each UWX value
4365 * that causes a fault with the given PFEC.
4368 /* Faults from writes to non-writable pages */
4369 u8 wf = (pfec & PFERR_WRITE_MASK) ? (u8)~w : 0;
4370 /* Faults from user mode accesses to supervisor pages */
4371 u8 uf = (pfec & PFERR_USER_MASK) ? (u8)~u : 0;
4372 /* Faults from fetches of non-executable pages*/
4373 u8 ff = (pfec & PFERR_FETCH_MASK) ? (u8)~x : 0;
4374 /* Faults from kernel mode fetches of user pages */
4376 /* Faults from kernel mode accesses of user pages */
4380 /* Faults from kernel mode accesses to user pages */
4381 u8 kf = (pfec & PFERR_USER_MASK) ? 0 : u;
4383 /* Not really needed: !nx will cause pte.nx to fault */
4387 /* Allow supervisor writes if !cr0.wp */
4389 wf = (pfec & PFERR_USER_MASK) ? wf : 0;
4391 /* Disallow supervisor fetches of user code if cr4.smep */
4393 smepf = (pfec & PFERR_FETCH_MASK) ? kf : 0;
4396 * SMAP:kernel-mode data accesses from user-mode
4397 * mappings should fault. A fault is considered
4398 * as a SMAP violation if all of the following
4399 * conditions are true:
4400 * - X86_CR4_SMAP is set in CR4
4401 * - A user page is accessed
4402 * - The access is not a fetch
4403 * - Page fault in kernel mode
4404 * - if CPL = 3 or X86_EFLAGS_AC is clear
4406 * Here, we cover the first three conditions.
4407 * The fourth is computed dynamically in permission_fault();
4408 * PFERR_RSVD_MASK bit will be set in PFEC if the access is
4409 * *not* subject to SMAP restrictions.
4412 smapf = (pfec & (PFERR_RSVD_MASK|PFERR_FETCH_MASK)) ? 0 : kf;
4415 mmu->permissions[byte] = ff | uf | wf | smepf | smapf;
4420 * PKU is an additional mechanism by which the paging controls access to
4421 * user-mode addresses based on the value in the PKRU register. Protection
4422 * key violations are reported through a bit in the page fault error code.
4423 * Unlike other bits of the error code, the PK bit is not known at the
4424 * call site of e.g. gva_to_gpa; it must be computed directly in
4425 * permission_fault based on two bits of PKRU, on some machine state (CR4,
4426 * CR0, EFER, CPL), and on other bits of the error code and the page tables.
4428 * In particular the following conditions come from the error code, the
4429 * page tables and the machine state:
4430 * - PK is always zero unless CR4.PKE=1 and EFER.LMA=1
4431 * - PK is always zero if RSVD=1 (reserved bit set) or F=1 (instruction fetch)
4432 * - PK is always zero if U=0 in the page tables
4433 * - PKRU.WD is ignored if CR0.WP=0 and the access is a supervisor access.
4435 * The PKRU bitmask caches the result of these four conditions. The error
4436 * code (minus the P bit) and the page table's U bit form an index into the
4437 * PKRU bitmask. Two bits of the PKRU bitmask are then extracted and ANDed
4438 * with the two bits of the PKRU register corresponding to the protection key.
4439 * For the first three conditions above the bits will be 00, thus masking
4440 * away both AD and WD. For all reads or if the last condition holds, WD
4441 * only will be masked away.
4443 static void update_pkru_bitmask(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
4454 /* PKEY is enabled only if CR4.PKE and EFER.LMA are both set. */
4455 if (!kvm_read_cr4_bits(vcpu, X86_CR4_PKE) || !is_long_mode(vcpu)) {
4460 wp = is_write_protection(vcpu);
4462 for (bit = 0; bit < ARRAY_SIZE(mmu->permissions); ++bit) {
4463 unsigned pfec, pkey_bits;
4464 bool check_pkey, check_write, ff, uf, wf, pte_user;
4467 ff = pfec & PFERR_FETCH_MASK;
4468 uf = pfec & PFERR_USER_MASK;
4469 wf = pfec & PFERR_WRITE_MASK;
4471 /* PFEC.RSVD is replaced by ACC_USER_MASK. */
4472 pte_user = pfec & PFERR_RSVD_MASK;
4475 * Only need to check the access which is not an
4476 * instruction fetch and is to a user page.
4478 check_pkey = (!ff && pte_user);
4480 * write access is controlled by PKRU if it is a
4481 * user access or CR0.WP = 1.
4483 check_write = check_pkey && wf && (uf || wp);
4485 /* PKRU.AD stops both read and write access. */
4486 pkey_bits = !!check_pkey;
4487 /* PKRU.WD stops write access. */
4488 pkey_bits |= (!!check_write) << 1;
4490 mmu->pkru_mask |= (pkey_bits & 3) << pfec;
4494 static void update_last_nonleaf_level(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
4496 unsigned root_level = mmu->root_level;
4498 mmu->last_nonleaf_level = root_level;
4499 if (root_level == PT32_ROOT_LEVEL && is_pse(vcpu))
4500 mmu->last_nonleaf_level++;
4503 static void paging64_init_context_common(struct kvm_vcpu *vcpu,
4504 struct kvm_mmu *context,
4507 context->nx = is_nx(vcpu);
4508 context->root_level = root_level;
4510 MMU_WARN_ON(!is_pae(vcpu));
4511 context->page_fault = paging64_page_fault;
4512 context->gva_to_gpa = paging64_gva_to_gpa;
4513 context->sync_page = paging64_sync_page;
4514 context->invlpg = paging64_invlpg;
4515 context->direct_map = false;
4518 static void paging64_init_context(struct kvm_vcpu *vcpu,
4519 struct kvm_mmu *context)
4521 int root_level = is_la57_mode(vcpu) ?
4522 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4524 paging64_init_context_common(vcpu, context, root_level);
4527 static void paging32_init_context(struct kvm_vcpu *vcpu,
4528 struct kvm_mmu *context)
4530 context->nx = false;
4531 context->root_level = PT32_ROOT_LEVEL;
4532 context->page_fault = paging32_page_fault;
4533 context->gva_to_gpa = paging32_gva_to_gpa;
4534 context->sync_page = paging32_sync_page;
4535 context->invlpg = paging32_invlpg;
4536 context->direct_map = false;
4539 static void paging32E_init_context(struct kvm_vcpu *vcpu,
4540 struct kvm_mmu *context)
4542 paging64_init_context_common(vcpu, context, PT32E_ROOT_LEVEL);
4545 static union kvm_mmu_extended_role kvm_calc_mmu_role_ext(struct kvm_vcpu *vcpu)
4547 union kvm_mmu_extended_role ext = {0};
4549 ext.cr0_pg = !!is_paging(vcpu);
4550 ext.cr4_pae = !!is_pae(vcpu);
4551 ext.cr4_smep = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMEP);
4552 ext.cr4_smap = !!kvm_read_cr4_bits(vcpu, X86_CR4_SMAP);
4553 ext.cr4_pse = !!is_pse(vcpu);
4554 ext.cr4_pke = !!kvm_read_cr4_bits(vcpu, X86_CR4_PKE);
4555 ext.cr4_la57 = !!kvm_read_cr4_bits(vcpu, X86_CR4_LA57);
4562 static union kvm_mmu_role kvm_calc_mmu_role_common(struct kvm_vcpu *vcpu,
4565 union kvm_mmu_role role = {0};
4567 role.base.access = ACC_ALL;
4568 role.base.nxe = !!is_nx(vcpu);
4569 role.base.cr0_wp = is_write_protection(vcpu);
4570 role.base.smm = is_smm(vcpu);
4571 role.base.guest_mode = is_guest_mode(vcpu);
4576 role.ext = kvm_calc_mmu_role_ext(vcpu);
4581 static inline int kvm_mmu_get_tdp_level(struct kvm_vcpu *vcpu)
4583 /* Use 5-level TDP if and only if it's useful/necessary. */
4584 if (max_tdp_level == 5 && cpuid_maxphyaddr(vcpu) <= 48)
4587 return max_tdp_level;
4590 static union kvm_mmu_role
4591 kvm_calc_tdp_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4593 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4595 role.base.ad_disabled = (shadow_accessed_mask == 0);
4596 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4597 role.base.direct = true;
4598 role.base.gpte_is_8_bytes = true;
4603 static void init_kvm_tdp_mmu(struct kvm_vcpu *vcpu)
4605 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4606 union kvm_mmu_role new_role =
4607 kvm_calc_tdp_mmu_root_page_role(vcpu, false);
4609 if (new_role.as_u64 == context->mmu_role.as_u64)
4612 context->mmu_role.as_u64 = new_role.as_u64;
4613 context->page_fault = kvm_tdp_page_fault;
4614 context->sync_page = nonpaging_sync_page;
4615 context->invlpg = NULL;
4616 context->shadow_root_level = kvm_mmu_get_tdp_level(vcpu);
4617 context->direct_map = true;
4618 context->get_guest_pgd = get_cr3;
4619 context->get_pdptr = kvm_pdptr_read;
4620 context->inject_page_fault = kvm_inject_page_fault;
4622 if (!is_paging(vcpu)) {
4623 context->nx = false;
4624 context->gva_to_gpa = nonpaging_gva_to_gpa;
4625 context->root_level = 0;
4626 } else if (is_long_mode(vcpu)) {
4627 context->nx = is_nx(vcpu);
4628 context->root_level = is_la57_mode(vcpu) ?
4629 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4630 reset_rsvds_bits_mask(vcpu, context);
4631 context->gva_to_gpa = paging64_gva_to_gpa;
4632 } else if (is_pae(vcpu)) {
4633 context->nx = is_nx(vcpu);
4634 context->root_level = PT32E_ROOT_LEVEL;
4635 reset_rsvds_bits_mask(vcpu, context);
4636 context->gva_to_gpa = paging64_gva_to_gpa;
4638 context->nx = false;
4639 context->root_level = PT32_ROOT_LEVEL;
4640 reset_rsvds_bits_mask(vcpu, context);
4641 context->gva_to_gpa = paging32_gva_to_gpa;
4644 update_permission_bitmask(vcpu, context, false);
4645 update_pkru_bitmask(vcpu, context, false);
4646 update_last_nonleaf_level(vcpu, context);
4647 reset_tdp_shadow_zero_bits_mask(vcpu, context);
4650 static union kvm_mmu_role
4651 kvm_calc_shadow_root_page_role_common(struct kvm_vcpu *vcpu, bool base_only)
4653 union kvm_mmu_role role = kvm_calc_mmu_role_common(vcpu, base_only);
4655 role.base.smep_andnot_wp = role.ext.cr4_smep &&
4656 !is_write_protection(vcpu);
4657 role.base.smap_andnot_wp = role.ext.cr4_smap &&
4658 !is_write_protection(vcpu);
4659 role.base.gpte_is_8_bytes = !!is_pae(vcpu);
4664 static union kvm_mmu_role
4665 kvm_calc_shadow_mmu_root_page_role(struct kvm_vcpu *vcpu, bool base_only)
4667 union kvm_mmu_role role =
4668 kvm_calc_shadow_root_page_role_common(vcpu, base_only);
4670 role.base.direct = !is_paging(vcpu);
4672 if (!is_long_mode(vcpu))
4673 role.base.level = PT32E_ROOT_LEVEL;
4674 else if (is_la57_mode(vcpu))
4675 role.base.level = PT64_ROOT_5LEVEL;
4677 role.base.level = PT64_ROOT_4LEVEL;
4682 static void shadow_mmu_init_context(struct kvm_vcpu *vcpu, struct kvm_mmu *context,
4683 struct kvm_mmu_role_regs *regs,
4684 union kvm_mmu_role new_role)
4686 if (!____is_cr0_pg(regs))
4687 nonpaging_init_context(vcpu, context);
4688 else if (____is_efer_lma(regs))
4689 paging64_init_context(vcpu, context);
4690 else if (____is_cr4_pae(regs))
4691 paging32E_init_context(vcpu, context);
4693 paging32_init_context(vcpu, context);
4695 if (____is_cr0_pg(regs)) {
4696 reset_rsvds_bits_mask(vcpu, context);
4697 update_permission_bitmask(vcpu, context, false);
4698 update_pkru_bitmask(vcpu, context, false);
4699 update_last_nonleaf_level(vcpu, context);
4701 context->shadow_root_level = new_role.base.level;
4703 context->mmu_role.as_u64 = new_role.as_u64;
4704 reset_shadow_zero_bits_mask(vcpu, context);
4707 static void kvm_init_shadow_mmu(struct kvm_vcpu *vcpu,
4708 struct kvm_mmu_role_regs *regs)
4710 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4711 union kvm_mmu_role new_role =
4712 kvm_calc_shadow_mmu_root_page_role(vcpu, false);
4714 if (new_role.as_u64 != context->mmu_role.as_u64)
4715 shadow_mmu_init_context(vcpu, context, regs, new_role);
4718 static union kvm_mmu_role
4719 kvm_calc_shadow_npt_root_page_role(struct kvm_vcpu *vcpu)
4721 union kvm_mmu_role role =
4722 kvm_calc_shadow_root_page_role_common(vcpu, false);
4724 role.base.direct = false;
4725 role.base.level = kvm_mmu_get_tdp_level(vcpu);
4730 void kvm_init_shadow_npt_mmu(struct kvm_vcpu *vcpu, unsigned long cr0,
4731 unsigned long cr4, u64 efer, gpa_t nested_cr3)
4733 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4734 struct kvm_mmu_role_regs regs = {
4739 union kvm_mmu_role new_role = kvm_calc_shadow_npt_root_page_role(vcpu);
4741 __kvm_mmu_new_pgd(vcpu, nested_cr3, new_role.base);
4743 if (new_role.as_u64 != context->mmu_role.as_u64)
4744 shadow_mmu_init_context(vcpu, context, ®s, new_role);
4747 * Redo the shadow bits, the reset done by shadow_mmu_init_context()
4748 * (above) may use the wrong shadow_root_level.
4750 reset_shadow_zero_bits_mask(vcpu, context);
4752 EXPORT_SYMBOL_GPL(kvm_init_shadow_npt_mmu);
4754 static union kvm_mmu_role
4755 kvm_calc_shadow_ept_root_page_role(struct kvm_vcpu *vcpu, bool accessed_dirty,
4756 bool execonly, u8 level)
4758 union kvm_mmu_role role = {0};
4760 /* SMM flag is inherited from root_mmu */
4761 role.base.smm = vcpu->arch.root_mmu.mmu_role.base.smm;
4763 role.base.level = level;
4764 role.base.gpte_is_8_bytes = true;
4765 role.base.direct = false;
4766 role.base.ad_disabled = !accessed_dirty;
4767 role.base.guest_mode = true;
4768 role.base.access = ACC_ALL;
4770 /* EPT, and thus nested EPT, does not consume CR0, CR4, nor EFER. */
4772 role.ext.execonly = execonly;
4778 void kvm_init_shadow_ept_mmu(struct kvm_vcpu *vcpu, bool execonly,
4779 bool accessed_dirty, gpa_t new_eptp)
4781 struct kvm_mmu *context = &vcpu->arch.guest_mmu;
4782 u8 level = vmx_eptp_page_walk_level(new_eptp);
4783 union kvm_mmu_role new_role =
4784 kvm_calc_shadow_ept_root_page_role(vcpu, accessed_dirty,
4787 __kvm_mmu_new_pgd(vcpu, new_eptp, new_role.base);
4789 if (new_role.as_u64 == context->mmu_role.as_u64)
4792 context->shadow_root_level = level;
4795 context->ept_ad = accessed_dirty;
4796 context->page_fault = ept_page_fault;
4797 context->gva_to_gpa = ept_gva_to_gpa;
4798 context->sync_page = ept_sync_page;
4799 context->invlpg = ept_invlpg;
4800 context->root_level = level;
4801 context->direct_map = false;
4802 context->mmu_role.as_u64 = new_role.as_u64;
4804 update_permission_bitmask(vcpu, context, true);
4805 update_pkru_bitmask(vcpu, context, true);
4806 update_last_nonleaf_level(vcpu, context);
4807 reset_rsvds_bits_mask_ept(vcpu, context, execonly);
4808 reset_ept_shadow_zero_bits_mask(vcpu, context, execonly);
4810 EXPORT_SYMBOL_GPL(kvm_init_shadow_ept_mmu);
4812 static void init_kvm_softmmu(struct kvm_vcpu *vcpu)
4814 struct kvm_mmu *context = &vcpu->arch.root_mmu;
4815 struct kvm_mmu_role_regs regs = vcpu_to_role_regs(vcpu);
4817 kvm_init_shadow_mmu(vcpu, ®s);
4819 context->get_guest_pgd = get_cr3;
4820 context->get_pdptr = kvm_pdptr_read;
4821 context->inject_page_fault = kvm_inject_page_fault;
4824 static union kvm_mmu_role kvm_calc_nested_mmu_role(struct kvm_vcpu *vcpu)
4826 union kvm_mmu_role role = kvm_calc_shadow_root_page_role_common(vcpu, false);
4829 * Nested MMUs are used only for walking L2's gva->gpa, they never have
4830 * shadow pages of their own and so "direct" has no meaning. Set it
4831 * to "true" to try to detect bogus usage of the nested MMU.
4833 role.base.direct = true;
4835 if (!is_paging(vcpu))
4836 role.base.level = 0;
4837 else if (is_long_mode(vcpu))
4838 role.base.level = is_la57_mode(vcpu) ? PT64_ROOT_5LEVEL :
4840 else if (is_pae(vcpu))
4841 role.base.level = PT32E_ROOT_LEVEL;
4843 role.base.level = PT32_ROOT_LEVEL;
4848 static void init_kvm_nested_mmu(struct kvm_vcpu *vcpu)
4850 union kvm_mmu_role new_role = kvm_calc_nested_mmu_role(vcpu);
4851 struct kvm_mmu *g_context = &vcpu->arch.nested_mmu;
4853 if (new_role.as_u64 == g_context->mmu_role.as_u64)
4856 g_context->mmu_role.as_u64 = new_role.as_u64;
4857 g_context->get_guest_pgd = get_cr3;
4858 g_context->get_pdptr = kvm_pdptr_read;
4859 g_context->inject_page_fault = kvm_inject_page_fault;
4862 * L2 page tables are never shadowed, so there is no need to sync
4865 g_context->invlpg = NULL;
4868 * Note that arch.mmu->gva_to_gpa translates l2_gpa to l1_gpa using
4869 * L1's nested page tables (e.g. EPT12). The nested translation
4870 * of l2_gva to l1_gpa is done by arch.nested_mmu.gva_to_gpa using
4871 * L2's page tables as the first level of translation and L1's
4872 * nested page tables as the second level of translation. Basically
4873 * the gva_to_gpa functions between mmu and nested_mmu are swapped.
4875 if (!is_paging(vcpu)) {
4876 g_context->nx = false;
4877 g_context->root_level = 0;
4878 g_context->gva_to_gpa = nonpaging_gva_to_gpa_nested;
4879 } else if (is_long_mode(vcpu)) {
4880 g_context->nx = is_nx(vcpu);
4881 g_context->root_level = is_la57_mode(vcpu) ?
4882 PT64_ROOT_5LEVEL : PT64_ROOT_4LEVEL;
4883 reset_rsvds_bits_mask(vcpu, g_context);
4884 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4885 } else if (is_pae(vcpu)) {
4886 g_context->nx = is_nx(vcpu);
4887 g_context->root_level = PT32E_ROOT_LEVEL;
4888 reset_rsvds_bits_mask(vcpu, g_context);
4889 g_context->gva_to_gpa = paging64_gva_to_gpa_nested;
4891 g_context->nx = false;
4892 g_context->root_level = PT32_ROOT_LEVEL;
4893 reset_rsvds_bits_mask(vcpu, g_context);
4894 g_context->gva_to_gpa = paging32_gva_to_gpa_nested;
4897 update_permission_bitmask(vcpu, g_context, false);
4898 update_pkru_bitmask(vcpu, g_context, false);
4899 update_last_nonleaf_level(vcpu, g_context);
4902 void kvm_init_mmu(struct kvm_vcpu *vcpu)
4904 if (mmu_is_nested(vcpu))
4905 init_kvm_nested_mmu(vcpu);
4906 else if (tdp_enabled)
4907 init_kvm_tdp_mmu(vcpu);
4909 init_kvm_softmmu(vcpu);
4911 EXPORT_SYMBOL_GPL(kvm_init_mmu);
4913 static union kvm_mmu_page_role
4914 kvm_mmu_calc_root_page_role(struct kvm_vcpu *vcpu)
4916 union kvm_mmu_role role;
4919 role = kvm_calc_tdp_mmu_root_page_role(vcpu, true);
4921 role = kvm_calc_shadow_mmu_root_page_role(vcpu, true);
4926 void kvm_mmu_after_set_cpuid(struct kvm_vcpu *vcpu)
4929 * Invalidate all MMU roles to force them to reinitialize as CPUID
4930 * information is factored into reserved bit calculations.
4932 vcpu->arch.root_mmu.mmu_role.ext.valid = 0;
4933 vcpu->arch.guest_mmu.mmu_role.ext.valid = 0;
4934 vcpu->arch.nested_mmu.mmu_role.ext.valid = 0;
4935 kvm_mmu_reset_context(vcpu);
4938 * KVM does not correctly handle changing guest CPUID after KVM_RUN, as
4939 * MAXPHYADDR, GBPAGES support, AMD reserved bit behavior, etc.. aren't
4940 * tracked in kvm_mmu_page_role. As a result, KVM may miss guest page
4941 * faults due to reusing SPs/SPTEs. Alert userspace, but otherwise
4942 * sweep the problem under the rug.
4944 * KVM's horrific CPUID ABI makes the problem all but impossible to
4945 * solve, as correctly handling multiple vCPU models (with respect to
4946 * paging and physical address properties) in a single VM would require
4947 * tracking all relevant CPUID information in kvm_mmu_page_role. That
4948 * is very undesirable as it would double the memory requirements for
4949 * gfn_track (see struct kvm_mmu_page_role comments), and in practice
4950 * no sane VMM mucks with the core vCPU model on the fly.
4952 if (vcpu->arch.last_vmentry_cpu != -1) {
4953 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} after KVM_RUN may cause guest instability\n");
4954 pr_warn_ratelimited("KVM: KVM_SET_CPUID{,2} will fail after KVM_RUN starting with Linux 5.16\n");
4958 void kvm_mmu_reset_context(struct kvm_vcpu *vcpu)
4960 kvm_mmu_unload(vcpu);
4963 EXPORT_SYMBOL_GPL(kvm_mmu_reset_context);
4965 int kvm_mmu_load(struct kvm_vcpu *vcpu)
4969 r = mmu_topup_memory_caches(vcpu, !vcpu->arch.mmu->direct_map);
4972 r = mmu_alloc_special_roots(vcpu);
4975 if (vcpu->arch.mmu->direct_map)
4976 r = mmu_alloc_direct_roots(vcpu);
4978 r = mmu_alloc_shadow_roots(vcpu);
4982 kvm_mmu_sync_roots(vcpu);
4984 kvm_mmu_load_pgd(vcpu);
4985 static_call(kvm_x86_tlb_flush_current)(vcpu);
4990 void kvm_mmu_unload(struct kvm_vcpu *vcpu)
4992 kvm_mmu_free_roots(vcpu, &vcpu->arch.root_mmu, KVM_MMU_ROOTS_ALL);
4993 WARN_ON(VALID_PAGE(vcpu->arch.root_mmu.root_hpa));
4994 kvm_mmu_free_roots(vcpu, &vcpu->arch.guest_mmu, KVM_MMU_ROOTS_ALL);
4995 WARN_ON(VALID_PAGE(vcpu->arch.guest_mmu.root_hpa));
4998 static bool need_remote_flush(u64 old, u64 new)
5000 if (!is_shadow_present_pte(old))
5002 if (!is_shadow_present_pte(new))
5004 if ((old ^ new) & PT64_BASE_ADDR_MASK)
5006 old ^= shadow_nx_mask;
5007 new ^= shadow_nx_mask;
5008 return (old & ~new & PT64_PERM_MASK) != 0;
5011 static u64 mmu_pte_write_fetch_gpte(struct kvm_vcpu *vcpu, gpa_t *gpa,
5018 * Assume that the pte write on a page table of the same type
5019 * as the current vcpu paging mode since we update the sptes only
5020 * when they have the same mode.
5022 if (is_pae(vcpu) && *bytes == 4) {
5023 /* Handle a 32-bit guest writing two halves of a 64-bit gpte */
5028 if (*bytes == 4 || *bytes == 8) {
5029 r = kvm_vcpu_read_guest_atomic(vcpu, *gpa, &gentry, *bytes);
5038 * If we're seeing too many writes to a page, it may no longer be a page table,
5039 * or we may be forking, in which case it is better to unmap the page.
5041 static bool detect_write_flooding(struct kvm_mmu_page *sp)
5044 * Skip write-flooding detected for the sp whose level is 1, because
5045 * it can become unsync, then the guest page is not write-protected.
5047 if (sp->role.level == PG_LEVEL_4K)
5050 atomic_inc(&sp->write_flooding_count);
5051 return atomic_read(&sp->write_flooding_count) >= 3;
5055 * Misaligned accesses are too much trouble to fix up; also, they usually
5056 * indicate a page is not used as a page table.
5058 static bool detect_write_misaligned(struct kvm_mmu_page *sp, gpa_t gpa,
5061 unsigned offset, pte_size, misaligned;
5063 pgprintk("misaligned: gpa %llx bytes %d role %x\n",
5064 gpa, bytes, sp->role.word);
5066 offset = offset_in_page(gpa);
5067 pte_size = sp->role.gpte_is_8_bytes ? 8 : 4;
5070 * Sometimes, the OS only writes the last one bytes to update status
5071 * bits, for example, in linux, andb instruction is used in clear_bit().
5073 if (!(offset & (pte_size - 1)) && bytes == 1)
5076 misaligned = (offset ^ (offset + bytes - 1)) & ~(pte_size - 1);
5077 misaligned |= bytes < 4;
5082 static u64 *get_written_sptes(struct kvm_mmu_page *sp, gpa_t gpa, int *nspte)
5084 unsigned page_offset, quadrant;
5088 page_offset = offset_in_page(gpa);
5089 level = sp->role.level;
5091 if (!sp->role.gpte_is_8_bytes) {
5092 page_offset <<= 1; /* 32->64 */
5094 * A 32-bit pde maps 4MB while the shadow pdes map
5095 * only 2MB. So we need to double the offset again
5096 * and zap two pdes instead of one.
5098 if (level == PT32_ROOT_LEVEL) {
5099 page_offset &= ~7; /* kill rounding error */
5103 quadrant = page_offset >> PAGE_SHIFT;
5104 page_offset &= ~PAGE_MASK;
5105 if (quadrant != sp->role.quadrant)
5109 spte = &sp->spt[page_offset / sizeof(*spte)];
5113 static void kvm_mmu_pte_write(struct kvm_vcpu *vcpu, gpa_t gpa,
5114 const u8 *new, int bytes,
5115 struct kvm_page_track_notifier_node *node)
5117 gfn_t gfn = gpa >> PAGE_SHIFT;
5118 struct kvm_mmu_page *sp;
5119 LIST_HEAD(invalid_list);
5120 u64 entry, gentry, *spte;
5122 bool remote_flush, local_flush;
5125 * If we don't have indirect shadow pages, it means no page is
5126 * write-protected, so we can exit simply.
5128 if (!READ_ONCE(vcpu->kvm->arch.indirect_shadow_pages))
5131 remote_flush = local_flush = false;
5133 pgprintk("%s: gpa %llx bytes %d\n", __func__, gpa, bytes);
5136 * No need to care whether allocation memory is successful
5137 * or not since pte prefetch is skipped if it does not have
5138 * enough objects in the cache.
5140 mmu_topup_memory_caches(vcpu, true);
5142 write_lock(&vcpu->kvm->mmu_lock);
5144 gentry = mmu_pte_write_fetch_gpte(vcpu, &gpa, &bytes);
5146 ++vcpu->kvm->stat.mmu_pte_write;
5147 kvm_mmu_audit(vcpu, AUDIT_PRE_PTE_WRITE);
5149 for_each_gfn_indirect_valid_sp(vcpu->kvm, sp, gfn) {
5150 if (detect_write_misaligned(sp, gpa, bytes) ||
5151 detect_write_flooding(sp)) {
5152 kvm_mmu_prepare_zap_page(vcpu->kvm, sp, &invalid_list);
5153 ++vcpu->kvm->stat.mmu_flooded;
5157 spte = get_written_sptes(sp, gpa, &npte);
5164 mmu_page_zap_pte(vcpu->kvm, sp, spte, NULL);
5165 if (gentry && sp->role.level != PG_LEVEL_4K)
5166 ++vcpu->kvm->stat.mmu_pde_zapped;
5167 if (need_remote_flush(entry, *spte))
5168 remote_flush = true;
5172 kvm_mmu_flush_or_zap(vcpu, &invalid_list, remote_flush, local_flush);
5173 kvm_mmu_audit(vcpu, AUDIT_POST_PTE_WRITE);
5174 write_unlock(&vcpu->kvm->mmu_lock);
5177 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gpa_t cr2_or_gpa, u64 error_code,
5178 void *insn, int insn_len)
5180 int r, emulation_type = EMULTYPE_PF;
5181 bool direct = vcpu->arch.mmu->direct_map;
5183 if (WARN_ON(!VALID_PAGE(vcpu->arch.mmu->root_hpa)))
5184 return RET_PF_RETRY;
5187 if (unlikely(error_code & PFERR_RSVD_MASK)) {
5188 r = handle_mmio_page_fault(vcpu, cr2_or_gpa, direct);
5189 if (r == RET_PF_EMULATE)
5193 if (r == RET_PF_INVALID) {
5194 r = kvm_mmu_do_page_fault(vcpu, cr2_or_gpa,
5195 lower_32_bits(error_code), false);
5196 if (WARN_ON_ONCE(r == RET_PF_INVALID))
5202 if (r != RET_PF_EMULATE)
5206 * Before emulating the instruction, check if the error code
5207 * was due to a RO violation while translating the guest page.
5208 * This can occur when using nested virtualization with nested
5209 * paging in both guests. If true, we simply unprotect the page
5210 * and resume the guest.
5212 if (vcpu->arch.mmu->direct_map &&
5213 (error_code & PFERR_NESTED_GUEST_PAGE) == PFERR_NESTED_GUEST_PAGE) {
5214 kvm_mmu_unprotect_page(vcpu->kvm, gpa_to_gfn(cr2_or_gpa));
5219 * vcpu->arch.mmu.page_fault returned RET_PF_EMULATE, but we can still
5220 * optimistically try to just unprotect the page and let the processor
5221 * re-execute the instruction that caused the page fault. Do not allow
5222 * retrying MMIO emulation, as it's not only pointless but could also
5223 * cause us to enter an infinite loop because the processor will keep
5224 * faulting on the non-existent MMIO address. Retrying an instruction
5225 * from a nested guest is also pointless and dangerous as we are only
5226 * explicitly shadowing L1's page tables, i.e. unprotecting something
5227 * for L1 isn't going to magically fix whatever issue cause L2 to fail.
5229 if (!mmio_info_in_cache(vcpu, cr2_or_gpa, direct) && !is_guest_mode(vcpu))
5230 emulation_type |= EMULTYPE_ALLOW_RETRY_PF;
5232 return x86_emulate_instruction(vcpu, cr2_or_gpa, emulation_type, insn,
5235 EXPORT_SYMBOL_GPL(kvm_mmu_page_fault);
5237 void kvm_mmu_invalidate_gva(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu,
5238 gva_t gva, hpa_t root_hpa)
5242 /* It's actually a GPA for vcpu->arch.guest_mmu. */
5243 if (mmu != &vcpu->arch.guest_mmu) {
5244 /* INVLPG on a non-canonical address is a NOP according to the SDM. */
5245 if (is_noncanonical_address(gva, vcpu))
5248 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5254 if (root_hpa == INVALID_PAGE) {
5255 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5258 * INVLPG is required to invalidate any global mappings for the VA,
5259 * irrespective of PCID. Since it would take us roughly similar amount
5260 * of work to determine whether any of the prev_root mappings of the VA
5261 * is marked global, or to just sync it blindly, so we might as well
5262 * just always sync it.
5264 * Mappings not reachable via the current cr3 or the prev_roots will be
5265 * synced when switching to that cr3, so nothing needs to be done here
5268 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5269 if (VALID_PAGE(mmu->prev_roots[i].hpa))
5270 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5272 mmu->invlpg(vcpu, gva, root_hpa);
5276 void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva)
5278 kvm_mmu_invalidate_gva(vcpu, vcpu->arch.mmu, gva, INVALID_PAGE);
5279 ++vcpu->stat.invlpg;
5281 EXPORT_SYMBOL_GPL(kvm_mmu_invlpg);
5284 void kvm_mmu_invpcid_gva(struct kvm_vcpu *vcpu, gva_t gva, unsigned long pcid)
5286 struct kvm_mmu *mmu = vcpu->arch.mmu;
5287 bool tlb_flush = false;
5290 if (pcid == kvm_get_active_pcid(vcpu)) {
5291 mmu->invlpg(vcpu, gva, mmu->root_hpa);
5295 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++) {
5296 if (VALID_PAGE(mmu->prev_roots[i].hpa) &&
5297 pcid == kvm_get_pcid(vcpu, mmu->prev_roots[i].pgd)) {
5298 mmu->invlpg(vcpu, gva, mmu->prev_roots[i].hpa);
5304 static_call(kvm_x86_tlb_flush_gva)(vcpu, gva);
5306 ++vcpu->stat.invlpg;
5309 * Mappings not reachable via the current cr3 or the prev_roots will be
5310 * synced when switching to that cr3, so nothing needs to be done here
5315 void kvm_configure_mmu(bool enable_tdp, int tdp_max_root_level,
5316 int tdp_huge_page_level)
5318 tdp_enabled = enable_tdp;
5319 max_tdp_level = tdp_max_root_level;
5322 * max_huge_page_level reflects KVM's MMU capabilities irrespective
5323 * of kernel support, e.g. KVM may be capable of using 1GB pages when
5324 * the kernel is not. But, KVM never creates a page size greater than
5325 * what is used by the kernel for any given HVA, i.e. the kernel's
5326 * capabilities are ultimately consulted by kvm_mmu_hugepage_adjust().
5329 max_huge_page_level = tdp_huge_page_level;
5330 else if (boot_cpu_has(X86_FEATURE_GBPAGES))
5331 max_huge_page_level = PG_LEVEL_1G;
5333 max_huge_page_level = PG_LEVEL_2M;
5335 EXPORT_SYMBOL_GPL(kvm_configure_mmu);
5337 /* The return value indicates if tlb flush on all vcpus is needed. */
5338 typedef bool (*slot_level_handler) (struct kvm *kvm, struct kvm_rmap_head *rmap_head,
5339 struct kvm_memory_slot *slot);
5341 /* The caller should hold mmu-lock before calling this function. */
5342 static __always_inline bool
5343 slot_handle_level_range(struct kvm *kvm, struct kvm_memory_slot *memslot,
5344 slot_level_handler fn, int start_level, int end_level,
5345 gfn_t start_gfn, gfn_t end_gfn, bool flush_on_yield,
5348 struct slot_rmap_walk_iterator iterator;
5350 for_each_slot_rmap_range(memslot, start_level, end_level, start_gfn,
5351 end_gfn, &iterator) {
5353 flush |= fn(kvm, iterator.rmap, memslot);
5355 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
5356 if (flush && flush_on_yield) {
5357 kvm_flush_remote_tlbs_with_address(kvm,
5359 iterator.gfn - start_gfn + 1);
5362 cond_resched_rwlock_write(&kvm->mmu_lock);
5369 static __always_inline bool
5370 slot_handle_level(struct kvm *kvm, struct kvm_memory_slot *memslot,
5371 slot_level_handler fn, int start_level, int end_level,
5372 bool flush_on_yield)
5374 return slot_handle_level_range(kvm, memslot, fn, start_level,
5375 end_level, memslot->base_gfn,
5376 memslot->base_gfn + memslot->npages - 1,
5377 flush_on_yield, false);
5380 static __always_inline bool
5381 slot_handle_leaf(struct kvm *kvm, struct kvm_memory_slot *memslot,
5382 slot_level_handler fn, bool flush_on_yield)
5384 return slot_handle_level(kvm, memslot, fn, PG_LEVEL_4K,
5385 PG_LEVEL_4K, flush_on_yield);
5388 static void free_mmu_pages(struct kvm_mmu *mmu)
5390 if (!tdp_enabled && mmu->pae_root)
5391 set_memory_encrypted((unsigned long)mmu->pae_root, 1);
5392 free_page((unsigned long)mmu->pae_root);
5393 free_page((unsigned long)mmu->pml4_root);
5396 static int __kvm_mmu_create(struct kvm_vcpu *vcpu, struct kvm_mmu *mmu)
5401 mmu->root_hpa = INVALID_PAGE;
5403 mmu->translate_gpa = translate_gpa;
5404 for (i = 0; i < KVM_MMU_NUM_PREV_ROOTS; i++)
5405 mmu->prev_roots[i] = KVM_MMU_ROOT_INFO_INVALID;
5408 * When using PAE paging, the four PDPTEs are treated as 'root' pages,
5409 * while the PDP table is a per-vCPU construct that's allocated at MMU
5410 * creation. When emulating 32-bit mode, cr3 is only 32 bits even on
5411 * x86_64. Therefore we need to allocate the PDP table in the first
5412 * 4GB of memory, which happens to fit the DMA32 zone. TDP paging
5413 * generally doesn't use PAE paging and can skip allocating the PDP
5414 * table. The main exception, handled here, is SVM's 32-bit NPT. The
5415 * other exception is for shadowing L1's 32-bit or PAE NPT on 64-bit
5416 * KVM; that horror is handled on-demand by mmu_alloc_shadow_roots().
5418 if (tdp_enabled && kvm_mmu_get_tdp_level(vcpu) > PT32E_ROOT_LEVEL)
5421 page = alloc_page(GFP_KERNEL_ACCOUNT | __GFP_DMA32);
5425 mmu->pae_root = page_address(page);
5428 * CR3 is only 32 bits when PAE paging is used, thus it's impossible to
5429 * get the CPU to treat the PDPTEs as encrypted. Decrypt the page so
5430 * that KVM's writes and the CPU's reads get along. Note, this is
5431 * only necessary when using shadow paging, as 64-bit NPT can get at
5432 * the C-bit even when shadowing 32-bit NPT, and SME isn't supported
5433 * by 32-bit kernels (when KVM itself uses 32-bit NPT).
5436 set_memory_decrypted((unsigned long)mmu->pae_root, 1);
5438 WARN_ON_ONCE(shadow_me_mask);
5440 for (i = 0; i < 4; ++i)
5441 mmu->pae_root[i] = INVALID_PAE_ROOT;
5446 int kvm_mmu_create(struct kvm_vcpu *vcpu)
5450 vcpu->arch.mmu_pte_list_desc_cache.kmem_cache = pte_list_desc_cache;
5451 vcpu->arch.mmu_pte_list_desc_cache.gfp_zero = __GFP_ZERO;
5453 vcpu->arch.mmu_page_header_cache.kmem_cache = mmu_page_header_cache;
5454 vcpu->arch.mmu_page_header_cache.gfp_zero = __GFP_ZERO;
5456 vcpu->arch.mmu_shadow_page_cache.gfp_zero = __GFP_ZERO;
5458 vcpu->arch.mmu = &vcpu->arch.root_mmu;
5459 vcpu->arch.walk_mmu = &vcpu->arch.root_mmu;
5461 vcpu->arch.nested_mmu.translate_gpa = translate_nested_gpa;
5463 ret = __kvm_mmu_create(vcpu, &vcpu->arch.guest_mmu);
5467 ret = __kvm_mmu_create(vcpu, &vcpu->arch.root_mmu);
5469 goto fail_allocate_root;
5473 free_mmu_pages(&vcpu->arch.guest_mmu);
5477 #define BATCH_ZAP_PAGES 10
5478 static void kvm_zap_obsolete_pages(struct kvm *kvm)
5480 struct kvm_mmu_page *sp, *node;
5481 int nr_zapped, batch = 0;
5484 list_for_each_entry_safe_reverse(sp, node,
5485 &kvm->arch.active_mmu_pages, link) {
5487 * No obsolete valid page exists before a newly created page
5488 * since active_mmu_pages is a FIFO list.
5490 if (!is_obsolete_sp(kvm, sp))
5494 * Invalid pages should never land back on the list of active
5495 * pages. Skip the bogus page, otherwise we'll get stuck in an
5496 * infinite loop if the page gets put back on the list (again).
5498 if (WARN_ON(sp->role.invalid))
5502 * No need to flush the TLB since we're only zapping shadow
5503 * pages with an obsolete generation number and all vCPUS have
5504 * loaded a new root, i.e. the shadow pages being zapped cannot
5505 * be in active use by the guest.
5507 if (batch >= BATCH_ZAP_PAGES &&
5508 cond_resched_rwlock_write(&kvm->mmu_lock)) {
5513 if (__kvm_mmu_prepare_zap_page(kvm, sp,
5514 &kvm->arch.zapped_obsolete_pages, &nr_zapped)) {
5521 * Trigger a remote TLB flush before freeing the page tables to ensure
5522 * KVM is not in the middle of a lockless shadow page table walk, which
5523 * may reference the pages.
5525 kvm_mmu_commit_zap_page(kvm, &kvm->arch.zapped_obsolete_pages);
5529 * Fast invalidate all shadow pages and use lock-break technique
5530 * to zap obsolete pages.
5532 * It's required when memslot is being deleted or VM is being
5533 * destroyed, in these cases, we should ensure that KVM MMU does
5534 * not use any resource of the being-deleted slot or all slots
5535 * after calling the function.
5537 static void kvm_mmu_zap_all_fast(struct kvm *kvm)
5539 lockdep_assert_held(&kvm->slots_lock);
5541 write_lock(&kvm->mmu_lock);
5542 trace_kvm_mmu_zap_all_fast(kvm);
5545 * Toggle mmu_valid_gen between '0' and '1'. Because slots_lock is
5546 * held for the entire duration of zapping obsolete pages, it's
5547 * impossible for there to be multiple invalid generations associated
5548 * with *valid* shadow pages at any given time, i.e. there is exactly
5549 * one valid generation and (at most) one invalid generation.
5551 kvm->arch.mmu_valid_gen = kvm->arch.mmu_valid_gen ? 0 : 1;
5553 /* In order to ensure all threads see this change when
5554 * handling the MMU reload signal, this must happen in the
5555 * same critical section as kvm_reload_remote_mmus, and
5556 * before kvm_zap_obsolete_pages as kvm_zap_obsolete_pages
5557 * could drop the MMU lock and yield.
5559 if (is_tdp_mmu_enabled(kvm))
5560 kvm_tdp_mmu_invalidate_all_roots(kvm);
5563 * Notify all vcpus to reload its shadow page table and flush TLB.
5564 * Then all vcpus will switch to new shadow page table with the new
5567 * Note: we need to do this under the protection of mmu_lock,
5568 * otherwise, vcpu would purge shadow page but miss tlb flush.
5570 kvm_reload_remote_mmus(kvm);
5572 kvm_zap_obsolete_pages(kvm);
5574 write_unlock(&kvm->mmu_lock);
5576 if (is_tdp_mmu_enabled(kvm)) {
5577 read_lock(&kvm->mmu_lock);
5578 kvm_tdp_mmu_zap_invalidated_roots(kvm);
5579 read_unlock(&kvm->mmu_lock);
5583 static bool kvm_has_zapped_obsolete_pages(struct kvm *kvm)
5585 return unlikely(!list_empty_careful(&kvm->arch.zapped_obsolete_pages));
5588 static void kvm_mmu_invalidate_zap_pages_in_memslot(struct kvm *kvm,
5589 struct kvm_memory_slot *slot,
5590 struct kvm_page_track_notifier_node *node)
5592 kvm_mmu_zap_all_fast(kvm);
5595 void kvm_mmu_init_vm(struct kvm *kvm)
5597 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5599 if (!kvm_mmu_init_tdp_mmu(kvm))
5601 * No smp_load/store wrappers needed here as we are in
5602 * VM init and there cannot be any memslots / other threads
5603 * accessing this struct kvm yet.
5605 kvm->arch.memslots_have_rmaps = true;
5607 node->track_write = kvm_mmu_pte_write;
5608 node->track_flush_slot = kvm_mmu_invalidate_zap_pages_in_memslot;
5609 kvm_page_track_register_notifier(kvm, node);
5612 void kvm_mmu_uninit_vm(struct kvm *kvm)
5614 struct kvm_page_track_notifier_node *node = &kvm->arch.mmu_sp_tracker;
5616 kvm_page_track_unregister_notifier(kvm, node);
5618 kvm_mmu_uninit_tdp_mmu(kvm);
5621 void kvm_zap_gfn_range(struct kvm *kvm, gfn_t gfn_start, gfn_t gfn_end)
5623 struct kvm_memslots *slots;
5624 struct kvm_memory_slot *memslot;
5628 if (kvm_memslots_have_rmaps(kvm)) {
5629 write_lock(&kvm->mmu_lock);
5630 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
5631 slots = __kvm_memslots(kvm, i);
5632 kvm_for_each_memslot(memslot, slots) {
5635 start = max(gfn_start, memslot->base_gfn);
5636 end = min(gfn_end, memslot->base_gfn + memslot->npages);
5640 flush = slot_handle_level_range(kvm, memslot,
5641 kvm_zap_rmapp, PG_LEVEL_4K,
5642 KVM_MAX_HUGEPAGE_LEVEL, start,
5643 end - 1, true, flush);
5647 kvm_flush_remote_tlbs_with_address(kvm, gfn_start, gfn_end);
5648 write_unlock(&kvm->mmu_lock);
5651 if (is_tdp_mmu_enabled(kvm)) {
5654 read_lock(&kvm->mmu_lock);
5655 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++)
5656 flush = kvm_tdp_mmu_zap_gfn_range(kvm, i, gfn_start,
5657 gfn_end, flush, true);
5659 kvm_flush_remote_tlbs_with_address(kvm, gfn_start,
5662 read_unlock(&kvm->mmu_lock);
5666 static bool slot_rmap_write_protect(struct kvm *kvm,
5667 struct kvm_rmap_head *rmap_head,
5668 struct kvm_memory_slot *slot)
5670 return __rmap_write_protect(kvm, rmap_head, false);
5673 void kvm_mmu_slot_remove_write_access(struct kvm *kvm,
5674 struct kvm_memory_slot *memslot,
5679 if (kvm_memslots_have_rmaps(kvm)) {
5680 write_lock(&kvm->mmu_lock);
5681 flush = slot_handle_level(kvm, memslot, slot_rmap_write_protect,
5682 start_level, KVM_MAX_HUGEPAGE_LEVEL,
5684 write_unlock(&kvm->mmu_lock);
5687 if (is_tdp_mmu_enabled(kvm)) {
5688 read_lock(&kvm->mmu_lock);
5689 flush |= kvm_tdp_mmu_wrprot_slot(kvm, memslot, start_level);
5690 read_unlock(&kvm->mmu_lock);
5694 * We can flush all the TLBs out of the mmu lock without TLB
5695 * corruption since we just change the spte from writable to
5696 * readonly so that we only need to care the case of changing
5697 * spte from present to present (changing the spte from present
5698 * to nonpresent will flush all the TLBs immediately), in other
5699 * words, the only case we care is mmu_spte_update() where we
5700 * have checked Host-writable | MMU-writable instead of
5701 * PT_WRITABLE_MASK, that means it does not depend on PT_WRITABLE_MASK
5705 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5708 static bool kvm_mmu_zap_collapsible_spte(struct kvm *kvm,
5709 struct kvm_rmap_head *rmap_head,
5710 struct kvm_memory_slot *slot)
5713 struct rmap_iterator iter;
5714 int need_tlb_flush = 0;
5716 struct kvm_mmu_page *sp;
5719 for_each_rmap_spte(rmap_head, &iter, sptep) {
5720 sp = sptep_to_sp(sptep);
5721 pfn = spte_to_pfn(*sptep);
5724 * We cannot do huge page mapping for indirect shadow pages,
5725 * which are found on the last rmap (level = 1) when not using
5726 * tdp; such shadow pages are synced with the page table in
5727 * the guest, and the guest page table is using 4K page size
5728 * mapping if the indirect sp has level = 1.
5730 if (sp->role.direct && !kvm_is_reserved_pfn(pfn) &&
5731 sp->role.level < kvm_mmu_max_mapping_level(kvm, slot, sp->gfn,
5732 pfn, PG_LEVEL_NUM)) {
5733 pte_list_remove(rmap_head, sptep);
5735 if (kvm_available_flush_tlb_with_range())
5736 kvm_flush_remote_tlbs_with_address(kvm, sp->gfn,
5737 KVM_PAGES_PER_HPAGE(sp->role.level));
5745 return need_tlb_flush;
5748 void kvm_mmu_zap_collapsible_sptes(struct kvm *kvm,
5749 const struct kvm_memory_slot *memslot)
5751 /* FIXME: const-ify all uses of struct kvm_memory_slot. */
5752 struct kvm_memory_slot *slot = (struct kvm_memory_slot *)memslot;
5755 if (kvm_memslots_have_rmaps(kvm)) {
5756 write_lock(&kvm->mmu_lock);
5757 flush = slot_handle_leaf(kvm, slot, kvm_mmu_zap_collapsible_spte, true);
5759 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5760 write_unlock(&kvm->mmu_lock);
5763 if (is_tdp_mmu_enabled(kvm)) {
5764 read_lock(&kvm->mmu_lock);
5765 flush = kvm_tdp_mmu_zap_collapsible_sptes(kvm, slot, flush);
5767 kvm_arch_flush_remote_tlbs_memslot(kvm, slot);
5768 read_unlock(&kvm->mmu_lock);
5772 void kvm_arch_flush_remote_tlbs_memslot(struct kvm *kvm,
5773 const struct kvm_memory_slot *memslot)
5776 * All current use cases for flushing the TLBs for a specific memslot
5777 * related to dirty logging, and many do the TLB flush out of mmu_lock.
5778 * The interaction between the various operations on memslot must be
5779 * serialized by slots_locks to ensure the TLB flush from one operation
5780 * is observed by any other operation on the same memslot.
5782 lockdep_assert_held(&kvm->slots_lock);
5783 kvm_flush_remote_tlbs_with_address(kvm, memslot->base_gfn,
5787 void kvm_mmu_slot_leaf_clear_dirty(struct kvm *kvm,
5788 struct kvm_memory_slot *memslot)
5792 if (kvm_memslots_have_rmaps(kvm)) {
5793 write_lock(&kvm->mmu_lock);
5794 flush = slot_handle_leaf(kvm, memslot, __rmap_clear_dirty,
5796 write_unlock(&kvm->mmu_lock);
5799 if (is_tdp_mmu_enabled(kvm)) {
5800 read_lock(&kvm->mmu_lock);
5801 flush |= kvm_tdp_mmu_clear_dirty_slot(kvm, memslot);
5802 read_unlock(&kvm->mmu_lock);
5806 * It's also safe to flush TLBs out of mmu lock here as currently this
5807 * function is only used for dirty logging, in which case flushing TLB
5808 * out of mmu lock also guarantees no dirty pages will be lost in
5812 kvm_arch_flush_remote_tlbs_memslot(kvm, memslot);
5815 void kvm_mmu_zap_all(struct kvm *kvm)
5817 struct kvm_mmu_page *sp, *node;
5818 LIST_HEAD(invalid_list);
5821 write_lock(&kvm->mmu_lock);
5823 list_for_each_entry_safe(sp, node, &kvm->arch.active_mmu_pages, link) {
5824 if (WARN_ON(sp->role.invalid))
5826 if (__kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list, &ign))
5828 if (cond_resched_rwlock_write(&kvm->mmu_lock))
5832 kvm_mmu_commit_zap_page(kvm, &invalid_list);
5834 if (is_tdp_mmu_enabled(kvm))
5835 kvm_tdp_mmu_zap_all(kvm);
5837 write_unlock(&kvm->mmu_lock);
5840 void kvm_mmu_invalidate_mmio_sptes(struct kvm *kvm, u64 gen)
5842 WARN_ON(gen & KVM_MEMSLOT_GEN_UPDATE_IN_PROGRESS);
5844 gen &= MMIO_SPTE_GEN_MASK;
5847 * Generation numbers are incremented in multiples of the number of
5848 * address spaces in order to provide unique generations across all
5849 * address spaces. Strip what is effectively the address space
5850 * modifier prior to checking for a wrap of the MMIO generation so
5851 * that a wrap in any address space is detected.
5853 gen &= ~((u64)KVM_ADDRESS_SPACE_NUM - 1);
5856 * The very rare case: if the MMIO generation number has wrapped,
5857 * zap all shadow pages.
5859 if (unlikely(gen == 0)) {
5860 kvm_debug_ratelimited("kvm: zapping shadow pages for mmio generation wraparound\n");
5861 kvm_mmu_zap_all_fast(kvm);
5865 static unsigned long
5866 mmu_shrink_scan(struct shrinker *shrink, struct shrink_control *sc)
5869 int nr_to_scan = sc->nr_to_scan;
5870 unsigned long freed = 0;
5872 mutex_lock(&kvm_lock);
5874 list_for_each_entry(kvm, &vm_list, vm_list) {
5876 LIST_HEAD(invalid_list);
5879 * Never scan more than sc->nr_to_scan VM instances.
5880 * Will not hit this condition practically since we do not try
5881 * to shrink more than one VM and it is very unlikely to see
5882 * !n_used_mmu_pages so many times.
5887 * n_used_mmu_pages is accessed without holding kvm->mmu_lock
5888 * here. We may skip a VM instance errorneosly, but we do not
5889 * want to shrink a VM that only started to populate its MMU
5892 if (!kvm->arch.n_used_mmu_pages &&
5893 !kvm_has_zapped_obsolete_pages(kvm))
5896 idx = srcu_read_lock(&kvm->srcu);
5897 write_lock(&kvm->mmu_lock);
5899 if (kvm_has_zapped_obsolete_pages(kvm)) {
5900 kvm_mmu_commit_zap_page(kvm,
5901 &kvm->arch.zapped_obsolete_pages);
5905 freed = kvm_mmu_zap_oldest_mmu_pages(kvm, sc->nr_to_scan);
5908 write_unlock(&kvm->mmu_lock);
5909 srcu_read_unlock(&kvm->srcu, idx);
5912 * unfair on small ones
5913 * per-vm shrinkers cry out
5914 * sadness comes quickly
5916 list_move_tail(&kvm->vm_list, &vm_list);
5920 mutex_unlock(&kvm_lock);
5924 static unsigned long
5925 mmu_shrink_count(struct shrinker *shrink, struct shrink_control *sc)
5927 return percpu_counter_read_positive(&kvm_total_used_mmu_pages);
5930 static struct shrinker mmu_shrinker = {
5931 .count_objects = mmu_shrink_count,
5932 .scan_objects = mmu_shrink_scan,
5933 .seeks = DEFAULT_SEEKS * 10,
5936 static void mmu_destroy_caches(void)
5938 kmem_cache_destroy(pte_list_desc_cache);
5939 kmem_cache_destroy(mmu_page_header_cache);
5942 static bool get_nx_auto_mode(void)
5944 /* Return true when CPU has the bug, and mitigations are ON */
5945 return boot_cpu_has_bug(X86_BUG_ITLB_MULTIHIT) && !cpu_mitigations_off();
5948 static void __set_nx_huge_pages(bool val)
5950 nx_huge_pages = itlb_multihit_kvm_mitigation = val;
5953 static int set_nx_huge_pages(const char *val, const struct kernel_param *kp)
5955 bool old_val = nx_huge_pages;
5958 /* In "auto" mode deploy workaround only if CPU has the bug. */
5959 if (sysfs_streq(val, "off"))
5961 else if (sysfs_streq(val, "force"))
5963 else if (sysfs_streq(val, "auto"))
5964 new_val = get_nx_auto_mode();
5965 else if (strtobool(val, &new_val) < 0)
5968 __set_nx_huge_pages(new_val);
5970 if (new_val != old_val) {
5973 mutex_lock(&kvm_lock);
5975 list_for_each_entry(kvm, &vm_list, vm_list) {
5976 mutex_lock(&kvm->slots_lock);
5977 kvm_mmu_zap_all_fast(kvm);
5978 mutex_unlock(&kvm->slots_lock);
5980 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
5982 mutex_unlock(&kvm_lock);
5988 int kvm_mmu_module_init(void)
5992 if (nx_huge_pages == -1)
5993 __set_nx_huge_pages(get_nx_auto_mode());
5996 * MMU roles use union aliasing which is, generally speaking, an
5997 * undefined behavior. However, we supposedly know how compilers behave
5998 * and the current status quo is unlikely to change. Guardians below are
5999 * supposed to let us know if the assumption becomes false.
6001 BUILD_BUG_ON(sizeof(union kvm_mmu_page_role) != sizeof(u32));
6002 BUILD_BUG_ON(sizeof(union kvm_mmu_extended_role) != sizeof(u32));
6003 BUILD_BUG_ON(sizeof(union kvm_mmu_role) != sizeof(u64));
6005 kvm_mmu_reset_all_pte_masks();
6007 pte_list_desc_cache = kmem_cache_create("pte_list_desc",
6008 sizeof(struct pte_list_desc),
6009 0, SLAB_ACCOUNT, NULL);
6010 if (!pte_list_desc_cache)
6013 mmu_page_header_cache = kmem_cache_create("kvm_mmu_page_header",
6014 sizeof(struct kvm_mmu_page),
6015 0, SLAB_ACCOUNT, NULL);
6016 if (!mmu_page_header_cache)
6019 if (percpu_counter_init(&kvm_total_used_mmu_pages, 0, GFP_KERNEL))
6022 ret = register_shrinker(&mmu_shrinker);
6029 mmu_destroy_caches();
6034 * Calculate mmu pages needed for kvm.
6036 unsigned long kvm_mmu_calculate_default_mmu_pages(struct kvm *kvm)
6038 unsigned long nr_mmu_pages;
6039 unsigned long nr_pages = 0;
6040 struct kvm_memslots *slots;
6041 struct kvm_memory_slot *memslot;
6044 for (i = 0; i < KVM_ADDRESS_SPACE_NUM; i++) {
6045 slots = __kvm_memslots(kvm, i);
6047 kvm_for_each_memslot(memslot, slots)
6048 nr_pages += memslot->npages;
6051 nr_mmu_pages = nr_pages * KVM_PERMILLE_MMU_PAGES / 1000;
6052 nr_mmu_pages = max(nr_mmu_pages, KVM_MIN_ALLOC_MMU_PAGES);
6054 return nr_mmu_pages;
6057 void kvm_mmu_destroy(struct kvm_vcpu *vcpu)
6059 kvm_mmu_unload(vcpu);
6060 free_mmu_pages(&vcpu->arch.root_mmu);
6061 free_mmu_pages(&vcpu->arch.guest_mmu);
6062 mmu_free_memory_caches(vcpu);
6065 void kvm_mmu_module_exit(void)
6067 mmu_destroy_caches();
6068 percpu_counter_destroy(&kvm_total_used_mmu_pages);
6069 unregister_shrinker(&mmu_shrinker);
6070 mmu_audit_disable();
6073 static int set_nx_huge_pages_recovery_ratio(const char *val, const struct kernel_param *kp)
6075 unsigned int old_val;
6078 old_val = nx_huge_pages_recovery_ratio;
6079 err = param_set_uint(val, kp);
6083 if (READ_ONCE(nx_huge_pages) &&
6084 !old_val && nx_huge_pages_recovery_ratio) {
6087 mutex_lock(&kvm_lock);
6089 list_for_each_entry(kvm, &vm_list, vm_list)
6090 wake_up_process(kvm->arch.nx_lpage_recovery_thread);
6092 mutex_unlock(&kvm_lock);
6098 static void kvm_recover_nx_lpages(struct kvm *kvm)
6100 unsigned long nx_lpage_splits = kvm->stat.nx_lpage_splits;
6102 struct kvm_mmu_page *sp;
6104 LIST_HEAD(invalid_list);
6108 rcu_idx = srcu_read_lock(&kvm->srcu);
6109 write_lock(&kvm->mmu_lock);
6111 ratio = READ_ONCE(nx_huge_pages_recovery_ratio);
6112 to_zap = ratio ? DIV_ROUND_UP(nx_lpage_splits, ratio) : 0;
6113 for ( ; to_zap; --to_zap) {
6114 if (list_empty(&kvm->arch.lpage_disallowed_mmu_pages))
6118 * We use a separate list instead of just using active_mmu_pages
6119 * because the number of lpage_disallowed pages is expected to
6120 * be relatively small compared to the total.
6122 sp = list_first_entry(&kvm->arch.lpage_disallowed_mmu_pages,
6123 struct kvm_mmu_page,
6124 lpage_disallowed_link);
6125 WARN_ON_ONCE(!sp->lpage_disallowed);
6126 if (is_tdp_mmu_page(sp)) {
6127 flush |= kvm_tdp_mmu_zap_sp(kvm, sp);
6129 kvm_mmu_prepare_zap_page(kvm, sp, &invalid_list);
6130 WARN_ON_ONCE(sp->lpage_disallowed);
6133 if (need_resched() || rwlock_needbreak(&kvm->mmu_lock)) {
6134 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6135 cond_resched_rwlock_write(&kvm->mmu_lock);
6139 kvm_mmu_remote_flush_or_zap(kvm, &invalid_list, flush);
6141 write_unlock(&kvm->mmu_lock);
6142 srcu_read_unlock(&kvm->srcu, rcu_idx);
6145 static long get_nx_lpage_recovery_timeout(u64 start_time)
6147 return READ_ONCE(nx_huge_pages) && READ_ONCE(nx_huge_pages_recovery_ratio)
6148 ? start_time + 60 * HZ - get_jiffies_64()
6149 : MAX_SCHEDULE_TIMEOUT;
6152 static int kvm_nx_lpage_recovery_worker(struct kvm *kvm, uintptr_t data)
6155 long remaining_time;
6158 start_time = get_jiffies_64();
6159 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6161 set_current_state(TASK_INTERRUPTIBLE);
6162 while (!kthread_should_stop() && remaining_time > 0) {
6163 schedule_timeout(remaining_time);
6164 remaining_time = get_nx_lpage_recovery_timeout(start_time);
6165 set_current_state(TASK_INTERRUPTIBLE);
6168 set_current_state(TASK_RUNNING);
6170 if (kthread_should_stop())
6173 kvm_recover_nx_lpages(kvm);
6177 int kvm_mmu_post_init_vm(struct kvm *kvm)
6181 err = kvm_vm_create_worker_thread(kvm, kvm_nx_lpage_recovery_worker, 0,
6182 "kvm-nx-lpage-recovery",
6183 &kvm->arch.nx_lpage_recovery_thread);
6185 kthread_unpark(kvm->arch.nx_lpage_recovery_thread);
6190 void kvm_mmu_pre_destroy_vm(struct kvm *kvm)
6192 if (kvm->arch.nx_lpage_recovery_thread)
6193 kthread_stop(kvm->arch.nx_lpage_recovery_thread);