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KVM: x86/mmu: Ignore CR0 and CR4 bits in nested EPT MMU role
authorSean Christopherson <seanjc@google.com>
Tue, 22 Jun 2021 17:57:07 +0000 (10:57 -0700)
committerPaolo Bonzini <pbonzini@redhat.com>
Thu, 24 Jun 2021 22:00:40 +0000 (18:00 -0400)
commitcd6767c334b628cf566db56c778e67f7e6ae2845
tree6ae85477967b61494dc02a4f503ee21e3d90ba89tree | snapshot
parentaf098972295aab280b362090aef964d4eb89f63fcommit | diff
KVM: x86/mmu: Ignore CR0 and CR4 bits in nested EPT MMU role

Do not incorporate CR0/CR4 bits into the role for the nested EPT MMU, as
EPT behavior is not influenced by CR0/CR4.  Note, this is the guest_mmu,
(L1's EPT), not nested_mmu (L2's IA32 paging); the nested_mmu does need
CR0/CR4, and is initialized in a separate flow.

Signed-off-by: Sean Christopherson <seanjc@google.com>
Message-Id: <20210622175739.3610207-23-seanjc@google.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
arch/x86/kvm/mmu/mmu.c diff | blob | history
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