1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Low-level exception handling code
5 * Copyright (C) 2012 ARM Ltd.
6 * Authors: Catalin Marinas <catalin.marinas@arm.com>
7 * Will Deacon <will.deacon@arm.com>
10 #include <linux/arm-smccc.h>
11 #include <linux/init.h>
12 #include <linux/linkage.h>
14 #include <asm/alternative.h>
15 #include <asm/assembler.h>
16 #include <asm/asm-offsets.h>
17 #include <asm/asm_pointer_auth.h>
19 #include <asm/cpufeature.h>
20 #include <asm/errno.h>
23 #include <asm/memory.h>
25 #include <asm/processor.h>
26 #include <asm/ptrace.h>
28 #include <asm/thread_info.h>
29 #include <asm/asm-uaccess.h>
30 #include <asm/unistd.h>
33 * Context tracking and irqflag tracing need to instrument transitions between
34 * user and kernel mode.
36 .macro user_enter_irqoff
37 #if defined(CONFIG_CONTEXT_TRACKING) || defined(CONFIG_TRACE_IRQFLAGS)
43 .irp n,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29
48 .macro kernel_ventry, el:req, ht:req, regsize:req, label:req
50 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
52 alternative_if ARM64_UNMAP_KERNEL_AT_EL0
59 alternative_else_nop_endif
63 sub sp, sp, #PT_REGS_SIZE
64 #ifdef CONFIG_VMAP_STACK
66 * Test whether the SP has overflowed, without corrupting a GPR.
67 * Task and IRQ stacks are aligned so that SP & (1 << THREAD_SHIFT)
68 * should always be zero.
70 add sp, sp, x0 // sp' = sp + x0
71 sub x0, sp, x0 // x0' = sp' - x0 = (sp + x0) - x0 = sp
72 tbnz x0, #THREAD_SHIFT, 0f
73 sub x0, sp, x0 // x0'' = sp' - x0' = (sp + x0) - sp = x0
74 sub sp, sp, x0 // sp'' = sp' - x0 = (sp + x0) - x0 = sp
75 b el\el\ht\()_\regsize\()_\label
79 * Either we've just detected an overflow, or we've taken an exception
80 * while on the overflow stack. Either way, we won't return to
81 * userspace, and can clobber EL0 registers to free up GPRs.
84 /* Stash the original SP (minus PT_REGS_SIZE) in tpidr_el0. */
87 /* Recover the original x0 value and stash it in tpidrro_el0 */
91 /* Switch to the overflow stack */
92 adr_this_cpu sp, overflow_stack + OVERFLOW_STACK_SIZE, x0
95 * Check whether we were already on the overflow stack. This may happen
96 * after panic() re-enables interrupts.
98 mrs x0, tpidr_el0 // sp of interrupted context
99 sub x0, sp, x0 // delta with top of overflow stack
100 tst x0, #~(OVERFLOW_STACK_SIZE - 1) // within range?
101 b.ne __bad_stack // no? -> bad stack pointer
103 /* We were already on the overflow stack. Restore sp/x0 and carry on. */
107 b el\el\ht\()_\regsize\()_\label
110 .macro tramp_alias, dst, sym
111 mov_q \dst, TRAMP_VALIAS
112 add \dst, \dst, #(\sym - .entry.tramp.text)
116 * This macro corrupts x0-x3. It is the caller's duty to save/restore
119 .macro apply_ssbd, state, tmp1, tmp2
120 alternative_cb spectre_v4_patch_fw_mitigation_enable
121 b .L__asm_ssbd_skip\@ // Patched to NOP
123 ldr_this_cpu \tmp2, arm64_ssbd_callback_required, \tmp1
124 cbz \tmp2, .L__asm_ssbd_skip\@
125 ldr \tmp2, [tsk, #TSK_TI_FLAGS]
126 tbnz \tmp2, #TIF_SSBD, .L__asm_ssbd_skip\@
127 mov w0, #ARM_SMCCC_ARCH_WORKAROUND_2
129 alternative_cb spectre_v4_patch_fw_mitigation_conduit
130 nop // Patched to SMC/HVC #0
135 /* Check for MTE asynchronous tag check faults */
136 .macro check_mte_async_tcf, tmp, ti_flags, thread_sctlr
137 #ifdef CONFIG_ARM64_MTE
139 alternative_if_not ARM64_MTE
141 alternative_else_nop_endif
143 * Asynchronous tag check faults are only possible in ASYNC (2) or
144 * ASYM (3) modes. In each of these modes bit 1 of SCTLR_EL1.TCF0 is
145 * set, so skip the check if it is unset.
147 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
148 mrs_s \tmp, SYS_TFSRE0_EL1
149 tbz \tmp, #SYS_TFSR_EL1_TF0_SHIFT, 1f
150 /* Asynchronous TCF occurred for TTBR0 access, set the TI flag */
151 mov \tmp, #_TIF_MTE_ASYNC_FAULT
152 add \ti_flags, tsk, #TSK_TI_FLAGS
153 stset \tmp, [\ti_flags]
158 /* Clear the MTE asynchronous tag check faults */
159 .macro clear_mte_async_tcf thread_sctlr
160 #ifdef CONFIG_ARM64_MTE
161 alternative_if ARM64_MTE
162 /* See comment in check_mte_async_tcf above. */
163 tbz \thread_sctlr, #(SCTLR_EL1_TCF0_SHIFT + 1), 1f
165 msr_s SYS_TFSRE0_EL1, xzr
167 alternative_else_nop_endif
171 .macro mte_set_gcr, tmp, tmp2
172 #ifdef CONFIG_ARM64_MTE
174 * Calculate and set the exclude mask preserving
175 * the RRND (bit[16]) setting.
177 mrs_s \tmp2, SYS_GCR_EL1
178 bfxil \tmp2, \tmp, #MTE_CTRL_GCR_USER_EXCL_SHIFT, #16
179 msr_s SYS_GCR_EL1, \tmp2
183 .macro mte_set_kernel_gcr, tmp, tmp2
184 #ifdef CONFIG_KASAN_HW_TAGS
185 alternative_if_not ARM64_MTE
187 alternative_else_nop_endif
188 ldr_l \tmp, gcr_kernel_excl
190 mte_set_gcr \tmp, \tmp2
196 .macro mte_set_user_gcr, tsk, tmp, tmp2
197 #ifdef CONFIG_ARM64_MTE
198 alternative_if_not ARM64_MTE
200 alternative_else_nop_endif
201 ldr \tmp, [\tsk, #THREAD_MTE_CTRL]
203 mte_set_gcr \tmp, \tmp2
208 .macro kernel_entry, el, regsize = 64
210 mov w0, w0 // zero upper 32 bits of x0
212 stp x0, x1, [sp, #16 * 0]
213 stp x2, x3, [sp, #16 * 1]
214 stp x4, x5, [sp, #16 * 2]
215 stp x6, x7, [sp, #16 * 3]
216 stp x8, x9, [sp, #16 * 4]
217 stp x10, x11, [sp, #16 * 5]
218 stp x12, x13, [sp, #16 * 6]
219 stp x14, x15, [sp, #16 * 7]
220 stp x16, x17, [sp, #16 * 8]
221 stp x18, x19, [sp, #16 * 9]
222 stp x20, x21, [sp, #16 * 10]
223 stp x22, x23, [sp, #16 * 11]
224 stp x24, x25, [sp, #16 * 12]
225 stp x26, x27, [sp, #16 * 13]
226 stp x28, x29, [sp, #16 * 14]
231 ldr_this_cpu tsk, __entry_task, x20
235 * Ensure MDSCR_EL1.SS is clear, since we can unmask debug exceptions
238 ldr x19, [tsk, #TSK_TI_FLAGS]
239 disable_step_tsk x19, x20
241 /* Check for asynchronous tag check faults in user space */
242 ldr x0, [tsk, THREAD_SCTLR_USER]
243 check_mte_async_tcf x22, x23, x0
245 #ifdef CONFIG_ARM64_PTR_AUTH
246 alternative_if ARM64_HAS_ADDRESS_AUTH
248 * Enable IA for in-kernel PAC if the task had it disabled. Although
249 * this could be implemented with an unconditional MRS which would avoid
250 * a load, this was measured to be slower on Cortex-A75 and Cortex-A76.
252 * Install the kernel IA key only if IA was enabled in the task. If IA
253 * was disabled on kernel exit then we would have left the kernel IA
254 * installed so there is no need to install it again.
256 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
257 __ptrauth_keys_install_kernel_nosync tsk, x20, x22, x23
261 orr x0, x0, SCTLR_ELx_ENIA
265 alternative_else_nop_endif
268 apply_ssbd 1, x22, x23
270 mte_set_kernel_gcr x22, x23
274 add x21, sp, #PT_REGS_SIZE
276 .endif /* \el == 0 */
279 stp lr, x21, [sp, #S_LR]
282 * For exceptions from EL0, create a final frame record.
283 * For exceptions from EL1, create a synthetic frame record so the
284 * interrupted code shows up in the backtrace.
287 stp xzr, xzr, [sp, #S_STACKFRAME]
289 stp x29, x22, [sp, #S_STACKFRAME]
291 add x29, sp, #S_STACKFRAME
293 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
294 alternative_if_not ARM64_HAS_PAN
295 bl __swpan_entry_el\el
296 alternative_else_nop_endif
299 stp x22, x23, [sp, #S_PC]
301 /* Not in a syscall by default (el0_svc overwrites for real syscall) */
304 str w21, [sp, #S_SYSCALLNO]
308 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
309 mrs_s x20, SYS_ICC_PMR_EL1
310 str x20, [sp, #S_PMR_SAVE]
311 mov x20, #GIC_PRIO_IRQON | GIC_PRIO_PSR_I_SET
312 msr_s SYS_ICC_PMR_EL1, x20
313 alternative_else_nop_endif
315 /* Re-enable tag checking (TCO set on exception entry) */
316 #ifdef CONFIG_ARM64_MTE
317 alternative_if ARM64_MTE
319 alternative_else_nop_endif
323 * Registers that may be useful after this macro is invoked:
328 * x23 - aborted PSTATE
332 .macro kernel_exit, el
338 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
339 ldr x20, [sp, #S_PMR_SAVE]
340 msr_s SYS_ICC_PMR_EL1, x20
341 mrs_s x21, SYS_ICC_CTLR_EL1
342 tbz x21, #6, .L__skip_pmr_sync\@ // Check for ICC_CTLR_EL1.PMHE
343 dsb sy // Ensure priority change is seen by redistributor
345 alternative_else_nop_endif
347 ldp x21, x22, [sp, #S_PC] // load ELR, SPSR
349 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
350 alternative_if_not ARM64_HAS_PAN
351 bl __swpan_exit_el\el
352 alternative_else_nop_endif
356 ldr x23, [sp, #S_SP] // load return stack pointer
358 tst x22, #PSR_MODE32_BIT // native task?
361 #ifdef CONFIG_ARM64_ERRATUM_845719
362 alternative_if ARM64_WORKAROUND_845719
363 #ifdef CONFIG_PID_IN_CONTEXTIDR
364 mrs x29, contextidr_el1
365 msr contextidr_el1, x29
367 msr contextidr_el1, xzr
369 alternative_else_nop_endif
374 /* Ignore asynchronous tag check faults in the uaccess routines */
375 ldr x0, [tsk, THREAD_SCTLR_USER]
376 clear_mte_async_tcf x0
378 #ifdef CONFIG_ARM64_PTR_AUTH
379 alternative_if ARM64_HAS_ADDRESS_AUTH
381 * IA was enabled for in-kernel PAC. Disable it now if needed, or
382 * alternatively install the user's IA. All other per-task keys and
383 * SCTLR bits were updated on task switch.
385 * No kernel C function calls after this.
387 tbz x0, SCTLR_ELx_ENIA_SHIFT, 1f
388 __ptrauth_keys_install_user tsk, x0, x1, x2
392 bic x0, x0, SCTLR_ELx_ENIA
395 alternative_else_nop_endif
398 mte_set_user_gcr tsk, x0, x1
403 msr elr_el1, x21 // set up the return data
405 ldp x0, x1, [sp, #16 * 0]
406 ldp x2, x3, [sp, #16 * 1]
407 ldp x4, x5, [sp, #16 * 2]
408 ldp x6, x7, [sp, #16 * 3]
409 ldp x8, x9, [sp, #16 * 4]
410 ldp x10, x11, [sp, #16 * 5]
411 ldp x12, x13, [sp, #16 * 6]
412 ldp x14, x15, [sp, #16 * 7]
413 ldp x16, x17, [sp, #16 * 8]
414 ldp x18, x19, [sp, #16 * 9]
415 ldp x20, x21, [sp, #16 * 10]
416 ldp x22, x23, [sp, #16 * 11]
417 ldp x24, x25, [sp, #16 * 12]
418 ldp x26, x27, [sp, #16 * 13]
419 ldp x28, x29, [sp, #16 * 14]
421 add sp, sp, #PT_REGS_SIZE // restore sp
424 alternative_insn eret, nop, ARM64_UNMAP_KERNEL_AT_EL0
425 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
428 tramp_alias x30, tramp_exit_native
431 tramp_alias x30, tramp_exit_compat
435 /* Ensure any device/NC reads complete */
436 alternative_insn nop, "dmb sy", ARM64_WORKAROUND_1508412
443 #ifdef CONFIG_ARM64_SW_TTBR0_PAN
445 * Set the TTBR0 PAN bit in SPSR. When the exception is taken from
446 * EL0, there is no need to check the state of TTBR0_EL1 since
447 * accesses are always enabled.
448 * Note that the meaning of this bit differs from the ARMv8.1 PAN
449 * feature as all TTBR0_EL1 accesses are disabled, not just those to
452 SYM_CODE_START_LOCAL(__swpan_entry_el1)
454 tst x21, #TTBR_ASID_MASK // Check for the reserved ASID
455 orr x23, x23, #PSR_PAN_BIT // Set the emulated PAN in the saved SPSR
456 b.eq 1f // TTBR0 access already disabled
457 and x23, x23, #~PSR_PAN_BIT // Clear the emulated PAN in the saved SPSR
458 SYM_INNER_LABEL(__swpan_entry_el0, SYM_L_LOCAL)
459 __uaccess_ttbr0_disable x21
461 SYM_CODE_END(__swpan_entry_el1)
464 * Restore access to TTBR0_EL1. If returning to EL0, no need for SPSR
467 SYM_CODE_START_LOCAL(__swpan_exit_el1)
468 tbnz x22, #22, 1f // Skip re-enabling TTBR0 access if the PSR_PAN_BIT is set
469 __uaccess_ttbr0_enable x0, x1
470 1: and x22, x22, #~PSR_PAN_BIT // ARMv8.0 CPUs do not understand this bit
472 SYM_CODE_END(__swpan_exit_el1)
474 SYM_CODE_START_LOCAL(__swpan_exit_el0)
475 __uaccess_ttbr0_enable x0, x1
477 * Enable errata workarounds only if returning to user. The only
478 * workaround currently required for TTBR0_EL1 changes are for the
479 * Cavium erratum 27456 (broadcast TLBI instructions may cause I-cache
482 b post_ttbr_update_workaround
483 SYM_CODE_END(__swpan_exit_el0)
486 /* GPRs used by entry code */
487 tsk .req x28 // current thread_info
490 * Interrupt handling.
492 .macro gic_prio_kentry_setup, tmp:req
493 #ifdef CONFIG_ARM64_PSEUDO_NMI
494 alternative_if ARM64_HAS_IRQ_PRIO_MASKING
495 mov \tmp, #(GIC_PRIO_PSR_I_SET | GIC_PRIO_IRQON)
496 msr_s SYS_ICC_PMR_EL1, \tmp
497 alternative_else_nop_endif
506 .pushsection ".entry.text", "ax"
509 SYM_CODE_START(vectors)
510 kernel_ventry 1, t, 64, sync // Synchronous EL1t
511 kernel_ventry 1, t, 64, irq // IRQ EL1t
512 kernel_ventry 1, t, 64, fiq // FIQ EL1h
513 kernel_ventry 1, t, 64, error // Error EL1t
515 kernel_ventry 1, h, 64, sync // Synchronous EL1h
516 kernel_ventry 1, h, 64, irq // IRQ EL1h
517 kernel_ventry 1, h, 64, fiq // FIQ EL1h
518 kernel_ventry 1, h, 64, error // Error EL1h
520 kernel_ventry 0, t, 64, sync // Synchronous 64-bit EL0
521 kernel_ventry 0, t, 64, irq // IRQ 64-bit EL0
522 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
523 kernel_ventry 0, t, 64, error // Error 64-bit EL0
525 kernel_ventry 0, t, 32, sync // Synchronous 32-bit EL0
526 kernel_ventry 0, t, 32, irq // IRQ 32-bit EL0
527 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
528 kernel_ventry 0, t, 32, error // Error 32-bit EL0
529 SYM_CODE_END(vectors)
531 #ifdef CONFIG_VMAP_STACK
533 * We detected an overflow in kernel_ventry, which switched to the
534 * overflow stack. Stash the exception regs, and head to our overflow
538 /* Restore the original x0 value */
542 * Store the original GPRs to the new stack. The orginal SP (minus
543 * PT_REGS_SIZE) was stashed in tpidr_el0 by kernel_ventry.
545 sub sp, sp, #PT_REGS_SIZE
548 add x0, x0, #PT_REGS_SIZE
551 /* Stash the regs for handle_bad_stack */
557 #endif /* CONFIG_VMAP_STACK */
560 .macro entry_handler el:req, ht:req, regsize:req, label:req
561 SYM_CODE_START_LOCAL(el\el\ht\()_\regsize\()_\label)
562 kernel_entry \el, \regsize
564 bl el\el\ht\()_\regsize\()_\label\()_handler
570 SYM_CODE_END(el\el\ht\()_\regsize\()_\label)
574 * Early exception handlers
576 entry_handler 1, t, 64, sync
577 entry_handler 1, t, 64, irq
578 entry_handler 1, t, 64, fiq
579 entry_handler 1, t, 64, error
581 entry_handler 1, h, 64, sync
582 entry_handler 1, h, 64, irq
583 entry_handler 1, h, 64, fiq
584 entry_handler 1, h, 64, error
586 entry_handler 0, t, 64, sync
587 entry_handler 0, t, 64, irq
588 entry_handler 0, t, 64, fiq
589 entry_handler 0, t, 64, error
591 entry_handler 0, t, 32, sync
592 entry_handler 0, t, 32, irq
593 entry_handler 0, t, 32, fiq
594 entry_handler 0, t, 32, error
596 SYM_CODE_START_LOCAL(ret_to_kernel)
598 SYM_CODE_END(ret_to_kernel)
601 * "slow" syscall return path.
603 SYM_CODE_START_LOCAL(ret_to_user)
605 gic_prio_kentry_setup tmp=x3
606 #ifdef CONFIG_TRACE_IRQFLAGS
607 bl trace_hardirqs_off
609 ldr x19, [tsk, #TSK_TI_FLAGS]
610 and x2, x19, #_TIF_WORK_MASK
611 cbnz x2, work_pending
614 enable_step_tsk x19, x2
615 #ifdef CONFIG_GCC_PLUGIN_STACKLEAK
621 * Ok, we need to do extra processing, enter the slow path.
627 ldr x19, [tsk, #TSK_TI_FLAGS] // re-check for single-step
629 SYM_CODE_END(ret_to_user)
631 .popsection // .entry.text
633 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
635 * Exception vectors trampoline.
637 .pushsection ".entry.tramp.text", "ax"
639 // Move from tramp_pg_dir to swapper_pg_dir
640 .macro tramp_map_kernel, tmp
642 add \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
643 bic \tmp, \tmp, #USER_ASID_FLAG
645 #ifdef CONFIG_QCOM_FALKOR_ERRATUM_1003
646 alternative_if ARM64_WORKAROUND_QCOM_FALKOR_E1003
647 /* ASID already in \tmp[63:48] */
648 movk \tmp, #:abs_g2_nc:(TRAMP_VALIAS >> 12)
649 movk \tmp, #:abs_g1_nc:(TRAMP_VALIAS >> 12)
650 /* 2MB boundary containing the vectors, so we nobble the walk cache */
651 movk \tmp, #:abs_g0_nc:((TRAMP_VALIAS & ~(SZ_2M - 1)) >> 12)
655 alternative_else_nop_endif
656 #endif /* CONFIG_QCOM_FALKOR_ERRATUM_1003 */
659 // Move from swapper_pg_dir to tramp_pg_dir
660 .macro tramp_unmap_kernel, tmp
662 sub \tmp, \tmp, #TRAMP_SWAPPER_OFFSET
663 orr \tmp, \tmp, #USER_ASID_FLAG
666 * We avoid running the post_ttbr_update_workaround here because
667 * it's only needed by Cavium ThunderX, which requires KPTI to be
672 .macro tramp_ventry, regsize = 64
676 msr tpidrro_el0, x30 // Restored in kernel_ventry
679 * Defend against branch aliasing attacks by pushing a dummy
680 * entry onto the return stack and using a RET instruction to
681 * enter the full-fat kernel vectors.
687 #ifdef CONFIG_RANDOMIZE_BASE
688 adr x30, tramp_vectors + PAGE_SIZE
689 alternative_insn isb, nop, ARM64_WORKAROUND_QCOM_FALKOR_E1003
694 alternative_if_not ARM64_WORKAROUND_CAVIUM_TX2_219_PRFM
695 prfm plil1strm, [x30, #(1b - tramp_vectors)]
696 alternative_else_nop_endif
698 add x30, x30, #(1b - tramp_vectors)
703 .macro tramp_exit, regsize = 64
704 adr x30, tramp_vectors
706 tramp_unmap_kernel x30
715 SYM_CODE_START_NOALIGN(tramp_vectors)
727 SYM_CODE_END(tramp_vectors)
729 SYM_CODE_START(tramp_exit_native)
731 SYM_CODE_END(tramp_exit_native)
733 SYM_CODE_START(tramp_exit_compat)
735 SYM_CODE_END(tramp_exit_compat)
738 .popsection // .entry.tramp.text
739 #ifdef CONFIG_RANDOMIZE_BASE
740 .pushsection ".rodata", "a"
742 SYM_DATA_START(__entry_tramp_data_start)
744 SYM_DATA_END(__entry_tramp_data_start)
745 .popsection // .rodata
746 #endif /* CONFIG_RANDOMIZE_BASE */
747 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
750 * Register switch for AArch64. The callee-saved registers need to be saved
751 * and restored. On entry:
752 * x0 = previous task_struct (must be preserved across the switch)
753 * x1 = next task_struct
754 * Previous and next are guaranteed not to be the same.
757 SYM_FUNC_START(cpu_switch_to)
758 mov x10, #THREAD_CPU_CONTEXT
761 stp x19, x20, [x8], #16 // store callee-saved registers
762 stp x21, x22, [x8], #16
763 stp x23, x24, [x8], #16
764 stp x25, x26, [x8], #16
765 stp x27, x28, [x8], #16
766 stp x29, x9, [x8], #16
769 ldp x19, x20, [x8], #16 // restore callee-saved registers
770 ldp x21, x22, [x8], #16
771 ldp x23, x24, [x8], #16
772 ldp x25, x26, [x8], #16
773 ldp x27, x28, [x8], #16
774 ldp x29, x9, [x8], #16
778 ptrauth_keys_install_kernel x1, x8, x9, x10
782 SYM_FUNC_END(cpu_switch_to)
783 NOKPROBE(cpu_switch_to)
786 * This is how we return from a fork.
788 SYM_CODE_START(ret_from_fork)
790 cbz x19, 1f // not a kernel thread
793 1: get_current_task tsk
795 SYM_CODE_END(ret_from_fork)
796 NOKPROBE(ret_from_fork)
799 * void call_on_irq_stack(struct pt_regs *regs,
800 * void (*func)(struct pt_regs *));
802 * Calls func(regs) using this CPU's irq stack and shadow irq stack.
804 SYM_FUNC_START(call_on_irq_stack)
805 #ifdef CONFIG_SHADOW_CALL_STACK
806 stp scs_sp, xzr, [sp, #-16]!
807 ldr_this_cpu scs_sp, irq_shadow_call_stack_ptr, x17
809 /* Create a frame record to save our LR and SP (implicit in FP) */
810 stp x29, x30, [sp, #-16]!
813 ldr_this_cpu x16, irq_stack_ptr, x17
814 mov x15, #IRQ_STACK_SIZE
817 /* Move to the new stack and call the function there */
822 * Restore the SP from the FP, and restore the FP and LR from the frame
826 ldp x29, x30, [sp], #16
827 #ifdef CONFIG_SHADOW_CALL_STACK
828 ldp scs_sp, xzr, [sp], #16
831 SYM_FUNC_END(call_on_irq_stack)
832 NOKPROBE(call_on_irq_stack)
834 #ifdef CONFIG_ARM_SDE_INTERFACE
836 #include <asm/sdei.h>
837 #include <uapi/linux/arm_sdei.h>
839 .macro sdei_handler_exit exit_mode
840 /* On success, this call never returns... */
841 cmp \exit_mode, #SDEI_EXIT_SMC
849 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
851 * The regular SDEI entry point may have been unmapped along with the rest of
852 * the kernel. This trampoline restores the kernel mapping to make the x1 memory
853 * argument accessible.
855 * This clobbers x4, __sdei_handler() will restore this from firmware's
859 .pushsection ".entry.tramp.text", "ax"
860 SYM_CODE_START(__sdei_asm_entry_trampoline)
862 tbz x4, #USER_ASID_BIT, 1f
864 tramp_map_kernel tmp=x4
869 * Remember whether to unmap the kernel on exit.
871 1: str x4, [x1, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
873 #ifdef CONFIG_RANDOMIZE_BASE
874 adr x4, tramp_vectors + PAGE_SIZE
875 add x4, x4, #:lo12:__sdei_asm_trampoline_next_handler
878 ldr x4, =__sdei_asm_handler
881 SYM_CODE_END(__sdei_asm_entry_trampoline)
882 NOKPROBE(__sdei_asm_entry_trampoline)
885 * Make the exit call and restore the original ttbr1_el1
887 * x0 & x1: setup for the exit API call
889 * x4: struct sdei_registered_event argument from registration time.
891 SYM_CODE_START(__sdei_asm_exit_trampoline)
892 ldr x4, [x4, #(SDEI_EVENT_INTREGS + S_SDEI_TTBR1)]
895 tramp_unmap_kernel tmp=x4
897 1: sdei_handler_exit exit_mode=x2
898 SYM_CODE_END(__sdei_asm_exit_trampoline)
899 NOKPROBE(__sdei_asm_exit_trampoline)
901 .popsection // .entry.tramp.text
902 #ifdef CONFIG_RANDOMIZE_BASE
903 .pushsection ".rodata", "a"
904 SYM_DATA_START(__sdei_asm_trampoline_next_handler)
905 .quad __sdei_asm_handler
906 SYM_DATA_END(__sdei_asm_trampoline_next_handler)
907 .popsection // .rodata
908 #endif /* CONFIG_RANDOMIZE_BASE */
909 #endif /* CONFIG_UNMAP_KERNEL_AT_EL0 */
912 * Software Delegated Exception entry point.
915 * x1: struct sdei_registered_event argument from registration time.
917 * x3: interrupted PSTATE
918 * x4: maybe clobbered by the trampoline
920 * Firmware has preserved x0->x17 for us, we must save/restore the rest to
921 * follow SMC-CC. We save (or retrieve) all the registers as the handler may
924 SYM_CODE_START(__sdei_asm_handler)
925 stp x2, x3, [x1, #SDEI_EVENT_INTREGS + S_PC]
926 stp x4, x5, [x1, #SDEI_EVENT_INTREGS + 16 * 2]
927 stp x6, x7, [x1, #SDEI_EVENT_INTREGS + 16 * 3]
928 stp x8, x9, [x1, #SDEI_EVENT_INTREGS + 16 * 4]
929 stp x10, x11, [x1, #SDEI_EVENT_INTREGS + 16 * 5]
930 stp x12, x13, [x1, #SDEI_EVENT_INTREGS + 16 * 6]
931 stp x14, x15, [x1, #SDEI_EVENT_INTREGS + 16 * 7]
932 stp x16, x17, [x1, #SDEI_EVENT_INTREGS + 16 * 8]
933 stp x18, x19, [x1, #SDEI_EVENT_INTREGS + 16 * 9]
934 stp x20, x21, [x1, #SDEI_EVENT_INTREGS + 16 * 10]
935 stp x22, x23, [x1, #SDEI_EVENT_INTREGS + 16 * 11]
936 stp x24, x25, [x1, #SDEI_EVENT_INTREGS + 16 * 12]
937 stp x26, x27, [x1, #SDEI_EVENT_INTREGS + 16 * 13]
938 stp x28, x29, [x1, #SDEI_EVENT_INTREGS + 16 * 14]
940 stp lr, x4, [x1, #SDEI_EVENT_INTREGS + S_LR]
944 #if defined(CONFIG_VMAP_STACK) || defined(CONFIG_SHADOW_CALL_STACK)
945 ldrb w4, [x19, #SDEI_EVENT_PRIORITY]
948 #ifdef CONFIG_VMAP_STACK
950 * entry.S may have been using sp as a scratch register, find whether
951 * this is a normal or critical event and switch to the appropriate
952 * stack for this CPU.
955 ldr_this_cpu dst=x5, sym=sdei_stack_normal_ptr, tmp=x6
957 1: ldr_this_cpu dst=x5, sym=sdei_stack_critical_ptr, tmp=x6
958 2: mov x6, #SDEI_STACK_SIZE
963 #ifdef CONFIG_SHADOW_CALL_STACK
964 /* Use a separate shadow call stack for normal and critical events */
966 ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_normal_ptr, tmp=x6
968 3: ldr_this_cpu dst=scs_sp, sym=sdei_shadow_call_stack_critical_ptr, tmp=x6
973 * We may have interrupted userspace, or a guest, or exit-from or
974 * return-to either of these. We can't trust sp_el0, restore it.
977 ldr_this_cpu dst=x0, sym=__entry_task, tmp=x1
980 /* If we interrupted the kernel point to the previous stack/frame. */
984 csel x29, x29, xzr, eq // fp, or zero
985 csel x4, x2, xzr, eq // elr, or zero
987 stp x29, x4, [sp, #-16]!
990 add x0, x19, #SDEI_EVENT_INTREGS
995 /* restore regs >x17 that we clobbered */
996 mov x4, x19 // keep x4 for __sdei_asm_exit_trampoline
997 ldp x28, x29, [x4, #SDEI_EVENT_INTREGS + 16 * 14]
998 ldp x18, x19, [x4, #SDEI_EVENT_INTREGS + 16 * 9]
999 ldp lr, x1, [x4, #SDEI_EVENT_INTREGS + S_LR]
1002 mov x1, x0 // address to complete_and_resume
1003 /* x0 = (x0 <= 1) ? EVENT_COMPLETE:EVENT_COMPLETE_AND_RESUME */
1005 mov_q x2, SDEI_1_0_FN_SDEI_EVENT_COMPLETE
1006 mov_q x3, SDEI_1_0_FN_SDEI_EVENT_COMPLETE_AND_RESUME
1009 ldr_l x2, sdei_exit_mode
1011 alternative_if_not ARM64_UNMAP_KERNEL_AT_EL0
1012 sdei_handler_exit exit_mode=x2
1013 alternative_else_nop_endif
1015 #ifdef CONFIG_UNMAP_KERNEL_AT_EL0
1016 tramp_alias dst=x5, sym=__sdei_asm_exit_trampoline
1019 SYM_CODE_END(__sdei_asm_handler)
1020 NOKPROBE(__sdei_asm_handler)
1021 #endif /* CONFIG_ARM_SDE_INTERFACE */