arch/arm64/boot/dts/rockchip/rk3399.dtsi

   1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
   2 /*
   3  * Copyright (c) 2016 Fuzhou Rockchip Electronics Co., Ltd
   4  */
   5
   6 #include <dt-bindings/clock/rk3399-cru.h>
   7 #include <dt-bindings/gpio/gpio.h>
   8 #include <dt-bindings/interrupt-controller/arm-gic.h>
   9 #include <dt-bindings/interrupt-controller/irq.h>
  10 #include <dt-bindings/pinctrl/rockchip.h>
  11 #include <dt-bindings/power/rk3399-power.h>
  12 #include <dt-bindings/thermal/thermal.h>
  13
  14 / {
  15         compatible = "rockchip,rk3399";
  16
  17         interrupt-parent = <&gic>;
  18         #address-cells = <2>;
  19         #size-cells = <2>;
  20
  21         aliases {
  22                 ethernet0 = &gmac;
  23                 i2c0 = &i2c0;
  24                 i2c1 = &i2c1;
  25                 i2c2 = &i2c2;
  26                 i2c3 = &i2c3;
  27                 i2c4 = &i2c4;
  28                 i2c5 = &i2c5;
  29                 i2c6 = &i2c6;
  30                 i2c7 = &i2c7;
  31                 i2c8 = &i2c8;
  32                 mmc0 = &sdio0;
  33                 mmc1 = &sdmmc;
  34                 mmc2 = &sdhci;
  35                 serial0 = &uart0;
  36                 serial1 = &uart1;
  37                 serial2 = &uart2;
  38                 serial3 = &uart3;
  39                 serial4 = &uart4;
  40         };
  41
  42         cpus {
  43                 #address-cells = <2>;
  44                 #size-cells = <0>;
  45
  46                 cpu-map {
  47                         cluster0 {
  48                                 core0 {
  49                                         cpu = <&cpu_l0>;
  50                                 };
  51                                 core1 {
  52                                         cpu = <&cpu_l1>;
  53                                 };
  54                                 core2 {
  55                                         cpu = <&cpu_l2>;
  56                                 };
  57                                 core3 {
  58                                         cpu = <&cpu_l3>;
  59                                 };
  60                         };
  61
  62                         cluster1 {
  63                                 core0 {
  64                                         cpu = <&cpu_b0>;
  65                                 };
  66                                 core1 {
  67                                         cpu = <&cpu_b1>;
  68                                 };
  69                         };
  70                 };
  71
  72                 cpu_l0: cpu@0 {
  73                         device_type = "cpu";
  74                         compatible = "arm,cortex-a53";
  75                         reg = <0x0 0x0>;
  76                         enable-method = "psci";
  77                         capacity-dmips-mhz = <485>;
  78                         clocks = <&cru ARMCLKL>;
  79                         #cooling-cells = <2>; /* min followed by max */
  80                         dynamic-power-coefficient = <100>;
  81                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  82                 };
  83
  84                 cpu_l1: cpu@1 {
  85                         device_type = "cpu";
  86                         compatible = "arm,cortex-a53";
  87                         reg = <0x0 0x1>;
  88                         enable-method = "psci";
  89                         capacity-dmips-mhz = <485>;
  90                         clocks = <&cru ARMCLKL>;
  91                         #cooling-cells = <2>; /* min followed by max */
  92                         dynamic-power-coefficient = <100>;
  93                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
  94                 };
  95
  96                 cpu_l2: cpu@2 {
  97                         device_type = "cpu";
  98                         compatible = "arm,cortex-a53";
  99                         reg = <0x0 0x2>;
 100                         enable-method = "psci";
 101                         capacity-dmips-mhz = <485>;
 102                         clocks = <&cru ARMCLKL>;
 103                         #cooling-cells = <2>; /* min followed by max */
 104                         dynamic-power-coefficient = <100>;
 105                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 106                 };
 107
 108                 cpu_l3: cpu@3 {
 109                         device_type = "cpu";
 110                         compatible = "arm,cortex-a53";
 111                         reg = <0x0 0x3>;
 112                         enable-method = "psci";
 113                         capacity-dmips-mhz = <485>;
 114                         clocks = <&cru ARMCLKL>;
 115                         #cooling-cells = <2>; /* min followed by max */
 116                         dynamic-power-coefficient = <100>;
 117                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 118                 };
 119
 120                 cpu_b0: cpu@100 {
 121                         device_type = "cpu";
 122                         compatible = "arm,cortex-a72";
 123                         reg = <0x0 0x100>;
 124                         enable-method = "psci";
 125                         capacity-dmips-mhz = <1024>;
 126                         clocks = <&cru ARMCLKB>;
 127                         #cooling-cells = <2>; /* min followed by max */
 128                         dynamic-power-coefficient = <436>;
 129                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 130                 };
 131
 132                 cpu_b1: cpu@101 {
 133                         device_type = "cpu";
 134                         compatible = "arm,cortex-a72";
 135                         reg = <0x0 0x101>;
 136                         enable-method = "psci";
 137                         capacity-dmips-mhz = <1024>;
 138                         clocks = <&cru ARMCLKB>;
 139                         #cooling-cells = <2>; /* min followed by max */
 140                         dynamic-power-coefficient = <436>;
 141                         cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP>;
 142                 };
 143
 144                 idle-states {
 145                         entry-method = "psci";
 146
 147                         CPU_SLEEP: cpu-sleep {
 148                                 compatible = "arm,idle-state";
 149                                 local-timer-stop;
 150                                 arm,psci-suspend-param = <0x0010000>;
 151                                 entry-latency-us = <120>;
 152                                 exit-latency-us = <250>;
 153                                 min-residency-us = <900>;
 154                         };
 155
 156                         CLUSTER_SLEEP: cluster-sleep {
 157                                 compatible = "arm,idle-state";
 158                                 local-timer-stop;
 159                                 arm,psci-suspend-param = <0x1010000>;
 160                                 entry-latency-us = <400>;
 161                                 exit-latency-us = <500>;
 162                                 min-residency-us = <2000>;
 163                         };
 164                 };
 165         };
 166
 167         display-subsystem {
 168                 compatible = "rockchip,display-subsystem";
 169                 ports = <&vopl_out>, <&vopb_out>;
 170         };
 171
 172         pmu_a53 {
 173                 compatible = "arm,cortex-a53-pmu";
 174                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster0>;
 175         };
 176
 177         pmu_a72 {
 178                 compatible = "arm,cortex-a72-pmu";
 179                 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW &ppi_cluster1>;
 180         };
 181
 182         psci {
 183                 compatible = "arm,psci-1.0";
 184                 method = "smc";
 185         };
 186
 187         timer {
 188                 compatible = "arm,armv8-timer";
 189                 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW 0>,
 190                              <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW 0>,
 191                              <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW 0>,
 192                              <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW 0>;
 193                 arm,no-tick-in-suspend;
 194         };
 195
 196         xin24m: xin24m {
 197                 compatible = "fixed-clock";
 198                 clock-frequency = <24000000>;
 199                 clock-output-names = "xin24m";
 200                 #clock-cells = <0>;
 201         };
 202
 203         pcie0: pcie@f8000000 {
 204                 compatible = "rockchip,rk3399-pcie";
 205                 reg = <0x0 0xf8000000 0x0 0x2000000>,
 206                       <0x0 0xfd000000 0x0 0x1000000>;
 207                 reg-names = "axi-base", "apb-base";
 208                 device_type = "pci";
 209                 #address-cells = <3>;
 210                 #size-cells = <2>;
 211                 #interrupt-cells = <1>;
 212                 aspm-no-l0s;
 213                 bus-range = <0x0 0x1f>;
 214                 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
 215                          <&cru PCLK_PCIE>, <&cru SCLK_PCIE_PM>;
 216                 clock-names = "aclk", "aclk-perf",
 217                               "hclk", "pm";
 218                 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH 0>,
 219                              <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH 0>,
 220                              <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH 0>;
 221                 interrupt-names = "sys", "legacy", "client";
 222                 interrupt-map-mask = <0 0 0 7>;
 223                 interrupt-map = <0 0 0 1 &pcie0_intc 0>,
 224                                 <0 0 0 2 &pcie0_intc 1>,
 225                                 <0 0 0 3 &pcie0_intc 2>,
 226                                 <0 0 0 4 &pcie0_intc 3>;
 227                 max-link-speed = <1>;
 228                 msi-map = <0x0 &its 0x0 0x1000>;
 229                 phys = <&pcie_phy 0>, <&pcie_phy 1>,
 230                        <&pcie_phy 2>, <&pcie_phy 3>;
 231                 phy-names = "pcie-phy-0", "pcie-phy-1",
 232                             "pcie-phy-2", "pcie-phy-3";
 233                 ranges = <0x83000000 0x0 0xfa000000 0x0 0xfa000000 0x0 0x1e00000>,
 234                          <0x81000000 0x0 0xfbe00000 0x0 0xfbe00000 0x0 0x100000>;
 235                 resets = <&cru SRST_PCIE_CORE>, <&cru SRST_PCIE_MGMT>,
 236                          <&cru SRST_PCIE_MGMT_STICKY>, <&cru SRST_PCIE_PIPE>,
 237                          <&cru SRST_PCIE_PM>, <&cru SRST_P_PCIE>,
 238                          <&cru SRST_A_PCIE>;
 239                 reset-names = "core", "mgmt", "mgmt-sticky", "pipe",
 240                               "pm", "pclk", "aclk";
 241                 status = "disabled";
 242
 243                 pcie0_intc: interrupt-controller {
 244                         interrupt-controller;
 245                         #address-cells = <0>;
 246                         #interrupt-cells = <1>;
 247                 };
 248         };
 249
 250         gmac: ethernet@fe300000 {
 251                 compatible = "rockchip,rk3399-gmac";
 252                 reg = <0x0 0xfe300000 0x0 0x10000>;
 253                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH 0>;
 254                 interrupt-names = "macirq";
 255                 clocks = <&cru SCLK_MAC>, <&cru SCLK_MAC_RX>,
 256                          <&cru SCLK_MAC_TX>, <&cru SCLK_MACREF>,
 257                          <&cru SCLK_MACREF_OUT>, <&cru ACLK_GMAC>,
 258                          <&cru PCLK_GMAC>;
 259                 clock-names = "stmmaceth", "mac_clk_rx",
 260                               "mac_clk_tx", "clk_mac_ref",
 261                               "clk_mac_refout", "aclk_mac",
 262                               "pclk_mac";
 263                 power-domains = <&power RK3399_PD_GMAC>;
 264                 resets = <&cru SRST_A_GMAC>;
 265                 reset-names = "stmmaceth";
 266                 rockchip,grf = <&grf>;
 267                 snps,txpbl = <0x4>;
 268                 status = "disabled";
 269         };
 270
 271         sdio0: mmc@fe310000 {
 272                 compatible = "rockchip,rk3399-dw-mshc",
 273                              "rockchip,rk3288-dw-mshc";
 274                 reg = <0x0 0xfe310000 0x0 0x4000>;
 275                 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH 0>;
 276                 max-frequency = <150000000>;
 277                 clocks = <&cru HCLK_SDIO>, <&cru SCLK_SDIO>,
 278                          <&cru SCLK_SDIO_DRV>, <&cru SCLK_SDIO_SAMPLE>;
 279                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 280                 fifo-depth = <0x100>;
 281                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 282                 resets = <&cru SRST_SDIO0>;
 283                 reset-names = "reset";
 284                 status = "disabled";
 285         };
 286
 287         sdmmc: mmc@fe320000 {
 288                 compatible = "rockchip,rk3399-dw-mshc",
 289                              "rockchip,rk3288-dw-mshc";
 290                 reg = <0x0 0xfe320000 0x0 0x4000>;
 291                 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH 0>;
 292                 max-frequency = <150000000>;
 293                 assigned-clocks = <&cru HCLK_SD>;
 294                 assigned-clock-rates = <200000000>;
 295                 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
 296                          <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
 297                 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
 298                 fifo-depth = <0x100>;
 299                 power-domains = <&power RK3399_PD_SD>;
 300                 resets = <&cru SRST_SDMMC>;
 301                 reset-names = "reset";
 302                 status = "disabled";
 303         };
 304
 305         sdhci: mmc@fe330000 {
 306                 compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 307                 reg = <0x0 0xfe330000 0x0 0x10000>;
 308                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH 0>;
 309                 arasan,soc-ctl-syscon = <&grf>;
 310                 assigned-clocks = <&cru SCLK_EMMC>;
 311                 assigned-clock-rates = <200000000>;
 312                 clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 313                 clock-names = "clk_xin", "clk_ahb";
 314                 clock-output-names = "emmc_cardclock";
 315                 #clock-cells = <0>;
 316                 phys = <&emmc_phy>;
 317                 phy-names = "phy_arasan";
 318                 power-domains = <&power RK3399_PD_EMMC>;
 319                 disable-cqe-dcmd;
 320                 status = "disabled";
 321         };
 322
 323         usb_host0_ehci: usb@fe380000 {
 324                 compatible = "generic-ehci";
 325                 reg = <0x0 0xfe380000 0x0 0x20000>;
 326                 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH 0>;
 327                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 328                          <&u2phy0>;
 329                 phys = <&u2phy0_host>;
 330                 phy-names = "usb";
 331                 status = "disabled";
 332         };
 333
 334         usb_host0_ohci: usb@fe3a0000 {
 335                 compatible = "generic-ohci";
 336                 reg = <0x0 0xfe3a0000 0x0 0x20000>;
 337                 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH 0>;
 338                 clocks = <&cru HCLK_HOST0>, <&cru HCLK_HOST0_ARB>,
 339                          <&u2phy0>;
 340                 phys = <&u2phy0_host>;
 341                 phy-names = "usb";
 342                 status = "disabled";
 343         };
 344
 345         usb_host1_ehci: usb@fe3c0000 {
 346                 compatible = "generic-ehci";
 347                 reg = <0x0 0xfe3c0000 0x0 0x20000>;
 348                 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>;
 349                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 350                          <&u2phy1>;
 351                 phys = <&u2phy1_host>;
 352                 phy-names = "usb";
 353                 status = "disabled";
 354         };
 355
 356         usb_host1_ohci: usb@fe3e0000 {
 357                 compatible = "generic-ohci";
 358                 reg = <0x0 0xfe3e0000 0x0 0x20000>;
 359                 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH 0>;
 360                 clocks = <&cru HCLK_HOST1>, <&cru HCLK_HOST1_ARB>,
 361                          <&u2phy1>;
 362                 phys = <&u2phy1_host>;
 363                 phy-names = "usb";
 364                 status = "disabled";
 365         };
 366
 367         usbdrd3_0: usb@fe800000 {
 368                 compatible = "rockchip,rk3399-dwc3";
 369                 #address-cells = <2>;
 370                 #size-cells = <2>;
 371                 ranges;
 372                 clocks = <&cru SCLK_USB3OTG0_REF>, <&cru SCLK_USB3OTG0_SUSPEND>,
 373                          <&cru ACLK_USB3OTG0>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 374                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 375                 clock-names = "ref_clk", "suspend_clk",
 376                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 377                               "aclk_usb3", "grf_clk";
 378                 resets = <&cru SRST_A_USB3_OTG0>;
 379                 reset-names = "usb3-otg";
 380                 status = "disabled";
 381
 382                 usbdrd_dwc3_0: usb@fe800000 {
 383                         compatible = "snps,dwc3";
 384                         reg = <0x0 0xfe800000 0x0 0x100000>;
 385                         interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH 0>;
 386                         clocks = <&cru SCLK_USB3OTG0_REF>, <&cru ACLK_USB3OTG0>,
 387                                  <&cru SCLK_USB3OTG0_SUSPEND>;
 388                         clock-names = "ref", "bus_early", "suspend";
 389                         dr_mode = "otg";
 390                         phys = <&u2phy0_otg>, <&tcphy0_usb3>;
 391                         phy-names = "usb2-phy", "usb3-phy";
 392                         phy_type = "utmi_wide";
 393                         snps,dis_enblslpm_quirk;
 394                         snps,dis-u2-freeclk-exists-quirk;
 395                         snps,dis_u2_susphy_quirk;
 396                         snps,dis-del-phy-power-chg-quirk;
 397                         snps,dis-tx-ipgap-linecheck-quirk;
 398                         power-domains = <&power RK3399_PD_USB3>;
 399                         status = "disabled";
 400                 };
 401         };
 402
 403         usbdrd3_1: usb@fe900000 {
 404                 compatible = "rockchip,rk3399-dwc3";
 405                 #address-cells = <2>;
 406                 #size-cells = <2>;
 407                 ranges;
 408                 clocks = <&cru SCLK_USB3OTG1_REF>, <&cru SCLK_USB3OTG1_SUSPEND>,
 409                          <&cru ACLK_USB3OTG1>, <&cru ACLK_USB3_RKSOC_AXI_PERF>,
 410                          <&cru ACLK_USB3>, <&cru ACLK_USB3_GRF>;
 411                 clock-names = "ref_clk", "suspend_clk",
 412                               "bus_clk", "aclk_usb3_rksoc_axi_perf",
 413                               "aclk_usb3", "grf_clk";
 414                 resets = <&cru SRST_A_USB3_OTG1>;
 415                 reset-names = "usb3-otg";
 416                 status = "disabled";
 417
 418                 usbdrd_dwc3_1: usb@fe900000 {
 419                         compatible = "snps,dwc3";
 420                         reg = <0x0 0xfe900000 0x0 0x100000>;
 421                         interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>;
 422                         clocks = <&cru SCLK_USB3OTG1_REF>, <&cru ACLK_USB3OTG1>,
 423                                  <&cru SCLK_USB3OTG1_SUSPEND>;
 424                         clock-names = "ref", "bus_early", "suspend";
 425                         dr_mode = "otg";
 426                         phys = <&u2phy1_otg>, <&tcphy1_usb3>;
 427                         phy-names = "usb2-phy", "usb3-phy";
 428                         phy_type = "utmi_wide";
 429                         snps,dis_enblslpm_quirk;
 430                         snps,dis-u2-freeclk-exists-quirk;
 431                         snps,dis_u2_susphy_quirk;
 432                         snps,dis-del-phy-power-chg-quirk;
 433                         snps,dis-tx-ipgap-linecheck-quirk;
 434                         power-domains = <&power RK3399_PD_USB3>;
 435                         status = "disabled";
 436                 };
 437         };
 438
 439         cdn_dp: dp@fec00000 {
 440                 compatible = "rockchip,rk3399-cdn-dp";
 441                 reg = <0x0 0xfec00000 0x0 0x100000>;
 442                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 443                 assigned-clocks = <&cru SCLK_DP_CORE>, <&cru SCLK_SPDIF_REC_DPTX>;
 444                 assigned-clock-rates = <100000000>, <200000000>;
 445                 clocks = <&cru SCLK_DP_CORE>, <&cru PCLK_DP_CTRL>,
 446                          <&cru SCLK_SPDIF_REC_DPTX>, <&cru PCLK_VIO_GRF>;
 447                 clock-names = "core-clk", "pclk", "spdif", "grf";
 448                 phys = <&tcphy0_dp>, <&tcphy1_dp>;
 449                 power-domains = <&power RK3399_PD_HDCP>;
 450                 resets = <&cru SRST_DPTX_SPDIF_REC>, <&cru SRST_P_UPHY0_DPTX>,
 451                          <&cru SRST_P_UPHY0_APB>, <&cru SRST_DP_CORE>;
 452                 reset-names = "spdif", "dptx", "apb", "core";
 453                 rockchip,grf = <&grf>;
 454                 #sound-dai-cells = <1>;
 455                 status = "disabled";
 456
 457                 ports {
 458                         dp_in: port {
 459                                 #address-cells = <1>;
 460                                 #size-cells = <0>;
 461
 462                                 dp_in_vopb: endpoint@0 {
 463                                         reg = <0>;
 464                                         remote-endpoint = <&vopb_out_dp>;
 465                                 };
 466
 467                                 dp_in_vopl: endpoint@1 {
 468                                         reg = <1>;
 469                                         remote-endpoint = <&vopl_out_dp>;
 470                                 };
 471                         };
 472                 };
 473         };
 474
 475         gic: interrupt-controller@fee00000 {
 476                 compatible = "arm,gic-v3";
 477                 #interrupt-cells = <4>;
 478                 #address-cells = <2>;
 479                 #size-cells = <2>;
 480                 ranges;
 481                 interrupt-controller;
 482
 483                 reg = <0x0 0xfee00000 0 0x10000>, /* GICD */
 484                       <0x0 0xfef00000 0 0xc0000>, /* GICR */
 485                       <0x0 0xfff00000 0 0x10000>, /* GICC */
 486                       <0x0 0xfff10000 0 0x10000>, /* GICH */
 487                       <0x0 0xfff20000 0 0x10000>; /* GICV */
 488                 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
 489                 its: interrupt-controller@fee20000 {
 490                         compatible = "arm,gic-v3-its";
 491                         msi-controller;
 492                         #msi-cells = <1>;
 493                         reg = <0x0 0xfee20000 0x0 0x20000>;
 494                 };
 495
 496                 ppi-partitions {
 497                         ppi_cluster0: interrupt-partition-0 {
 498                                 affinity = <&cpu_l0 &cpu_l1 &cpu_l2 &cpu_l3>;
 499                         };
 500
 501                         ppi_cluster1: interrupt-partition-1 {
 502                                 affinity = <&cpu_b0 &cpu_b1>;
 503                         };
 504                 };
 505         };
 506
 507         saradc: saradc@ff100000 {
 508                 compatible = "rockchip,rk3399-saradc";
 509                 reg = <0x0 0xff100000 0x0 0x100>;
 510                 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH 0>;
 511                 #io-channel-cells = <1>;
 512                 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
 513                 clock-names = "saradc", "apb_pclk";
 514                 resets = <&cru SRST_P_SARADC>;
 515                 reset-names = "saradc-apb";
 516                 status = "disabled";
 517         };
 518
 519         i2c1: i2c@ff110000 {
 520                 compatible = "rockchip,rk3399-i2c";
 521                 reg = <0x0 0xff110000 0x0 0x1000>;
 522                 assigned-clocks = <&cru SCLK_I2C1>;
 523                 assigned-clock-rates = <200000000>;
 524                 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
 525                 clock-names = "i2c", "pclk";
 526                 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH 0>;
 527                 pinctrl-names = "default";
 528                 pinctrl-0 = <&i2c1_xfer>;
 529                 #address-cells = <1>;
 530                 #size-cells = <0>;
 531                 status = "disabled";
 532         };
 533
 534         i2c2: i2c@ff120000 {
 535                 compatible = "rockchip,rk3399-i2c";
 536                 reg = <0x0 0xff120000 0x0 0x1000>;
 537                 assigned-clocks = <&cru SCLK_I2C2>;
 538                 assigned-clock-rates = <200000000>;
 539                 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
 540                 clock-names = "i2c", "pclk";
 541                 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH 0>;
 542                 pinctrl-names = "default";
 543                 pinctrl-0 = <&i2c2_xfer>;
 544                 #address-cells = <1>;
 545                 #size-cells = <0>;
 546                 status = "disabled";
 547         };
 548
 549         i2c3: i2c@ff130000 {
 550                 compatible = "rockchip,rk3399-i2c";
 551                 reg = <0x0 0xff130000 0x0 0x1000>;
 552                 assigned-clocks = <&cru SCLK_I2C3>;
 553                 assigned-clock-rates = <200000000>;
 554                 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
 555                 clock-names = "i2c", "pclk";
 556                 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH 0>;
 557                 pinctrl-names = "default";
 558                 pinctrl-0 = <&i2c3_xfer>;
 559                 #address-cells = <1>;
 560                 #size-cells = <0>;
 561                 status = "disabled";
 562         };
 563
 564         i2c5: i2c@ff140000 {
 565                 compatible = "rockchip,rk3399-i2c";
 566                 reg = <0x0 0xff140000 0x0 0x1000>;
 567                 assigned-clocks = <&cru SCLK_I2C5>;
 568                 assigned-clock-rates = <200000000>;
 569                 clocks = <&cru SCLK_I2C5>, <&cru PCLK_I2C5>;
 570                 clock-names = "i2c", "pclk";
 571                 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH 0>;
 572                 pinctrl-names = "default";
 573                 pinctrl-0 = <&i2c5_xfer>;
 574                 #address-cells = <1>;
 575                 #size-cells = <0>;
 576                 status = "disabled";
 577         };
 578
 579         i2c6: i2c@ff150000 {
 580                 compatible = "rockchip,rk3399-i2c";
 581                 reg = <0x0 0xff150000 0x0 0x1000>;
 582                 assigned-clocks = <&cru SCLK_I2C6>;
 583                 assigned-clock-rates = <200000000>;
 584                 clocks = <&cru SCLK_I2C6>, <&cru PCLK_I2C6>;
 585                 clock-names = "i2c", "pclk";
 586                 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH 0>;
 587                 pinctrl-names = "default";
 588                 pinctrl-0 = <&i2c6_xfer>;
 589                 #address-cells = <1>;
 590                 #size-cells = <0>;
 591                 status = "disabled";
 592         };
 593
 594         i2c7: i2c@ff160000 {
 595                 compatible = "rockchip,rk3399-i2c";
 596                 reg = <0x0 0xff160000 0x0 0x1000>;
 597                 assigned-clocks = <&cru SCLK_I2C7>;
 598                 assigned-clock-rates = <200000000>;
 599                 clocks = <&cru SCLK_I2C7>, <&cru PCLK_I2C7>;
 600                 clock-names = "i2c", "pclk";
 601                 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH 0>;
 602                 pinctrl-names = "default";
 603                 pinctrl-0 = <&i2c7_xfer>;
 604                 #address-cells = <1>;
 605                 #size-cells = <0>;
 606                 status = "disabled";
 607         };
 608
 609         uart0: serial@ff180000 {
 610                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 611                 reg = <0x0 0xff180000 0x0 0x100>;
 612                 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
 613                 clock-names = "baudclk", "apb_pclk";
 614                 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH 0>;
 615                 reg-shift = <2>;
 616                 reg-io-width = <4>;
 617                 pinctrl-names = "default";
 618                 pinctrl-0 = <&uart0_xfer>;
 619                 status = "disabled";
 620         };
 621
 622         uart1: serial@ff190000 {
 623                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 624                 reg = <0x0 0xff190000 0x0 0x100>;
 625                 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
 626                 clock-names = "baudclk", "apb_pclk";
 627                 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH 0>;
 628                 reg-shift = <2>;
 629                 reg-io-width = <4>;
 630                 pinctrl-names = "default";
 631                 pinctrl-0 = <&uart1_xfer>;
 632                 status = "disabled";
 633         };
 634
 635         uart2: serial@ff1a0000 {
 636                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 637                 reg = <0x0 0xff1a0000 0x0 0x100>;
 638                 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
 639                 clock-names = "baudclk", "apb_pclk";
 640                 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH 0>;
 641                 reg-shift = <2>;
 642                 reg-io-width = <4>;
 643                 pinctrl-names = "default";
 644                 pinctrl-0 = <&uart2c_xfer>;
 645                 status = "disabled";
 646         };
 647
 648         uart3: serial@ff1b0000 {
 649                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
 650                 reg = <0x0 0xff1b0000 0x0 0x100>;
 651                 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
 652                 clock-names = "baudclk", "apb_pclk";
 653                 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH 0>;
 654                 reg-shift = <2>;
 655                 reg-io-width = <4>;
 656                 pinctrl-names = "default";
 657                 pinctrl-0 = <&uart3_xfer>;
 658                 status = "disabled";
 659         };
 660
 661         spi0: spi@ff1c0000 {
 662                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 663                 reg = <0x0 0xff1c0000 0x0 0x1000>;
 664                 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
 665                 clock-names = "spiclk", "apb_pclk";
 666                 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH 0>;
 667                 dmas = <&dmac_peri 10>, <&dmac_peri 11>;
 668                 dma-names = "tx", "rx";
 669                 pinctrl-names = "default";
 670                 pinctrl-0 = <&spi0_clk &spi0_tx &spi0_rx &spi0_cs0>;
 671                 #address-cells = <1>;
 672                 #size-cells = <0>;
 673                 status = "disabled";
 674         };
 675
 676         spi1: spi@ff1d0000 {
 677                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 678                 reg = <0x0 0xff1d0000 0x0 0x1000>;
 679                 clocks = <&cru SCLK_SPI1>, <&cru PCLK_SPI1>;
 680                 clock-names = "spiclk", "apb_pclk";
 681                 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH 0>;
 682                 dmas = <&dmac_peri 12>, <&dmac_peri 13>;
 683                 dma-names = "tx", "rx";
 684                 pinctrl-names = "default";
 685                 pinctrl-0 = <&spi1_clk &spi1_tx &spi1_rx &spi1_cs0>;
 686                 #address-cells = <1>;
 687                 #size-cells = <0>;
 688                 status = "disabled";
 689         };
 690
 691         spi2: spi@ff1e0000 {
 692                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 693                 reg = <0x0 0xff1e0000 0x0 0x1000>;
 694                 clocks = <&cru SCLK_SPI2>, <&cru PCLK_SPI2>;
 695                 clock-names = "spiclk", "apb_pclk";
 696                 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH 0>;
 697                 dmas = <&dmac_peri 14>, <&dmac_peri 15>;
 698                 dma-names = "tx", "rx";
 699                 pinctrl-names = "default";
 700                 pinctrl-0 = <&spi2_clk &spi2_tx &spi2_rx &spi2_cs0>;
 701                 #address-cells = <1>;
 702                 #size-cells = <0>;
 703                 status = "disabled";
 704         };
 705
 706         spi4: spi@ff1f0000 {
 707                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 708                 reg = <0x0 0xff1f0000 0x0 0x1000>;
 709                 clocks = <&cru SCLK_SPI4>, <&cru PCLK_SPI4>;
 710                 clock-names = "spiclk", "apb_pclk";
 711                 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH 0>;
 712                 dmas = <&dmac_peri 18>, <&dmac_peri 19>;
 713                 dma-names = "tx", "rx";
 714                 pinctrl-names = "default";
 715                 pinctrl-0 = <&spi4_clk &spi4_tx &spi4_rx &spi4_cs0>;
 716                 #address-cells = <1>;
 717                 #size-cells = <0>;
 718                 status = "disabled";
 719         };
 720
 721         spi5: spi@ff200000 {
 722                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
 723                 reg = <0x0 0xff200000 0x0 0x1000>;
 724                 clocks = <&cru SCLK_SPI5>, <&cru PCLK_SPI5>;
 725                 clock-names = "spiclk", "apb_pclk";
 726                 interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH 0>;
 727                 dmas = <&dmac_bus 8>, <&dmac_bus 9>;
 728                 dma-names = "tx", "rx";
 729                 pinctrl-names = "default";
 730                 pinctrl-0 = <&spi5_clk &spi5_tx &spi5_rx &spi5_cs0>;
 731                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
 732                 #address-cells = <1>;
 733                 #size-cells = <0>;
 734                 status = "disabled";
 735         };
 736
 737         thermal_zones: thermal-zones {
 738                 cpu_thermal: cpu-thermal {
 739                         polling-delay-passive = <100>;
 740                         polling-delay = <1000>;
 741
 742                         thermal-sensors = <&tsadc 0>;
 743
 744                         trips {
 745                                 cpu_alert0: cpu_alert0 {
 746                                         temperature = <70000>;
 747                                         hysteresis = <2000>;
 748                                         type = "passive";
 749                                 };
 750                                 cpu_alert1: cpu_alert1 {
 751                                         temperature = <75000>;
 752                                         hysteresis = <2000>;
 753                                         type = "passive";
 754                                 };
 755                                 cpu_crit: cpu_crit {
 756                                         temperature = <95000>;
 757                                         hysteresis = <2000>;
 758                                         type = "critical";
 759                                 };
 760                         };
 761
 762                         cooling-maps {
 763                                 map0 {
 764                                         trip = <&cpu_alert0>;
 765                                         cooling-device =
 766                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 767                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 768                                 };
 769                                 map1 {
 770                                         trip = <&cpu_alert1>;
 771                                         cooling-device =
 772                                                 <&cpu_l0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 773                                                 <&cpu_l1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 774                                                 <&cpu_l2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 775                                                 <&cpu_l3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 776                                                 <&cpu_b0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
 777                                                 <&cpu_b1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 778                                 };
 779                         };
 780                 };
 781
 782                 gpu_thermal: gpu-thermal {
 783                         polling-delay-passive = <100>;
 784                         polling-delay = <1000>;
 785
 786                         thermal-sensors = <&tsadc 1>;
 787
 788                         trips {
 789                                 gpu_alert0: gpu_alert0 {
 790                                         temperature = <75000>;
 791                                         hysteresis = <2000>;
 792                                         type = "passive";
 793                                 };
 794                                 gpu_crit: gpu_crit {
 795                                         temperature = <95000>;
 796                                         hysteresis = <2000>;
 797                                         type = "critical";
 798                                 };
 799                         };
 800
 801                         cooling-maps {
 802                                 map0 {
 803                                         trip = <&gpu_alert0>;
 804                                         cooling-device =
 805                                                 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 806                                 };
 807                         };
 808                 };
 809         };
 810
 811         tsadc: tsadc@ff260000 {
 812                 compatible = "rockchip,rk3399-tsadc";
 813                 reg = <0x0 0xff260000 0x0 0x100>;
 814                 interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH 0>;
 815                 assigned-clocks = <&cru SCLK_TSADC>;
 816                 assigned-clock-rates = <750000>;
 817                 clocks = <&cru SCLK_TSADC>, <&cru PCLK_TSADC>;
 818                 clock-names = "tsadc", "apb_pclk";
 819                 resets = <&cru SRST_TSADC>;
 820                 reset-names = "tsadc-apb";
 821                 rockchip,grf = <&grf>;
 822                 rockchip,hw-tshut-temp = <95000>;
 823                 pinctrl-names = "init", "default", "sleep";
 824                 pinctrl-0 = <&otp_pin>;
 825                 pinctrl-1 = <&otp_out>;
 826                 pinctrl-2 = <&otp_pin>;
 827                 #thermal-sensor-cells = <1>;
 828                 status = "disabled";
 829         };
 830
 831         qos_emmc: qos@ffa58000 {
 832                 compatible = "rockchip,rk3399-qos", "syscon";
 833                 reg = <0x0 0xffa58000 0x0 0x20>;
 834         };
 835
 836         qos_gmac: qos@ffa5c000 {
 837                 compatible = "rockchip,rk3399-qos", "syscon";
 838                 reg = <0x0 0xffa5c000 0x0 0x20>;
 839         };
 840
 841         qos_pcie: qos@ffa60080 {
 842                 compatible = "rockchip,rk3399-qos", "syscon";
 843                 reg = <0x0 0xffa60080 0x0 0x20>;
 844         };
 845
 846         qos_usb_host0: qos@ffa60100 {
 847                 compatible = "rockchip,rk3399-qos", "syscon";
 848                 reg = <0x0 0xffa60100 0x0 0x20>;
 849         };
 850
 851         qos_usb_host1: qos@ffa60180 {
 852                 compatible = "rockchip,rk3399-qos", "syscon";
 853                 reg = <0x0 0xffa60180 0x0 0x20>;
 854         };
 855
 856         qos_usb_otg0: qos@ffa70000 {
 857                 compatible = "rockchip,rk3399-qos", "syscon";
 858                 reg = <0x0 0xffa70000 0x0 0x20>;
 859         };
 860
 861         qos_usb_otg1: qos@ffa70080 {
 862                 compatible = "rockchip,rk3399-qos", "syscon";
 863                 reg = <0x0 0xffa70080 0x0 0x20>;
 864         };
 865
 866         qos_sd: qos@ffa74000 {
 867                 compatible = "rockchip,rk3399-qos", "syscon";
 868                 reg = <0x0 0xffa74000 0x0 0x20>;
 869         };
 870
 871         qos_sdioaudio: qos@ffa76000 {
 872                 compatible = "rockchip,rk3399-qos", "syscon";
 873                 reg = <0x0 0xffa76000 0x0 0x20>;
 874         };
 875
 876         qos_hdcp: qos@ffa90000 {
 877                 compatible = "rockchip,rk3399-qos", "syscon";
 878                 reg = <0x0 0xffa90000 0x0 0x20>;
 879         };
 880
 881         qos_iep: qos@ffa98000 {
 882                 compatible = "rockchip,rk3399-qos", "syscon";
 883                 reg = <0x0 0xffa98000 0x0 0x20>;
 884         };
 885
 886         qos_isp0_m0: qos@ffaa0000 {
 887                 compatible = "rockchip,rk3399-qos", "syscon";
 888                 reg = <0x0 0xffaa0000 0x0 0x20>;
 889         };
 890
 891         qos_isp0_m1: qos@ffaa0080 {
 892                 compatible = "rockchip,rk3399-qos", "syscon";
 893                 reg = <0x0 0xffaa0080 0x0 0x20>;
 894         };
 895
 896         qos_isp1_m0: qos@ffaa8000 {
 897                 compatible = "rockchip,rk3399-qos", "syscon";
 898                 reg = <0x0 0xffaa8000 0x0 0x20>;
 899         };
 900
 901         qos_isp1_m1: qos@ffaa8080 {
 902                 compatible = "rockchip,rk3399-qos", "syscon";
 903                 reg = <0x0 0xffaa8080 0x0 0x20>;
 904         };
 905
 906         qos_rga_r: qos@ffab0000 {
 907                 compatible = "rockchip,rk3399-qos", "syscon";
 908                 reg = <0x0 0xffab0000 0x0 0x20>;
 909         };
 910
 911         qos_rga_w: qos@ffab0080 {
 912                 compatible = "rockchip,rk3399-qos", "syscon";
 913                 reg = <0x0 0xffab0080 0x0 0x20>;
 914         };
 915
 916         qos_video_m0: qos@ffab8000 {
 917                 compatible = "rockchip,rk3399-qos", "syscon";
 918                 reg = <0x0 0xffab8000 0x0 0x20>;
 919         };
 920
 921         qos_video_m1_r: qos@ffac0000 {
 922                 compatible = "rockchip,rk3399-qos", "syscon";
 923                 reg = <0x0 0xffac0000 0x0 0x20>;
 924         };
 925
 926         qos_video_m1_w: qos@ffac0080 {
 927                 compatible = "rockchip,rk3399-qos", "syscon";
 928                 reg = <0x0 0xffac0080 0x0 0x20>;
 929         };
 930
 931         qos_vop_big_r: qos@ffac8000 {
 932                 compatible = "rockchip,rk3399-qos", "syscon";
 933                 reg = <0x0 0xffac8000 0x0 0x20>;
 934         };
 935
 936         qos_vop_big_w: qos@ffac8080 {
 937                 compatible = "rockchip,rk3399-qos", "syscon";
 938                 reg = <0x0 0xffac8080 0x0 0x20>;
 939         };
 940
 941         qos_vop_little: qos@ffad0000 {
 942                 compatible = "rockchip,rk3399-qos", "syscon";
 943                 reg = <0x0 0xffad0000 0x0 0x20>;
 944         };
 945
 946         qos_perihp: qos@ffad8080 {
 947                 compatible = "rockchip,rk3399-qos", "syscon";
 948                 reg = <0x0 0xffad8080 0x0 0x20>;
 949         };
 950
 951         qos_gpu: qos@ffae0000 {
 952                 compatible = "rockchip,rk3399-qos", "syscon";
 953                 reg = <0x0 0xffae0000 0x0 0x20>;
 954         };
 955
 956         pmu: power-management@ff310000 {
 957                 compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 958                 reg = <0x0 0xff310000 0x0 0x1000>;
 959
 960                 /*
 961                  * Note: RK3399 supports 6 voltage domains including VD_CORE_L,
 962                  * VD_CORE_B, VD_CENTER, VD_GPU, VD_LOGIC and VD_PMU.
 963                  * Some of the power domains are grouped together for every
 964                  * voltage domain.
 965                  * The detail contents as below.
 966                  */
 967                 power: power-controller {
 968                         compatible = "rockchip,rk3399-power-controller";
 969                         #power-domain-cells = <1>;
 970                         #address-cells = <1>;
 971                         #size-cells = <0>;
 972
 973                         /* These power domains are grouped by VD_CENTER */
 974                         pd_iep@RK3399_PD_IEP {
 975                                 reg = <RK3399_PD_IEP>;
 976                                 clocks = <&cru ACLK_IEP>,
 977                                          <&cru HCLK_IEP>;
 978                                 pm_qos = <&qos_iep>;
 979                         };
 980                         pd_rga@RK3399_PD_RGA {
 981                                 reg = <RK3399_PD_RGA>;
 982                                 clocks = <&cru ACLK_RGA>,
 983                                          <&cru HCLK_RGA>;
 984                                 pm_qos = <&qos_rga_r>,
 985                                          <&qos_rga_w>;
 986                         };
 987                         pd_vcodec@RK3399_PD_VCODEC {
 988                                 reg = <RK3399_PD_VCODEC>;
 989                                 clocks = <&cru ACLK_VCODEC>,
 990                                          <&cru HCLK_VCODEC>;
 991                                 pm_qos = <&qos_video_m0>;
 992                         };
 993                         pd_vdu@RK3399_PD_VDU {
 994                                 reg = <RK3399_PD_VDU>;
 995                                 clocks = <&cru ACLK_VDU>,
 996                                          <&cru HCLK_VDU>;
 997                                 pm_qos = <&qos_video_m1_r>,
 998                                          <&qos_video_m1_w>;
 999                         };
1000
1001                         /* These power domains are grouped by VD_GPU */
1002                         pd_gpu@RK3399_PD_GPU {
1003                                 reg = <RK3399_PD_GPU>;
1004                                 clocks = <&cru ACLK_GPU>;
1005                                 pm_qos = <&qos_gpu>;
1006                         };
1007
1008                         /* These power domains are grouped by VD_LOGIC */
1009                         pd_edp@RK3399_PD_EDP {
1010                                 reg = <RK3399_PD_EDP>;
1011                                 clocks = <&cru PCLK_EDP_CTRL>;
1012                         };
1013                         pd_emmc@RK3399_PD_EMMC {
1014                                 reg = <RK3399_PD_EMMC>;
1015                                 clocks = <&cru ACLK_EMMC>;
1016                                 pm_qos = <&qos_emmc>;
1017                         };
1018                         pd_gmac@RK3399_PD_GMAC {
1019                                 reg = <RK3399_PD_GMAC>;
1020                                 clocks = <&cru ACLK_GMAC>,
1021                                          <&cru PCLK_GMAC>;
1022                                 pm_qos = <&qos_gmac>;
1023                         };
1024                         pd_sd@RK3399_PD_SD {
1025                                 reg = <RK3399_PD_SD>;
1026                                 clocks = <&cru HCLK_SDMMC>,
1027                                          <&cru SCLK_SDMMC>;
1028                                 pm_qos = <&qos_sd>;
1029                         };
1030                         pd_sdioaudio@RK3399_PD_SDIOAUDIO {
1031                                 reg = <RK3399_PD_SDIOAUDIO>;
1032                                 clocks = <&cru HCLK_SDIO>;
1033                                 pm_qos = <&qos_sdioaudio>;
1034                         };
1035                         pd_tcpc0@RK3399_PD_TCPD0 {
1036                                 reg = <RK3399_PD_TCPD0>;
1037                                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1038                                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1039                         };
1040                         pd_tcpc1@RK3399_PD_TCPD1 {
1041                                 reg = <RK3399_PD_TCPD1>;
1042                                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1043                                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1044                         };
1045                         pd_usb3@RK3399_PD_USB3 {
1046                                 reg = <RK3399_PD_USB3>;
1047                                 clocks = <&cru ACLK_USB3>;
1048                                 pm_qos = <&qos_usb_otg0>,
1049                                          <&qos_usb_otg1>;
1050                         };
1051                         pd_vio@RK3399_PD_VIO {
1052                                 reg = <RK3399_PD_VIO>;
1053                                 #address-cells = <1>;
1054                                 #size-cells = <0>;
1055
1056                                 pd_hdcp@RK3399_PD_HDCP {
1057                                         reg = <RK3399_PD_HDCP>;
1058                                         clocks = <&cru ACLK_HDCP>,
1059                                                  <&cru HCLK_HDCP>,
1060                                                  <&cru PCLK_HDCP>;
1061                                         pm_qos = <&qos_hdcp>;
1062                                 };
1063                                 pd_isp0@RK3399_PD_ISP0 {
1064                                         reg = <RK3399_PD_ISP0>;
1065                                         clocks = <&cru ACLK_ISP0>,
1066                                                  <&cru HCLK_ISP0>;
1067                                         pm_qos = <&qos_isp0_m0>,
1068                                                  <&qos_isp0_m1>;
1069                                 };
1070                                 pd_isp1@RK3399_PD_ISP1 {
1071                                         reg = <RK3399_PD_ISP1>;
1072                                         clocks = <&cru ACLK_ISP1>,
1073                                                  <&cru HCLK_ISP1>;
1074                                         pm_qos = <&qos_isp1_m0>,
1075                                                  <&qos_isp1_m1>;
1076                                 };
1077                                 pd_vo@RK3399_PD_VO {
1078                                         reg = <RK3399_PD_VO>;
1079                                         #address-cells = <1>;
1080                                         #size-cells = <0>;
1081
1082                                         pd_vopb@RK3399_PD_VOPB {
1083                                                 reg = <RK3399_PD_VOPB>;
1084                                                 clocks = <&cru ACLK_VOP0>,
1085                                                          <&cru HCLK_VOP0>;
1086                                                 pm_qos = <&qos_vop_big_r>,
1087                                                          <&qos_vop_big_w>;
1088                                         };
1089                                         pd_vopl@RK3399_PD_VOPL {
1090                                                 reg = <RK3399_PD_VOPL>;
1091                                                 clocks = <&cru ACLK_VOP1>,
1092                                                          <&cru HCLK_VOP1>;
1093                                                 pm_qos = <&qos_vop_little>;
1094                                         };
1095                                 };
1096                         };
1097                 };
1098         };
1099
1100         pmugrf: syscon@ff320000 {
1101                 compatible = "rockchip,rk3399-pmugrf", "syscon", "simple-mfd";
1102                 reg = <0x0 0xff320000 0x0 0x1000>;
1103
1104                 pmu_io_domains: io-domains {
1105                         compatible = "rockchip,rk3399-pmu-io-voltage-domain";
1106                         status = "disabled";
1107                 };
1108         };
1109
1110         spi3: spi@ff350000 {
1111                 compatible = "rockchip,rk3399-spi", "rockchip,rk3066-spi";
1112                 reg = <0x0 0xff350000 0x0 0x1000>;
1113                 clocks = <&pmucru SCLK_SPI3_PMU>, <&pmucru PCLK_SPI3_PMU>;
1114                 clock-names = "spiclk", "apb_pclk";
1115                 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH 0>;
1116                 pinctrl-names = "default";
1117                 pinctrl-0 = <&spi3_clk &spi3_tx &spi3_rx &spi3_cs0>;
1118                 #address-cells = <1>;
1119                 #size-cells = <0>;
1120                 status = "disabled";
1121         };
1122
1123         uart4: serial@ff370000 {
1124                 compatible = "rockchip,rk3399-uart", "snps,dw-apb-uart";
1125                 reg = <0x0 0xff370000 0x0 0x100>;
1126                 clocks = <&pmucru SCLK_UART4_PMU>, <&pmucru PCLK_UART4_PMU>;
1127                 clock-names = "baudclk", "apb_pclk";
1128                 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH 0>;
1129                 reg-shift = <2>;
1130                 reg-io-width = <4>;
1131                 pinctrl-names = "default";
1132                 pinctrl-0 = <&uart4_xfer>;
1133                 status = "disabled";
1134         };
1135
1136         i2c0: i2c@ff3c0000 {
1137                 compatible = "rockchip,rk3399-i2c";
1138                 reg = <0x0 0xff3c0000 0x0 0x1000>;
1139                 assigned-clocks = <&pmucru SCLK_I2C0_PMU>;
1140                 assigned-clock-rates = <200000000>;
1141                 clocks = <&pmucru SCLK_I2C0_PMU>, <&pmucru PCLK_I2C0_PMU>;
1142                 clock-names = "i2c", "pclk";
1143                 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH 0>;
1144                 pinctrl-names = "default";
1145                 pinctrl-0 = <&i2c0_xfer>;
1146                 #address-cells = <1>;
1147                 #size-cells = <0>;
1148                 status = "disabled";
1149         };
1150
1151         i2c4: i2c@ff3d0000 {
1152                 compatible = "rockchip,rk3399-i2c";
1153                 reg = <0x0 0xff3d0000 0x0 0x1000>;
1154                 assigned-clocks = <&pmucru SCLK_I2C4_PMU>;
1155                 assigned-clock-rates = <200000000>;
1156                 clocks = <&pmucru SCLK_I2C4_PMU>, <&pmucru PCLK_I2C4_PMU>;
1157                 clock-names = "i2c", "pclk";
1158                 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH 0>;
1159                 pinctrl-names = "default";
1160                 pinctrl-0 = <&i2c4_xfer>;
1161                 #address-cells = <1>;
1162                 #size-cells = <0>;
1163                 status = "disabled";
1164         };
1165
1166         i2c8: i2c@ff3e0000 {
1167                 compatible = "rockchip,rk3399-i2c";
1168                 reg = <0x0 0xff3e0000 0x0 0x1000>;
1169                 assigned-clocks = <&pmucru SCLK_I2C8_PMU>;
1170                 assigned-clock-rates = <200000000>;
1171                 clocks = <&pmucru SCLK_I2C8_PMU>, <&pmucru PCLK_I2C8_PMU>;
1172                 clock-names = "i2c", "pclk";
1173                 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH 0>;
1174                 pinctrl-names = "default";
1175                 pinctrl-0 = <&i2c8_xfer>;
1176                 #address-cells = <1>;
1177                 #size-cells = <0>;
1178                 status = "disabled";
1179         };
1180
1181         pwm0: pwm@ff420000 {
1182                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1183                 reg = <0x0 0xff420000 0x0 0x10>;
1184                 #pwm-cells = <3>;
1185                 pinctrl-names = "default";
1186                 pinctrl-0 = <&pwm0_pin>;
1187                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1188                 clock-names = "pwm";
1189                 status = "disabled";
1190         };
1191
1192         pwm1: pwm@ff420010 {
1193                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1194                 reg = <0x0 0xff420010 0x0 0x10>;
1195                 #pwm-cells = <3>;
1196                 pinctrl-names = "default";
1197                 pinctrl-0 = <&pwm1_pin>;
1198                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1199                 clock-names = "pwm";
1200                 status = "disabled";
1201         };
1202
1203         pwm2: pwm@ff420020 {
1204                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1205                 reg = <0x0 0xff420020 0x0 0x10>;
1206                 #pwm-cells = <3>;
1207                 pinctrl-names = "default";
1208                 pinctrl-0 = <&pwm2_pin>;
1209                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1210                 clock-names = "pwm";
1211                 status = "disabled";
1212         };
1213
1214         pwm3: pwm@ff420030 {
1215                 compatible = "rockchip,rk3399-pwm", "rockchip,rk3288-pwm";
1216                 reg = <0x0 0xff420030 0x0 0x10>;
1217                 #pwm-cells = <3>;
1218                 pinctrl-names = "default";
1219                 pinctrl-0 = <&pwm3a_pin>;
1220                 clocks = <&pmucru PCLK_RKPWM_PMU>;
1221                 clock-names = "pwm";
1222                 status = "disabled";
1223         };
1224
1225         vpu: video-codec@ff650000 {
1226                 compatible = "rockchip,rk3399-vpu";
1227                 reg = <0x0 0xff650000 0x0 0x800>;
1228                 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>,
1229                              <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
1230                 interrupt-names = "vepu", "vdpu";
1231                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1232                 clock-names = "aclk", "hclk";
1233                 iommus = <&vpu_mmu>;
1234                 power-domains = <&power RK3399_PD_VCODEC>;
1235         };
1236
1237         vpu_mmu: iommu@ff650800 {
1238                 compatible = "rockchip,iommu";
1239                 reg = <0x0 0xff650800 0x0 0x40>;
1240                 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
1241                 interrupt-names = "vpu_mmu";
1242                 clocks = <&cru ACLK_VCODEC>, <&cru HCLK_VCODEC>;
1243                 clock-names = "aclk", "iface";
1244                 #iommu-cells = <0>;
1245                 power-domains = <&power RK3399_PD_VCODEC>;
1246         };
1247
1248         vdec: video-codec@ff660000 {
1249                 compatible = "rockchip,rk3399-vdec";
1250                 reg = <0x0 0xff660000 0x0 0x400>;
1251                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
1252                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>,
1253                          <&cru SCLK_VDU_CA>, <&cru SCLK_VDU_CORE>;
1254                 clock-names = "axi", "ahb", "cabac", "core";
1255                 iommus = <&vdec_mmu>;
1256                 power-domains = <&power RK3399_PD_VDU>;
1257         };
1258
1259         vdec_mmu: iommu@ff660480 {
1260                 compatible = "rockchip,iommu";
1261                 reg = <0x0 0xff660480 0x0 0x40>, <0x0 0xff6604c0 0x0 0x40>;
1262                 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
1263                 interrupt-names = "vdec_mmu";
1264                 clocks = <&cru ACLK_VDU>, <&cru HCLK_VDU>;
1265                 clock-names = "aclk", "iface";
1266                 power-domains = <&power RK3399_PD_VDU>;
1267                 #iommu-cells = <0>;
1268         };
1269
1270         iep_mmu: iommu@ff670800 {
1271                 compatible = "rockchip,iommu";
1272                 reg = <0x0 0xff670800 0x0 0x40>;
1273                 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH 0>;
1274                 interrupt-names = "iep_mmu";
1275                 clocks = <&cru ACLK_IEP>, <&cru HCLK_IEP>;
1276                 clock-names = "aclk", "iface";
1277                 #iommu-cells = <0>;
1278                 status = "disabled";
1279         };
1280
1281         rga: rga@ff680000 {
1282                 compatible = "rockchip,rk3399-rga";
1283                 reg = <0x0 0xff680000 0x0 0x10000>;
1284                 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH 0>;
1285                 clocks = <&cru ACLK_RGA>, <&cru HCLK_RGA>, <&cru SCLK_RGA_CORE>;
1286                 clock-names = "aclk", "hclk", "sclk";
1287                 resets = <&cru SRST_RGA_CORE>, <&cru SRST_A_RGA>, <&cru SRST_H_RGA>;
1288                 reset-names = "core", "axi", "ahb";
1289                 power-domains = <&power RK3399_PD_RGA>;
1290         };
1291
1292         efuse0: efuse@ff690000 {
1293                 compatible = "rockchip,rk3399-efuse";
1294                 reg = <0x0 0xff690000 0x0 0x80>;
1295                 #address-cells = <1>;
1296                 #size-cells = <1>;
1297                 clocks = <&cru PCLK_EFUSE1024NS>;
1298                 clock-names = "pclk_efuse";
1299
1300                 /* Data cells */
1301                 cpu_id: cpu-id@7 {
1302                         reg = <0x07 0x10>;
1303                 };
1304                 cpub_leakage: cpu-leakage@17 {
1305                         reg = <0x17 0x1>;
1306                 };
1307                 gpu_leakage: gpu-leakage@18 {
1308                         reg = <0x18 0x1>;
1309                 };
1310                 center_leakage: center-leakage@19 {
1311                         reg = <0x19 0x1>;
1312                 };
1313                 cpul_leakage: cpu-leakage@1a {
1314                         reg = <0x1a 0x1>;
1315                 };
1316                 logic_leakage: logic-leakage@1b {
1317                         reg = <0x1b 0x1>;
1318                 };
1319                 wafer_info: wafer-info@1c {
1320                         reg = <0x1c 0x1>;
1321                 };
1322         };
1323
1324         dmac_bus: dma-controller@ff6d0000 {
1325                 compatible = "arm,pl330", "arm,primecell";
1326                 reg = <0x0 0xff6d0000 0x0 0x4000>;
1327                 interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH 0>,
1328                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH 0>;
1329                 #dma-cells = <1>;
1330                 arm,pl330-periph-burst;
1331                 clocks = <&cru ACLK_DMAC0_PERILP>;
1332                 clock-names = "apb_pclk";
1333         };
1334
1335         dmac_peri: dma-controller@ff6e0000 {
1336                 compatible = "arm,pl330", "arm,primecell";
1337                 reg = <0x0 0xff6e0000 0x0 0x4000>;
1338                 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH 0>,
1339                              <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH 0>;
1340                 #dma-cells = <1>;
1341                 arm,pl330-periph-burst;
1342                 clocks = <&cru ACLK_DMAC1_PERILP>;
1343                 clock-names = "apb_pclk";
1344         };
1345
1346         pmucru: pmu-clock-controller@ff750000 {
1347                 compatible = "rockchip,rk3399-pmucru";
1348                 reg = <0x0 0xff750000 0x0 0x1000>;
1349                 rockchip,grf = <&pmugrf>;
1350                 #clock-cells = <1>;
1351                 #reset-cells = <1>;
1352                 assigned-clocks = <&pmucru PLL_PPLL>;
1353                 assigned-clock-rates = <676000000>;
1354         };
1355
1356         cru: clock-controller@ff760000 {
1357                 compatible = "rockchip,rk3399-cru";
1358                 reg = <0x0 0xff760000 0x0 0x1000>;
1359                 rockchip,grf = <&grf>;
1360                 #clock-cells = <1>;
1361                 #reset-cells = <1>;
1362                 assigned-clocks =
1363                         <&cru PLL_GPLL>, <&cru PLL_CPLL>,
1364                         <&cru PLL_NPLL>,
1365                         <&cru ACLK_PERIHP>, <&cru HCLK_PERIHP>,
1366                         <&cru PCLK_PERIHP>,
1367                         <&cru ACLK_PERILP0>, <&cru HCLK_PERILP0>,
1368                         <&cru PCLK_PERILP0>, <&cru ACLK_CCI>,
1369                         <&cru HCLK_PERILP1>, <&cru PCLK_PERILP1>,
1370                         <&cru ACLK_VIO>, <&cru ACLK_HDCP>,
1371                         <&cru ACLK_GIC_PRE>,
1372                         <&cru PCLK_DDR>;
1373                 assigned-clock-rates =
1374                          <594000000>,  <800000000>,
1375                         <1000000000>,
1376                          <150000000>,   <75000000>,
1377                           <37500000>,
1378                          <100000000>,  <100000000>,
1379                           <50000000>, <600000000>,
1380                          <100000000>,   <50000000>,
1381                          <400000000>, <400000000>,
1382                          <200000000>,
1383                          <200000000>;
1384         };
1385
1386         grf: syscon@ff770000 {
1387                 compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
1388                 reg = <0x0 0xff770000 0x0 0x10000>;
1389                 #address-cells = <1>;
1390                 #size-cells = <1>;
1391
1392                 io_domains: io-domains {
1393                         compatible = "rockchip,rk3399-io-voltage-domain";
1394                         status = "disabled";
1395                 };
1396
1397                 mipi_dphy_rx0: mipi-dphy-rx0 {
1398                         compatible = "rockchip,rk3399-mipi-dphy-rx0";
1399                         clocks = <&cru SCLK_MIPIDPHY_REF>,
1400                                  <&cru SCLK_DPHY_RX0_CFG>,
1401                                  <&cru PCLK_VIO_GRF>;
1402                         clock-names = "dphy-ref", "dphy-cfg", "grf";
1403                         power-domains = <&power RK3399_PD_VIO>;
1404                         #phy-cells = <0>;
1405                         status = "disabled";
1406                 };
1407
1408                 u2phy0: usb2-phy@e450 {
1409                         compatible = "rockchip,rk3399-usb2phy";
1410                         reg = <0xe450 0x10>;
1411                         clocks = <&cru SCLK_USB2PHY0_REF>;
1412                         clock-names = "phyclk";
1413                         #clock-cells = <0>;
1414                         clock-output-names = "clk_usbphy0_480m";
1415                         status = "disabled";
1416
1417                         u2phy0_host: host-port {
1418                                 #phy-cells = <0>;
1419                                 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH 0>;
1420                                 interrupt-names = "linestate";
1421                                 status = "disabled";
1422                         };
1423
1424                         u2phy0_otg: otg-port {
1425                                 #phy-cells = <0>;
1426                                 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH 0>,
1427                                              <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH 0>,
1428                                              <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH 0>;
1429                                 interrupt-names = "otg-bvalid", "otg-id",
1430                                                   "linestate";
1431                                 status = "disabled";
1432                         };
1433                 };
1434
1435                 u2phy1: usb2-phy@e460 {
1436                         compatible = "rockchip,rk3399-usb2phy";
1437                         reg = <0xe460 0x10>;
1438                         clocks = <&cru SCLK_USB2PHY1_REF>;
1439                         clock-names = "phyclk";
1440                         #clock-cells = <0>;
1441                         clock-output-names = "clk_usbphy1_480m";
1442                         status = "disabled";
1443
1444                         u2phy1_host: host-port {
1445                                 #phy-cells = <0>;
1446                                 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
1447                                 interrupt-names = "linestate";
1448                                 status = "disabled";
1449                         };
1450
1451                         u2phy1_otg: otg-port {
1452                                 #phy-cells = <0>;
1453                                 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH 0>,
1454                                              <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH 0>,
1455                                              <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH 0>;
1456                                 interrupt-names = "otg-bvalid", "otg-id",
1457                                                   "linestate";
1458                                 status = "disabled";
1459                         };
1460                 };
1461
1462                 emmc_phy: phy@f780 {
1463                         compatible = "rockchip,rk3399-emmc-phy";
1464                         reg = <0xf780 0x24>;
1465                         clocks = <&sdhci>;
1466                         clock-names = "emmcclk";
1467                         #phy-cells = <0>;
1468                         status = "disabled";
1469                 };
1470
1471                 pcie_phy: pcie-phy {
1472                         compatible = "rockchip,rk3399-pcie-phy";
1473                         clocks = <&cru SCLK_PCIEPHY_REF>;
1474                         clock-names = "refclk";
1475                         #phy-cells = <1>;
1476                         resets = <&cru SRST_PCIEPHY>;
1477                         drive-impedance-ohm = <50>;
1478                         reset-names = "phy";
1479                         status = "disabled";
1480                 };
1481         };
1482
1483         tcphy0: phy@ff7c0000 {
1484                 compatible = "rockchip,rk3399-typec-phy";
1485                 reg = <0x0 0xff7c0000 0x0 0x40000>;
1486                 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
1487                          <&cru SCLK_UPHY0_TCPDPHY_REF>;
1488                 clock-names = "tcpdcore", "tcpdphy-ref";
1489                 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
1490                 assigned-clock-rates = <50000000>;
1491                 power-domains = <&power RK3399_PD_TCPD0>;
1492                 resets = <&cru SRST_UPHY0>,
1493                          <&cru SRST_UPHY0_PIPE_L00>,
1494                          <&cru SRST_P_UPHY0_TCPHY>;
1495                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1496                 rockchip,grf = <&grf>;
1497                 status = "disabled";
1498
1499                 tcphy0_dp: dp-port {
1500                         #phy-cells = <0>;
1501                 };
1502
1503                 tcphy0_usb3: usb3-port {
1504                         #phy-cells = <0>;
1505                 };
1506         };
1507
1508         tcphy1: phy@ff800000 {
1509                 compatible = "rockchip,rk3399-typec-phy";
1510                 reg = <0x0 0xff800000 0x0 0x40000>;
1511                 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
1512                          <&cru SCLK_UPHY1_TCPDPHY_REF>;
1513                 clock-names = "tcpdcore", "tcpdphy-ref";
1514                 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
1515                 assigned-clock-rates = <50000000>;
1516                 power-domains = <&power RK3399_PD_TCPD1>;
1517                 resets = <&cru SRST_UPHY1>,
1518                          <&cru SRST_UPHY1_PIPE_L00>,
1519                          <&cru SRST_P_UPHY1_TCPHY>;
1520                 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
1521                 rockchip,grf = <&grf>;
1522                 status = "disabled";
1523
1524                 tcphy1_dp: dp-port {
1525                         #phy-cells = <0>;
1526                 };
1527
1528                 tcphy1_usb3: usb3-port {
1529                         #phy-cells = <0>;
1530                 };
1531         };
1532
1533         watchdog@ff848000 {
1534                 compatible = "snps,dw-wdt";
1535                 reg = <0x0 0xff848000 0x0 0x100>;
1536                 clocks = <&cru PCLK_WDT>;
1537                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
1538         };
1539
1540         rktimer: rktimer@ff850000 {
1541                 compatible = "rockchip,rk3399-timer";
1542                 reg = <0x0 0xff850000 0x0 0x1000>;
1543                 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH 0>;
1544                 clocks = <&cru PCLK_TIMER0>, <&cru SCLK_TIMER00>;
1545                 clock-names = "pclk", "timer";
1546         };
1547
1548         spdif: spdif@ff870000 {
1549                 compatible = "rockchip,rk3399-spdif";
1550                 reg = <0x0 0xff870000 0x0 0x1000>;
1551                 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH 0>;
1552                 dmas = <&dmac_bus 7>;
1553                 dma-names = "tx";
1554                 clock-names = "mclk", "hclk";
1555                 clocks = <&cru SCLK_SPDIF_8CH>, <&cru HCLK_SPDIF>;
1556                 pinctrl-names = "default";
1557                 pinctrl-0 = <&spdif_bus>;
1558                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1559                 #sound-dai-cells = <0>;
1560                 status = "disabled";
1561         };
1562
1563         i2s0: i2s@ff880000 {
1564                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1565                 reg = <0x0 0xff880000 0x0 0x1000>;
1566                 rockchip,grf = <&grf>;
1567                 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH 0>;
1568                 dmas = <&dmac_bus 0>, <&dmac_bus 1>;
1569                 dma-names = "tx", "rx";
1570                 clock-names = "i2s_clk", "i2s_hclk";
1571                 clocks = <&cru SCLK_I2S0_8CH>, <&cru HCLK_I2S0_8CH>;
1572                 pinctrl-names = "default";
1573                 pinctrl-0 = <&i2s0_8ch_bus>;
1574                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1575                 #sound-dai-cells = <0>;
1576                 status = "disabled";
1577         };
1578
1579         i2s1: i2s@ff890000 {
1580                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1581                 reg = <0x0 0xff890000 0x0 0x1000>;
1582                 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH 0>;
1583                 dmas = <&dmac_bus 2>, <&dmac_bus 3>;
1584                 dma-names = "tx", "rx";
1585                 clock-names = "i2s_clk", "i2s_hclk";
1586                 clocks = <&cru SCLK_I2S1_8CH>, <&cru HCLK_I2S1_8CH>;
1587                 pinctrl-names = "default";
1588                 pinctrl-0 = <&i2s1_2ch_bus>;
1589                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1590                 #sound-dai-cells = <0>;
1591                 status = "disabled";
1592         };
1593
1594         i2s2: i2s@ff8a0000 {
1595                 compatible = "rockchip,rk3399-i2s", "rockchip,rk3066-i2s";
1596                 reg = <0x0 0xff8a0000 0x0 0x1000>;
1597                 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH 0>;
1598                 dmas = <&dmac_bus 4>, <&dmac_bus 5>;
1599                 dma-names = "tx", "rx";
1600                 clock-names = "i2s_clk", "i2s_hclk";
1601                 clocks = <&cru SCLK_I2S2_8CH>, <&cru HCLK_I2S2_8CH>;
1602                 power-domains = <&power RK3399_PD_SDIOAUDIO>;
1603                 #sound-dai-cells = <0>;
1604                 status = "disabled";
1605         };
1606
1607         vopl: vop@ff8f0000 {
1608                 compatible = "rockchip,rk3399-vop-lit";
1609                 reg = <0x0 0xff8f0000 0x0 0x3efc>;
1610                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1611                 assigned-clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1612                 assigned-clock-rates = <400000000>, <100000000>;
1613                 clocks = <&cru ACLK_VOP1>, <&cru DCLK_VOP1>, <&cru HCLK_VOP1>;
1614                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1615                 iommus = <&vopl_mmu>;
1616                 power-domains = <&power RK3399_PD_VOPL>;
1617                 resets = <&cru SRST_A_VOP1>, <&cru SRST_H_VOP1>, <&cru SRST_D_VOP1>;
1618                 reset-names = "axi", "ahb", "dclk";
1619                 status = "disabled";
1620
1621                 vopl_out: port {
1622                         #address-cells = <1>;
1623                         #size-cells = <0>;
1624
1625                         vopl_out_mipi: endpoint@0 {
1626                                 reg = <0>;
1627                                 remote-endpoint = <&mipi_in_vopl>;
1628                         };
1629
1630                         vopl_out_edp: endpoint@1 {
1631                                 reg = <1>;
1632                                 remote-endpoint = <&edp_in_vopl>;
1633                         };
1634
1635                         vopl_out_hdmi: endpoint@2 {
1636                                 reg = <2>;
1637                                 remote-endpoint = <&hdmi_in_vopl>;
1638                         };
1639
1640                         vopl_out_mipi1: endpoint@3 {
1641                                 reg = <3>;
1642                                 remote-endpoint = <&mipi1_in_vopl>;
1643                         };
1644
1645                         vopl_out_dp: endpoint@4 {
1646                                 reg = <4>;
1647                                 remote-endpoint = <&dp_in_vopl>;
1648                         };
1649                 };
1650         };
1651
1652         vopl_mmu: iommu@ff8f3f00 {
1653                 compatible = "rockchip,iommu";
1654                 reg = <0x0 0xff8f3f00 0x0 0x100>;
1655                 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
1656                 interrupt-names = "vopl_mmu";
1657                 clocks = <&cru ACLK_VOP1>, <&cru HCLK_VOP1>;
1658                 clock-names = "aclk", "iface";
1659                 power-domains = <&power RK3399_PD_VOPL>;
1660                 #iommu-cells = <0>;
1661                 status = "disabled";
1662         };
1663
1664         vopb: vop@ff900000 {
1665                 compatible = "rockchip,rk3399-vop-big";
1666                 reg = <0x0 0xff900000 0x0 0x3efc>;
1667                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1668                 assigned-clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1669                 assigned-clock-rates = <400000000>, <100000000>;
1670                 clocks = <&cru ACLK_VOP0>, <&cru DCLK_VOP0>, <&cru HCLK_VOP0>;
1671                 clock-names = "aclk_vop", "dclk_vop", "hclk_vop";
1672                 iommus = <&vopb_mmu>;
1673                 power-domains = <&power RK3399_PD_VOPB>;
1674                 resets = <&cru SRST_A_VOP0>, <&cru SRST_H_VOP0>, <&cru SRST_D_VOP0>;
1675                 reset-names = "axi", "ahb", "dclk";
1676                 status = "disabled";
1677
1678                 vopb_out: port {
1679                         #address-cells = <1>;
1680                         #size-cells = <0>;
1681
1682                         vopb_out_edp: endpoint@0 {
1683                                 reg = <0>;
1684                                 remote-endpoint = <&edp_in_vopb>;
1685                         };
1686
1687                         vopb_out_mipi: endpoint@1 {
1688                                 reg = <1>;
1689                                 remote-endpoint = <&mipi_in_vopb>;
1690                         };
1691
1692                         vopb_out_hdmi: endpoint@2 {
1693                                 reg = <2>;
1694                                 remote-endpoint = <&hdmi_in_vopb>;
1695                         };
1696
1697                         vopb_out_mipi1: endpoint@3 {
1698                                 reg = <3>;
1699                                 remote-endpoint = <&mipi1_in_vopb>;
1700                         };
1701
1702                         vopb_out_dp: endpoint@4 {
1703                                 reg = <4>;
1704                                 remote-endpoint = <&dp_in_vopb>;
1705                         };
1706                 };
1707         };
1708
1709         vopb_mmu: iommu@ff903f00 {
1710                 compatible = "rockchip,iommu";
1711                 reg = <0x0 0xff903f00 0x0 0x100>;
1712                 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
1713                 interrupt-names = "vopb_mmu";
1714                 clocks = <&cru ACLK_VOP0>, <&cru HCLK_VOP0>;
1715                 clock-names = "aclk", "iface";
1716                 power-domains = <&power RK3399_PD_VOPB>;
1717                 #iommu-cells = <0>;
1718                 status = "disabled";
1719         };
1720
1721         isp0: isp0@ff910000 {
1722                 compatible = "rockchip,rk3399-cif-isp";
1723                 reg = <0x0 0xff910000 0x0 0x4000>;
1724                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1725                 clocks = <&cru SCLK_ISP0>,
1726                          <&cru ACLK_ISP0_WRAPPER>,
1727                          <&cru HCLK_ISP0_WRAPPER>;
1728                 clock-names = "isp", "aclk", "hclk";
1729                 iommus = <&isp0_mmu>;
1730                 phys = <&mipi_dphy_rx0>;
1731                 phy-names = "dphy";
1732                 power-domains = <&power RK3399_PD_ISP0>;
1733                 status = "disabled";
1734
1735                 ports {
1736                         #address-cells = <1>;
1737                         #size-cells = <0>;
1738
1739                         port@0 {
1740                                 reg = <0>;
1741                                 #address-cells = <1>;
1742                                 #size-cells = <0>;
1743                         };
1744                 };
1745         };
1746
1747         isp0_mmu: iommu@ff914000 {
1748                 compatible = "rockchip,iommu";
1749                 reg = <0x0 0xff914000 0x0 0x100>, <0x0 0xff915000 0x0 0x100>;
1750                 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH 0>;
1751                 interrupt-names = "isp0_mmu";
1752                 clocks = <&cru ACLK_ISP0_WRAPPER>, <&cru HCLK_ISP0_WRAPPER>;
1753                 clock-names = "aclk", "iface";
1754                 #iommu-cells = <0>;
1755                 power-domains = <&power RK3399_PD_ISP0>;
1756                 rockchip,disable-mmu-reset;
1757         };
1758
1759         isp1_mmu: iommu@ff924000 {
1760                 compatible = "rockchip,iommu";
1761                 reg = <0x0 0xff924000 0x0 0x100>, <0x0 0xff925000 0x0 0x100>;
1762                 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH 0>;
1763                 interrupt-names = "isp1_mmu";
1764                 clocks = <&cru ACLK_ISP1_WRAPPER>, <&cru HCLK_ISP1_WRAPPER>;
1765                 clock-names = "aclk", "iface";
1766                 #iommu-cells = <0>;
1767                 power-domains = <&power RK3399_PD_ISP1>;
1768                 rockchip,disable-mmu-reset;
1769         };
1770
1771         hdmi_sound: hdmi-sound {
1772                 compatible = "simple-audio-card";
1773                 simple-audio-card,format = "i2s";
1774                 simple-audio-card,mclk-fs = <256>;
1775                 simple-audio-card,name = "hdmi-sound";
1776                 status = "disabled";
1777
1778                 simple-audio-card,cpu {
1779                         sound-dai = <&i2s2>;
1780                 };
1781                 simple-audio-card,codec {
1782                         sound-dai = <&hdmi>;
1783                 };
1784         };
1785
1786         hdmi: hdmi@ff940000 {
1787                 compatible = "rockchip,rk3399-dw-hdmi";
1788                 reg = <0x0 0xff940000 0x0 0x20000>;
1789                 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH 0>;
1790                 clocks = <&cru PCLK_HDMI_CTRL>,
1791                          <&cru SCLK_HDMI_SFR>,
1792                          <&cru PLL_VPLL>,
1793                          <&cru PCLK_VIO_GRF>,
1794                          <&cru SCLK_HDMI_CEC>;
1795                 clock-names = "iahb", "isfr", "vpll", "grf", "cec";
1796                 power-domains = <&power RK3399_PD_HDCP>;
1797                 reg-io-width = <4>;
1798                 rockchip,grf = <&grf>;
1799                 #sound-dai-cells = <0>;
1800                 status = "disabled";
1801
1802                 ports {
1803                         hdmi_in: port {
1804                                 #address-cells = <1>;
1805                                 #size-cells = <0>;
1806
1807                                 hdmi_in_vopb: endpoint@0 {
1808                                         reg = <0>;
1809                                         remote-endpoint = <&vopb_out_hdmi>;
1810                                 };
1811                                 hdmi_in_vopl: endpoint@1 {
1812                                         reg = <1>;
1813                                         remote-endpoint = <&vopl_out_hdmi>;
1814                                 };
1815                         };
1816                 };
1817         };
1818
1819         mipi_dsi: mipi@ff960000 {
1820                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1821                 reg = <0x0 0xff960000 0x0 0x8000>;
1822                 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH 0>;
1823                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI0>,
1824                          <&cru SCLK_DPHY_TX0_CFG>, <&cru PCLK_VIO_GRF>;
1825                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1826                 power-domains = <&power RK3399_PD_VIO>;
1827                 resets = <&cru SRST_P_MIPI_DSI0>;
1828                 reset-names = "apb";
1829                 rockchip,grf = <&grf>;
1830                 #address-cells = <1>;
1831                 #size-cells = <0>;
1832                 status = "disabled";
1833
1834                 ports {
1835                         #address-cells = <1>;
1836                         #size-cells = <0>;
1837
1838                         mipi_in: port@0 {
1839                                 reg = <0>;
1840                                 #address-cells = <1>;
1841                                 #size-cells = <0>;
1842
1843                                 mipi_in_vopb: endpoint@0 {
1844                                         reg = <0>;
1845                                         remote-endpoint = <&vopb_out_mipi>;
1846                                 };
1847                                 mipi_in_vopl: endpoint@1 {
1848                                         reg = <1>;
1849                                         remote-endpoint = <&vopl_out_mipi>;
1850                                 };
1851                         };
1852                 };
1853         };
1854
1855         mipi_dsi1: mipi@ff968000 {
1856                 compatible = "rockchip,rk3399-mipi-dsi", "snps,dw-mipi-dsi";
1857                 reg = <0x0 0xff968000 0x0 0x8000>;
1858                 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH 0>;
1859                 clocks = <&cru SCLK_DPHY_PLL>, <&cru PCLK_MIPI_DSI1>,
1860                          <&cru SCLK_DPHY_TX1RX1_CFG>, <&cru PCLK_VIO_GRF>;
1861                 clock-names = "ref", "pclk", "phy_cfg", "grf";
1862                 power-domains = <&power RK3399_PD_VIO>;
1863                 resets = <&cru SRST_P_MIPI_DSI1>;
1864                 reset-names = "apb";
1865                 rockchip,grf = <&grf>;
1866                 #address-cells = <1>;
1867                 #size-cells = <0>;
1868                 status = "disabled";
1869
1870                 ports {
1871                         #address-cells = <1>;
1872                         #size-cells = <0>;
1873
1874                         mipi1_in: port@0 {
1875                                 reg = <0>;
1876                                 #address-cells = <1>;
1877                                 #size-cells = <0>;
1878
1879                                 mipi1_in_vopb: endpoint@0 {
1880                                         reg = <0>;
1881                                         remote-endpoint = <&vopb_out_mipi1>;
1882                                 };
1883
1884                                 mipi1_in_vopl: endpoint@1 {
1885                                         reg = <1>;
1886                                         remote-endpoint = <&vopl_out_mipi1>;
1887                                 };
1888                         };
1889                 };
1890         };
1891
1892         edp: edp@ff970000 {
1893                 compatible = "rockchip,rk3399-edp";
1894                 reg = <0x0 0xff970000 0x0 0x8000>;
1895                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
1896                 clocks = <&cru PCLK_EDP>, <&cru PCLK_EDP_CTRL>, <&cru PCLK_VIO_GRF>;
1897                 clock-names = "dp", "pclk", "grf";
1898                 pinctrl-names = "default";
1899                 pinctrl-0 = <&edp_hpd>;
1900                 power-domains = <&power RK3399_PD_EDP>;
1901                 resets = <&cru SRST_P_EDP_CTRL>;
1902                 reset-names = "dp";
1903                 rockchip,grf = <&grf>;
1904                 status = "disabled";
1905
1906                 ports {
1907                         #address-cells = <1>;
1908                         #size-cells = <0>;
1909                         edp_in: port@0 {
1910                                 reg = <0>;
1911                                 #address-cells = <1>;
1912                                 #size-cells = <0>;
1913
1914                                 edp_in_vopb: endpoint@0 {
1915                                         reg = <0>;
1916                                         remote-endpoint = <&vopb_out_edp>;
1917                                 };
1918
1919                                 edp_in_vopl: endpoint@1 {
1920                                         reg = <1>;
1921                                         remote-endpoint = <&vopl_out_edp>;
1922                                 };
1923                         };
1924                 };
1925         };
1926
1927         gpu: gpu@ff9a0000 {
1928                 compatible = "rockchip,rk3399-mali", "arm,mali-t860";
1929                 reg = <0x0 0xff9a0000 0x0 0x10000>;
1930                 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH 0>,
1931                              <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH 0>,
1932                              <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH 0>;
1933                 interrupt-names = "job", "mmu", "gpu";
1934                 clocks = <&cru ACLK_GPU>;
1935                 #cooling-cells = <2>;
1936                 power-domains = <&power RK3399_PD_GPU>;
1937                 status = "disabled";
1938         };
1939
1940         pinctrl: pinctrl {
1941                 compatible = "rockchip,rk3399-pinctrl";
1942                 rockchip,grf = <&grf>;
1943                 rockchip,pmu = <&pmugrf>;
1944                 #address-cells = <2>;
1945                 #size-cells = <2>;
1946                 ranges;
1947
1948                 gpio0: gpio0@ff720000 {
1949                         compatible = "rockchip,gpio-bank";
1950                         reg = <0x0 0xff720000 0x0 0x100>;
1951                         clocks = <&pmucru PCLK_GPIO0_PMU>;
1952                         interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH 0>;
1953
1954                         gpio-controller;
1955                         #gpio-cells = <0x2>;
1956
1957                         interrupt-controller;
1958                         #interrupt-cells = <0x2>;
1959                 };
1960
1961                 gpio1: gpio1@ff730000 {
1962                         compatible = "rockchip,gpio-bank";
1963                         reg = <0x0 0xff730000 0x0 0x100>;
1964                         clocks = <&pmucru PCLK_GPIO1_PMU>;
1965                         interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH 0>;
1966
1967                         gpio-controller;
1968                         #gpio-cells = <0x2>;
1969
1970                         interrupt-controller;
1971                         #interrupt-cells = <0x2>;
1972                 };
1973
1974                 gpio2: gpio2@ff780000 {
1975                         compatible = "rockchip,gpio-bank";
1976                         reg = <0x0 0xff780000 0x0 0x100>;
1977                         clocks = <&cru PCLK_GPIO2>;
1978                         interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH 0>;
1979
1980                         gpio-controller;
1981                         #gpio-cells = <0x2>;
1982
1983                         interrupt-controller;
1984                         #interrupt-cells = <0x2>;
1985                 };
1986
1987                 gpio3: gpio3@ff788000 {
1988                         compatible = "rockchip,gpio-bank";
1989                         reg = <0x0 0xff788000 0x0 0x100>;
1990                         clocks = <&cru PCLK_GPIO3>;
1991                         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH 0>;
1992
1993                         gpio-controller;
1994                         #gpio-cells = <0x2>;
1995
1996                         interrupt-controller;
1997                         #interrupt-cells = <0x2>;
1998                 };
1999
2000                 gpio4: gpio4@ff790000 {
2001                         compatible = "rockchip,gpio-bank";
2002                         reg = <0x0 0xff790000 0x0 0x100>;
2003                         clocks = <&cru PCLK_GPIO4>;
2004                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
2005
2006                         gpio-controller;
2007                         #gpio-cells = <0x2>;
2008
2009                         interrupt-controller;
2010                         #interrupt-cells = <0x2>;
2011                 };
2012
2013                 pcfg_pull_up: pcfg-pull-up {
2014                         bias-pull-up;
2015                 };
2016
2017                 pcfg_pull_down: pcfg-pull-down {
2018                         bias-pull-down;
2019                 };
2020
2021                 pcfg_pull_none: pcfg-pull-none {
2022                         bias-disable;
2023                 };
2024
2025                 pcfg_pull_none_12ma: pcfg-pull-none-12ma {
2026                         bias-disable;
2027                         drive-strength = <12>;
2028                 };
2029
2030                 pcfg_pull_none_13ma: pcfg-pull-none-13ma {
2031                         bias-disable;
2032                         drive-strength = <13>;
2033                 };
2034
2035                 pcfg_pull_none_18ma: pcfg-pull-none-18ma {
2036                         bias-disable;
2037                         drive-strength = <18>;
2038                 };
2039
2040                 pcfg_pull_none_20ma: pcfg-pull-none-20ma {
2041                         bias-disable;
2042                         drive-strength = <20>;
2043                 };
2044
2045                 pcfg_pull_up_2ma: pcfg-pull-up-2ma {
2046                         bias-pull-up;
2047                         drive-strength = <2>;
2048                 };
2049
2050                 pcfg_pull_up_8ma: pcfg-pull-up-8ma {
2051                         bias-pull-up;
2052                         drive-strength = <8>;
2053                 };
2054
2055                 pcfg_pull_up_18ma: pcfg-pull-up-18ma {
2056                         bias-pull-up;
2057                         drive-strength = <18>;
2058                 };
2059
2060                 pcfg_pull_up_20ma: pcfg-pull-up-20ma {
2061                         bias-pull-up;
2062                         drive-strength = <20>;
2063                 };
2064
2065                 pcfg_pull_down_4ma: pcfg-pull-down-4ma {
2066                         bias-pull-down;
2067                         drive-strength = <4>;
2068                 };
2069
2070                 pcfg_pull_down_8ma: pcfg-pull-down-8ma {
2071                         bias-pull-down;
2072                         drive-strength = <8>;
2073                 };
2074
2075                 pcfg_pull_down_12ma: pcfg-pull-down-12ma {
2076                         bias-pull-down;
2077                         drive-strength = <12>;
2078                 };
2079
2080                 pcfg_pull_down_18ma: pcfg-pull-down-18ma {
2081                         bias-pull-down;
2082                         drive-strength = <18>;
2083                 };
2084
2085                 pcfg_pull_down_20ma: pcfg-pull-down-20ma {
2086                         bias-pull-down;
2087                         drive-strength = <20>;
2088                 };
2089
2090                 pcfg_output_high: pcfg-output-high {
2091                         output-high;
2092                 };
2093
2094                 pcfg_output_low: pcfg-output-low {
2095                         output-low;
2096                 };
2097
2098                 clock {
2099                         clk_32k: clk-32k {
2100                                 rockchip,pins = <0 RK_PA0 2 &pcfg_pull_none>;
2101                         };
2102                 };
2103
2104                 edp {
2105                         edp_hpd: edp-hpd {
2106                                 rockchip,pins =
2107                                         <4 RK_PC7 2 &pcfg_pull_none>;
2108                         };
2109                 };
2110
2111                 gmac {
2112                         rgmii_pins: rgmii-pins {
2113                                 rockchip,pins =
2114                                         /* mac_txclk */
2115                                         <3 RK_PC1 1 &pcfg_pull_none_13ma>,
2116                                         /* mac_rxclk */
2117                                         <3 RK_PB6 1 &pcfg_pull_none>,
2118                                         /* mac_mdio */
2119                                         <3 RK_PB5 1 &pcfg_pull_none>,
2120                                         /* mac_txen */
2121                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2122                                         /* mac_clk */
2123                                         <3 RK_PB3 1 &pcfg_pull_none>,
2124                                         /* mac_rxdv */
2125                                         <3 RK_PB1 1 &pcfg_pull_none>,
2126                                         /* mac_mdc */
2127                                         <3 RK_PB0 1 &pcfg_pull_none>,
2128                                         /* mac_rxd1 */
2129                                         <3 RK_PA7 1 &pcfg_pull_none>,
2130                                         /* mac_rxd0 */
2131                                         <3 RK_PA6 1 &pcfg_pull_none>,
2132                                         /* mac_txd1 */
2133                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2134                                         /* mac_txd0 */
2135                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>,
2136                                         /* mac_rxd3 */
2137                                         <3 RK_PA3 1 &pcfg_pull_none>,
2138                                         /* mac_rxd2 */
2139                                         <3 RK_PA2 1 &pcfg_pull_none>,
2140                                         /* mac_txd3 */
2141                                         <3 RK_PA1 1 &pcfg_pull_none_13ma>,
2142                                         /* mac_txd2 */
2143                                         <3 RK_PA0 1 &pcfg_pull_none_13ma>;
2144                         };
2145
2146                         rmii_pins: rmii-pins {
2147                                 rockchip,pins =
2148                                         /* mac_mdio */
2149                                         <3 RK_PB5 1 &pcfg_pull_none>,
2150                                         /* mac_txen */
2151                                         <3 RK_PB4 1 &pcfg_pull_none_13ma>,
2152                                         /* mac_clk */
2153                                         <3 RK_PB3 1 &pcfg_pull_none>,
2154                                         /* mac_rxer */
2155                                         <3 RK_PB2 1 &pcfg_pull_none>,
2156                                         /* mac_rxdv */
2157                                         <3 RK_PB1 1 &pcfg_pull_none>,
2158                                         /* mac_mdc */
2159                                         <3 RK_PB0 1 &pcfg_pull_none>,
2160                                         /* mac_rxd1 */
2161                                         <3 RK_PA7 1 &pcfg_pull_none>,
2162                                         /* mac_rxd0 */
2163                                         <3 RK_PA6 1 &pcfg_pull_none>,
2164                                         /* mac_txd1 */
2165                                         <3 RK_PA5 1 &pcfg_pull_none_13ma>,
2166                                         /* mac_txd0 */
2167                                         <3 RK_PA4 1 &pcfg_pull_none_13ma>;
2168                         };
2169                 };
2170
2171                 i2c0 {
2172                         i2c0_xfer: i2c0-xfer {
2173                                 rockchip,pins =
2174                                         <1 RK_PB7 2 &pcfg_pull_none>,
2175                                         <1 RK_PC0 2 &pcfg_pull_none>;
2176                         };
2177                 };
2178
2179                 i2c1 {
2180                         i2c1_xfer: i2c1-xfer {
2181                                 rockchip,pins =
2182                                         <4 RK_PA2 1 &pcfg_pull_none>,
2183                                         <4 RK_PA1 1 &pcfg_pull_none>;
2184                         };
2185                 };
2186
2187                 i2c2 {
2188                         i2c2_xfer: i2c2-xfer {
2189                                 rockchip,pins =
2190                                         <2 RK_PA1 2 &pcfg_pull_none_12ma>,
2191                                         <2 RK_PA0 2 &pcfg_pull_none_12ma>;
2192                         };
2193                 };
2194
2195                 i2c3 {
2196                         i2c3_xfer: i2c3-xfer {
2197                                 rockchip,pins =
2198                                         <4 RK_PC1 1 &pcfg_pull_none>,
2199                                         <4 RK_PC0 1 &pcfg_pull_none>;
2200                         };
2201                 };
2202
2203                 i2c4 {
2204                         i2c4_xfer: i2c4-xfer {
2205                                 rockchip,pins =
2206                                         <1 RK_PB4 1 &pcfg_pull_none>,
2207                                         <1 RK_PB3 1 &pcfg_pull_none>;
2208                         };
2209                 };
2210
2211                 i2c5 {
2212                         i2c5_xfer: i2c5-xfer {
2213                                 rockchip,pins =
2214                                         <3 RK_PB3 2 &pcfg_pull_none>,
2215                                         <3 RK_PB2 2 &pcfg_pull_none>;
2216                         };
2217                 };
2218
2219                 i2c6 {
2220                         i2c6_xfer: i2c6-xfer {
2221                                 rockchip,pins =
2222                                         <2 RK_PB2 2 &pcfg_pull_none>,
2223                                         <2 RK_PB1 2 &pcfg_pull_none>;
2224                         };
2225                 };
2226
2227                 i2c7 {
2228                         i2c7_xfer: i2c7-xfer {
2229                                 rockchip,pins =
2230                                         <2 RK_PB0 2 &pcfg_pull_none>,
2231                                         <2 RK_PA7 2 &pcfg_pull_none>;
2232                         };
2233                 };
2234
2235                 i2c8 {
2236                         i2c8_xfer: i2c8-xfer {
2237                                 rockchip,pins =
2238                                         <1 RK_PC5 1 &pcfg_pull_none>,
2239                                         <1 RK_PC4 1 &pcfg_pull_none>;
2240                         };
2241                 };
2242
2243                 i2s0 {
2244                         i2s0_2ch_bus: i2s0-2ch-bus {
2245                                 rockchip,pins =
2246                                         <3 RK_PD0 1 &pcfg_pull_none>,
2247                                         <3 RK_PD1 1 &pcfg_pull_none>,
2248                                         <3 RK_PD2 1 &pcfg_pull_none>,
2249                                         <3 RK_PD3 1 &pcfg_pull_none>,
2250                                         <3 RK_PD7 1 &pcfg_pull_none>,
2251                                         <4 RK_PA0 1 &pcfg_pull_none>;
2252                         };
2253
2254                         i2s0_8ch_bus: i2s0-8ch-bus {
2255                                 rockchip,pins =
2256                                         <3 RK_PD0 1 &pcfg_pull_none>,
2257                                         <3 RK_PD1 1 &pcfg_pull_none>,
2258                                         <3 RK_PD2 1 &pcfg_pull_none>,
2259                                         <3 RK_PD3 1 &pcfg_pull_none>,
2260                                         <3 RK_PD4 1 &pcfg_pull_none>,
2261                                         <3 RK_PD5 1 &pcfg_pull_none>,
2262                                         <3 RK_PD6 1 &pcfg_pull_none>,
2263                                         <3 RK_PD7 1 &pcfg_pull_none>,
2264                                         <4 RK_PA0 1 &pcfg_pull_none>;
2265                         };
2266                 };
2267
2268                 i2s1 {
2269                         i2s1_2ch_bus: i2s1-2ch-bus {
2270                                 rockchip,pins =
2271                                         <4 RK_PA3 1 &pcfg_pull_none>,
2272                                         <4 RK_PA4 1 &pcfg_pull_none>,
2273                                         <4 RK_PA5 1 &pcfg_pull_none>,
2274                                         <4 RK_PA6 1 &pcfg_pull_none>,
2275                                         <4 RK_PA7 1 &pcfg_pull_none>;
2276                         };
2277                 };
2278
2279                 sdio0 {
2280                         sdio0_bus1: sdio0-bus1 {
2281                                 rockchip,pins =
2282                                         <2 RK_PC4 1 &pcfg_pull_up>;
2283                         };
2284
2285                         sdio0_bus4: sdio0-bus4 {
2286                                 rockchip,pins =
2287                                         <2 RK_PC4 1 &pcfg_pull_up>,
2288                                         <2 RK_PC5 1 &pcfg_pull_up>,
2289                                         <2 RK_PC6 1 &pcfg_pull_up>,
2290                                         <2 RK_PC7 1 &pcfg_pull_up>;
2291                         };
2292
2293                         sdio0_cmd: sdio0-cmd {
2294                                 rockchip,pins =
2295                                         <2 RK_PD0 1 &pcfg_pull_up>;
2296                         };
2297
2298                         sdio0_clk: sdio0-clk {
2299                                 rockchip,pins =
2300                                         <2 RK_PD1 1 &pcfg_pull_none>;
2301                         };
2302
2303                         sdio0_cd: sdio0-cd {
2304                                 rockchip,pins =
2305                                         <2 RK_PD2 1 &pcfg_pull_up>;
2306                         };
2307
2308                         sdio0_pwr: sdio0-pwr {
2309                                 rockchip,pins =
2310                                         <2 RK_PD3 1 &pcfg_pull_up>;
2311                         };
2312
2313                         sdio0_bkpwr: sdio0-bkpwr {
2314                                 rockchip,pins =
2315                                         <2 RK_PD4 1 &pcfg_pull_up>;
2316                         };
2317
2318                         sdio0_wp: sdio0-wp {
2319                                 rockchip,pins =
2320                                         <0 RK_PA3 1 &pcfg_pull_up>;
2321                         };
2322
2323                         sdio0_int: sdio0-int {
2324                                 rockchip,pins =
2325                                         <0 RK_PA4 1 &pcfg_pull_up>;
2326                         };
2327                 };
2328
2329                 sdmmc {
2330                         sdmmc_bus1: sdmmc-bus1 {
2331                                 rockchip,pins =
2332                                         <4 RK_PB0 1 &pcfg_pull_up>;
2333                         };
2334
2335                         sdmmc_bus4: sdmmc-bus4 {
2336                                 rockchip,pins =
2337                                         <4 RK_PB0 1 &pcfg_pull_up>,
2338                                         <4 RK_PB1 1 &pcfg_pull_up>,
2339                                         <4 RK_PB2 1 &pcfg_pull_up>,
2340                                         <4 RK_PB3 1 &pcfg_pull_up>;
2341                         };
2342
2343                         sdmmc_clk: sdmmc-clk {
2344                                 rockchip,pins =
2345                                         <4 RK_PB4 1 &pcfg_pull_none>;
2346                         };
2347
2348                         sdmmc_cmd: sdmmc-cmd {
2349                                 rockchip,pins =
2350                                         <4 RK_PB5 1 &pcfg_pull_up>;
2351                         };
2352
2353                         sdmmc_cd: sdmmc-cd {
2354                                 rockchip,pins =
2355                                         <0 RK_PA7 1 &pcfg_pull_up>;
2356                         };
2357
2358                         sdmmc_wp: sdmmc-wp {
2359                                 rockchip,pins =
2360                                         <0 RK_PB0 1 &pcfg_pull_up>;
2361                         };
2362                 };
2363
2364                 sleep {
2365                         ap_pwroff: ap-pwroff {
2366                                 rockchip,pins = <1 RK_PA5 1 &pcfg_pull_none>;
2367                         };
2368
2369                         ddrio_pwroff: ddrio-pwroff {
2370                                 rockchip,pins = <0 RK_PA1 1 &pcfg_pull_none>;
2371                         };
2372                 };
2373
2374                 spdif {
2375                         spdif_bus: spdif-bus {
2376                                 rockchip,pins =
2377                                         <4 RK_PC5 1 &pcfg_pull_none>;
2378                         };
2379
2380                         spdif_bus_1: spdif-bus-1 {
2381                                 rockchip,pins =
2382                                         <3 RK_PC0 3 &pcfg_pull_none>;
2383                         };
2384                 };
2385
2386                 spi0 {
2387                         spi0_clk: spi0-clk {
2388                                 rockchip,pins =
2389                                         <3 RK_PA6 2 &pcfg_pull_up>;
2390                         };
2391                         spi0_cs0: spi0-cs0 {
2392                                 rockchip,pins =
2393                                         <3 RK_PA7 2 &pcfg_pull_up>;
2394                         };
2395                         spi0_cs1: spi0-cs1 {
2396                                 rockchip,pins =
2397                                         <3 RK_PB0 2 &pcfg_pull_up>;
2398                         };
2399                         spi0_tx: spi0-tx {
2400                                 rockchip,pins =
2401                                         <3 RK_PA5 2 &pcfg_pull_up>;
2402                         };
2403                         spi0_rx: spi0-rx {
2404                                 rockchip,pins =
2405                                         <3 RK_PA4 2 &pcfg_pull_up>;
2406                         };
2407                 };
2408
2409                 spi1 {
2410                         spi1_clk: spi1-clk {
2411                                 rockchip,pins =
2412                                         <1 RK_PB1 2 &pcfg_pull_up>;
2413                         };
2414                         spi1_cs0: spi1-cs0 {
2415                                 rockchip,pins =
2416                                         <1 RK_PB2 2 &pcfg_pull_up>;
2417                         };
2418                         spi1_rx: spi1-rx {
2419                                 rockchip,pins =
2420                                         <1 RK_PA7 2 &pcfg_pull_up>;
2421                         };
2422                         spi1_tx: spi1-tx {
2423                                 rockchip,pins =
2424                                         <1 RK_PB0 2 &pcfg_pull_up>;
2425                         };
2426                 };
2427
2428                 spi2 {
2429                         spi2_clk: spi2-clk {
2430                                 rockchip,pins =
2431                                         <2 RK_PB3 1 &pcfg_pull_up>;
2432                         };
2433                         spi2_cs0: spi2-cs0 {
2434                                 rockchip,pins =
2435                                         <2 RK_PB4 1 &pcfg_pull_up>;
2436                         };
2437                         spi2_rx: spi2-rx {
2438                                 rockchip,pins =
2439                                         <2 RK_PB1 1 &pcfg_pull_up>;
2440                         };
2441                         spi2_tx: spi2-tx {
2442                                 rockchip,pins =
2443                                         <2 RK_PB2 1 &pcfg_pull_up>;
2444                         };
2445                 };
2446
2447                 spi3 {
2448                         spi3_clk: spi3-clk {
2449                                 rockchip,pins =
2450                                         <1 RK_PC1 1 &pcfg_pull_up>;
2451                         };
2452                         spi3_cs0: spi3-cs0 {
2453                                 rockchip,pins =
2454                                         <1 RK_PC2 1 &pcfg_pull_up>;
2455                         };
2456                         spi3_rx: spi3-rx {
2457                                 rockchip,pins =
2458                                         <1 RK_PB7 1 &pcfg_pull_up>;
2459                         };
2460                         spi3_tx: spi3-tx {
2461                                 rockchip,pins =
2462                                         <1 RK_PC0 1 &pcfg_pull_up>;
2463                         };
2464                 };
2465
2466                 spi4 {
2467                         spi4_clk: spi4-clk {
2468                                 rockchip,pins =
2469                                         <3 RK_PA2 2 &pcfg_pull_up>;
2470                         };
2471                         spi4_cs0: spi4-cs0 {
2472                                 rockchip,pins =
2473                                         <3 RK_PA3 2 &pcfg_pull_up>;
2474                         };
2475                         spi4_rx: spi4-rx {
2476                                 rockchip,pins =
2477                                         <3 RK_PA0 2 &pcfg_pull_up>;
2478                         };
2479                         spi4_tx: spi4-tx {
2480                                 rockchip,pins =
2481                                         <3 RK_PA1 2 &pcfg_pull_up>;
2482                         };
2483                 };
2484
2485                 spi5 {
2486                         spi5_clk: spi5-clk {
2487                                 rockchip,pins =
2488                                         <2 RK_PC6 2 &pcfg_pull_up>;
2489                         };
2490                         spi5_cs0: spi5-cs0 {
2491                                 rockchip,pins =
2492                                         <2 RK_PC7 2 &pcfg_pull_up>;
2493                         };
2494                         spi5_rx: spi5-rx {
2495                                 rockchip,pins =
2496                                         <2 RK_PC4 2 &pcfg_pull_up>;
2497                         };
2498                         spi5_tx: spi5-tx {
2499                                 rockchip,pins =
2500                                         <2 RK_PC5 2 &pcfg_pull_up>;
2501                         };
2502                 };
2503
2504                 testclk {
2505                         test_clkout0: test-clkout0 {
2506                                 rockchip,pins =
2507                                         <0 RK_PA0 1 &pcfg_pull_none>;
2508                         };
2509
2510                         test_clkout1: test-clkout1 {
2511                                 rockchip,pins =
2512                                         <2 RK_PD1 2 &pcfg_pull_none>;
2513                         };
2514
2515                         test_clkout2: test-clkout2 {
2516                                 rockchip,pins =
2517                                         <0 RK_PB0 3 &pcfg_pull_none>;
2518                         };
2519                 };
2520
2521                 tsadc {
2522                         otp_pin: otp-pin {
2523                                 rockchip,pins = <1 RK_PA6 RK_FUNC_GPIO &pcfg_pull_none>;
2524                         };
2525
2526                         otp_out: otp-out {
2527                                 rockchip,pins = <1 RK_PA6 1 &pcfg_pull_none>;
2528                         };
2529                 };
2530
2531                 uart0 {
2532                         uart0_xfer: uart0-xfer {
2533                                 rockchip,pins =
2534                                         <2 RK_PC0 1 &pcfg_pull_up>,
2535                                         <2 RK_PC1 1 &pcfg_pull_none>;
2536                         };
2537
2538                         uart0_cts: uart0-cts {
2539                                 rockchip,pins =
2540                                         <2 RK_PC2 1 &pcfg_pull_none>;
2541                         };
2542
2543                         uart0_rts: uart0-rts {
2544                                 rockchip,pins =
2545                                         <2 RK_PC3 1 &pcfg_pull_none>;
2546                         };
2547                 };
2548
2549                 uart1 {
2550                         uart1_xfer: uart1-xfer {
2551                                 rockchip,pins =
2552                                         <3 RK_PB4 2 &pcfg_pull_up>,
2553                                         <3 RK_PB5 2 &pcfg_pull_none>;
2554                         };
2555                 };
2556
2557                 uart2a {
2558                         uart2a_xfer: uart2a-xfer {
2559                                 rockchip,pins =
2560                                         <4 RK_PB0 2 &pcfg_pull_up>,
2561                                         <4 RK_PB1 2 &pcfg_pull_none>;
2562                         };
2563                 };
2564
2565                 uart2b {
2566                         uart2b_xfer: uart2b-xfer {
2567                                 rockchip,pins =
2568                                         <4 RK_PC0 2 &pcfg_pull_up>,
2569                                         <4 RK_PC1 2 &pcfg_pull_none>;
2570                         };
2571                 };
2572
2573                 uart2c {
2574                         uart2c_xfer: uart2c-xfer {
2575                                 rockchip,pins =
2576                                         <4 RK_PC3 1 &pcfg_pull_up>,
2577                                         <4 RK_PC4 1 &pcfg_pull_none>;
2578                         };
2579                 };
2580
2581                 uart3 {
2582                         uart3_xfer: uart3-xfer {
2583                                 rockchip,pins =
2584                                         <3 RK_PB6 2 &pcfg_pull_up>,
2585                                         <3 RK_PB7 2 &pcfg_pull_none>;
2586                         };
2587
2588                         uart3_cts: uart3-cts {
2589                                 rockchip,pins =
2590                                         <3 RK_PC0 2 &pcfg_pull_none>;
2591                         };
2592
2593                         uart3_rts: uart3-rts {
2594                                 rockchip,pins =
2595                                         <3 RK_PC1 2 &pcfg_pull_none>;
2596                         };
2597                 };
2598
2599                 uart4 {
2600                         uart4_xfer: uart4-xfer {
2601                                 rockchip,pins =
2602                                         <1 RK_PA7 1 &pcfg_pull_up>,
2603                                         <1 RK_PB0 1 &pcfg_pull_none>;
2604                         };
2605                 };
2606
2607                 uarthdcp {
2608                         uarthdcp_xfer: uarthdcp-xfer {
2609                                 rockchip,pins =
2610                                         <4 RK_PC5 2 &pcfg_pull_up>,
2611                                         <4 RK_PC6 2 &pcfg_pull_none>;
2612                         };
2613                 };
2614
2615                 pwm0 {
2616                         pwm0_pin: pwm0-pin {
2617                                 rockchip,pins =
2618                                         <4 RK_PC2 1 &pcfg_pull_none>;
2619                         };
2620
2621                         pwm0_pin_pull_down: pwm0-pin-pull-down {
2622                                 rockchip,pins =
2623                                         <4 RK_PC2 1 &pcfg_pull_down>;
2624                         };
2625
2626                         vop0_pwm_pin: vop0-pwm-pin {
2627                                 rockchip,pins =
2628                                         <4 RK_PC2 2 &pcfg_pull_none>;
2629                         };
2630
2631                         vop1_pwm_pin: vop1-pwm-pin {
2632                                 rockchip,pins =
2633                                         <4 RK_PC2 3 &pcfg_pull_none>;
2634                         };
2635                 };
2636
2637                 pwm1 {
2638                         pwm1_pin: pwm1-pin {
2639                                 rockchip,pins =
2640                                         <4 RK_PC6 1 &pcfg_pull_none>;
2641                         };
2642
2643                         pwm1_pin_pull_down: pwm1-pin-pull-down {
2644                                 rockchip,pins =
2645                                         <4 RK_PC6 1 &pcfg_pull_down>;
2646                         };
2647                 };
2648
2649                 pwm2 {
2650                         pwm2_pin: pwm2-pin {
2651                                 rockchip,pins =
2652                                         <1 RK_PC3 1 &pcfg_pull_none>;
2653                         };
2654
2655                         pwm2_pin_pull_down: pwm2-pin-pull-down {
2656                                 rockchip,pins =
2657                                         <1 RK_PC3 1 &pcfg_pull_down>;
2658                         };
2659                 };
2660
2661                 pwm3a {
2662                         pwm3a_pin: pwm3a-pin {
2663                                 rockchip,pins =
2664                                         <0 RK_PA6 1 &pcfg_pull_none>;
2665                         };
2666                 };
2667
2668                 pwm3b {
2669                         pwm3b_pin: pwm3b-pin {
2670                                 rockchip,pins =
2671                                         <1 RK_PB6 1 &pcfg_pull_none>;
2672                         };
2673                 };
2674
2675                 hdmi {
2676                         hdmi_i2c_xfer: hdmi-i2c-xfer {
2677                                 rockchip,pins =
2678                                         <4 RK_PC1 3 &pcfg_pull_none>,
2679                                         <4 RK_PC0 3 &pcfg_pull_none>;
2680                         };
2681
2682                         hdmi_cec: hdmi-cec {
2683                                 rockchip,pins =
2684                                         <4 RK_PC7 1 &pcfg_pull_none>;
2685                         };
2686                 };
2687
2688                 pcie {
2689                         pcie_clkreqn_cpm: pci-clkreqn-cpm {
2690                                 rockchip,pins =
2691                                         <2 RK_PD2 RK_FUNC_GPIO &pcfg_pull_none>;
2692                         };
2693
2694                         pcie_clkreqnb_cpm: pci-clkreqnb-cpm {
2695                                 rockchip,pins =
2696                                         <4 RK_PD0 RK_FUNC_GPIO &pcfg_pull_none>;
2697                         };
2698                 };
2699
2700         };
2701 };