1 // SPDX-License-Identifier: BSD-3-Clause
3 * SC7180 SoC device tree source
5 * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
12 #include <dt-bindings/clock/qcom,rpmh.h>
13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sc7180.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
18 #include <dt-bindings/power/qcom-aoss-qmp.h>
19 #include <dt-bindings/power/qcom-rpmpd.h>
20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
23 #include <dt-bindings/thermal/thermal.h>
26 interrupt-parent = <&intc>;
60 compatible = "fixed-clock";
61 clock-frequency = <38400000>;
65 sleep_clk: sleep-clk {
66 compatible = "fixed-clock";
67 clock-frequency = <32764>;
72 reserved_memory: reserved-memory {
77 hyp_mem: memory@80000000 {
78 reg = <0x0 0x80000000 0x0 0x600000>;
82 xbl_mem: memory@80600000 {
83 reg = <0x0 0x80600000 0x0 0x200000>;
87 aop_mem: memory@80800000 {
88 reg = <0x0 0x80800000 0x0 0x20000>;
92 aop_cmd_db_mem: memory@80820000 {
93 reg = <0x0 0x80820000 0x0 0x20000>;
94 compatible = "qcom,cmd-db";
98 sec_apps_mem: memory@808ff000 {
99 reg = <0x0 0x808ff000 0x0 0x1000>;
103 smem_mem: memory@80900000 {
104 reg = <0x0 0x80900000 0x0 0x200000>;
108 tz_mem: memory@80b00000 {
109 reg = <0x0 0x80b00000 0x0 0x3900000>;
113 ipa_fw_mem: memory@8b700000 {
114 reg = <0 0x8b700000 0 0x10000>;
118 rmtfs_mem: memory@94600000 {
119 compatible = "qcom,rmtfs-mem";
120 reg = <0x0 0x94600000 0x0 0x200000>;
123 qcom,client-id = <1>;
129 #address-cells = <2>;
134 compatible = "qcom,kryo468";
136 enable-method = "psci";
137 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
140 capacity-dmips-mhz = <1024>;
141 dynamic-power-coefficient = <100>;
142 operating-points-v2 = <&cpu0_opp_table>;
143 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
144 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
145 next-level-cache = <&L2_0>;
146 #cooling-cells = <2>;
147 qcom,freq-domain = <&cpufreq_hw 0>;
149 compatible = "cache";
150 next-level-cache = <&L3_0>;
152 compatible = "cache";
159 compatible = "qcom,kryo468";
161 enable-method = "psci";
162 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
165 capacity-dmips-mhz = <1024>;
166 dynamic-power-coefficient = <100>;
167 next-level-cache = <&L2_100>;
168 operating-points-v2 = <&cpu0_opp_table>;
169 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
170 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
171 #cooling-cells = <2>;
172 qcom,freq-domain = <&cpufreq_hw 0>;
174 compatible = "cache";
175 next-level-cache = <&L3_0>;
181 compatible = "qcom,kryo468";
183 enable-method = "psci";
184 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
187 capacity-dmips-mhz = <1024>;
188 dynamic-power-coefficient = <100>;
189 next-level-cache = <&L2_200>;
190 operating-points-v2 = <&cpu0_opp_table>;
191 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
192 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
193 #cooling-cells = <2>;
194 qcom,freq-domain = <&cpufreq_hw 0>;
196 compatible = "cache";
197 next-level-cache = <&L3_0>;
203 compatible = "qcom,kryo468";
205 enable-method = "psci";
206 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
209 capacity-dmips-mhz = <1024>;
210 dynamic-power-coefficient = <100>;
211 next-level-cache = <&L2_300>;
212 operating-points-v2 = <&cpu0_opp_table>;
213 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
214 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
215 #cooling-cells = <2>;
216 qcom,freq-domain = <&cpufreq_hw 0>;
218 compatible = "cache";
219 next-level-cache = <&L3_0>;
225 compatible = "qcom,kryo468";
227 enable-method = "psci";
228 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
231 capacity-dmips-mhz = <1024>;
232 dynamic-power-coefficient = <100>;
233 next-level-cache = <&L2_400>;
234 operating-points-v2 = <&cpu0_opp_table>;
235 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
236 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
237 #cooling-cells = <2>;
238 qcom,freq-domain = <&cpufreq_hw 0>;
240 compatible = "cache";
241 next-level-cache = <&L3_0>;
247 compatible = "qcom,kryo468";
249 enable-method = "psci";
250 cpu-idle-states = <&LITTLE_CPU_SLEEP_0
253 capacity-dmips-mhz = <1024>;
254 dynamic-power-coefficient = <100>;
255 next-level-cache = <&L2_500>;
256 operating-points-v2 = <&cpu0_opp_table>;
257 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
258 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
259 #cooling-cells = <2>;
260 qcom,freq-domain = <&cpufreq_hw 0>;
262 compatible = "cache";
263 next-level-cache = <&L3_0>;
269 compatible = "qcom,kryo468";
271 enable-method = "psci";
272 cpu-idle-states = <&BIG_CPU_SLEEP_0
275 capacity-dmips-mhz = <1740>;
276 dynamic-power-coefficient = <405>;
277 next-level-cache = <&L2_600>;
278 operating-points-v2 = <&cpu6_opp_table>;
279 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
280 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
281 #cooling-cells = <2>;
282 qcom,freq-domain = <&cpufreq_hw 1>;
284 compatible = "cache";
285 next-level-cache = <&L3_0>;
291 compatible = "qcom,kryo468";
293 enable-method = "psci";
294 cpu-idle-states = <&BIG_CPU_SLEEP_0
297 capacity-dmips-mhz = <1740>;
298 dynamic-power-coefficient = <405>;
299 next-level-cache = <&L2_700>;
300 operating-points-v2 = <&cpu6_opp_table>;
301 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
302 <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
303 #cooling-cells = <2>;
304 qcom,freq-domain = <&cpufreq_hw 1>;
306 compatible = "cache";
307 next-level-cache = <&L3_0>;
348 entry-method = "psci";
350 LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
351 compatible = "arm,idle-state";
352 idle-state-name = "little-power-down";
353 arm,psci-suspend-param = <0x40000003>;
354 entry-latency-us = <549>;
355 exit-latency-us = <901>;
356 min-residency-us = <1774>;
360 LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
361 compatible = "arm,idle-state";
362 idle-state-name = "little-rail-power-down";
363 arm,psci-suspend-param = <0x40000004>;
364 entry-latency-us = <702>;
365 exit-latency-us = <915>;
366 min-residency-us = <4001>;
370 BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
371 compatible = "arm,idle-state";
372 idle-state-name = "big-power-down";
373 arm,psci-suspend-param = <0x40000003>;
374 entry-latency-us = <523>;
375 exit-latency-us = <1244>;
376 min-residency-us = <2207>;
380 BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
381 compatible = "arm,idle-state";
382 idle-state-name = "big-rail-power-down";
383 arm,psci-suspend-param = <0x40000004>;
384 entry-latency-us = <526>;
385 exit-latency-us = <1854>;
386 min-residency-us = <5555>;
390 CLUSTER_SLEEP_0: cluster-sleep-0 {
391 compatible = "arm,idle-state";
392 idle-state-name = "cluster-power-down";
393 arm,psci-suspend-param = <0x40003444>;
394 entry-latency-us = <3263>;
395 exit-latency-us = <6562>;
396 min-residency-us = <9926>;
402 cpu0_opp_table: cpu0_opp_table {
403 compatible = "operating-points-v2";
406 cpu0_opp1: opp-300000000 {
407 opp-hz = /bits/ 64 <300000000>;
408 opp-peak-kBps = <1200000 4800000>;
411 cpu0_opp2: opp-576000000 {
412 opp-hz = /bits/ 64 <576000000>;
413 opp-peak-kBps = <1200000 4800000>;
416 cpu0_opp3: opp-768000000 {
417 opp-hz = /bits/ 64 <768000000>;
418 opp-peak-kBps = <1200000 4800000>;
421 cpu0_opp4: opp-1017600000 {
422 opp-hz = /bits/ 64 <1017600000>;
423 opp-peak-kBps = <1804000 8908800>;
426 cpu0_opp5: opp-1248000000 {
427 opp-hz = /bits/ 64 <1248000000>;
428 opp-peak-kBps = <2188000 12902400>;
431 cpu0_opp6: opp-1324800000 {
432 opp-hz = /bits/ 64 <1324800000>;
433 opp-peak-kBps = <2188000 12902400>;
436 cpu0_opp7: opp-1516800000 {
437 opp-hz = /bits/ 64 <1516800000>;
438 opp-peak-kBps = <3072000 15052800>;
441 cpu0_opp8: opp-1612800000 {
442 opp-hz = /bits/ 64 <1612800000>;
443 opp-peak-kBps = <3072000 15052800>;
446 cpu0_opp9: opp-1708800000 {
447 opp-hz = /bits/ 64 <1708800000>;
448 opp-peak-kBps = <3072000 15052800>;
451 cpu0_opp10: opp-1804800000 {
452 opp-hz = /bits/ 64 <1804800000>;
453 opp-peak-kBps = <4068000 22425600>;
457 cpu6_opp_table: cpu6_opp_table {
458 compatible = "operating-points-v2";
461 cpu6_opp1: opp-300000000 {
462 opp-hz = /bits/ 64 <300000000>;
463 opp-peak-kBps = <2188000 8908800>;
466 cpu6_opp2: opp-652800000 {
467 opp-hz = /bits/ 64 <652800000>;
468 opp-peak-kBps = <2188000 8908800>;
471 cpu6_opp3: opp-825600000 {
472 opp-hz = /bits/ 64 <825600000>;
473 opp-peak-kBps = <2188000 8908800>;
476 cpu6_opp4: opp-979200000 {
477 opp-hz = /bits/ 64 <979200000>;
478 opp-peak-kBps = <2188000 8908800>;
481 cpu6_opp5: opp-1113600000 {
482 opp-hz = /bits/ 64 <1113600000>;
483 opp-peak-kBps = <2188000 8908800>;
486 cpu6_opp6: opp-1267200000 {
487 opp-hz = /bits/ 64 <1267200000>;
488 opp-peak-kBps = <4068000 12902400>;
491 cpu6_opp7: opp-1555200000 {
492 opp-hz = /bits/ 64 <1555200000>;
493 opp-peak-kBps = <4068000 15052800>;
496 cpu6_opp8: opp-1708800000 {
497 opp-hz = /bits/ 64 <1708800000>;
498 opp-peak-kBps = <6220000 19353600>;
501 cpu6_opp9: opp-1843200000 {
502 opp-hz = /bits/ 64 <1843200000>;
503 opp-peak-kBps = <6220000 19353600>;
506 cpu6_opp10: opp-1900800000 {
507 opp-hz = /bits/ 64 <1900800000>;
508 opp-peak-kBps = <6220000 22425600>;
511 cpu6_opp11: opp-1996800000 {
512 opp-hz = /bits/ 64 <1996800000>;
513 opp-peak-kBps = <6220000 22425600>;
516 cpu6_opp12: opp-2112000000 {
517 opp-hz = /bits/ 64 <2112000000>;
518 opp-peak-kBps = <6220000 22425600>;
521 cpu6_opp13: opp-2208000000 {
522 opp-hz = /bits/ 64 <2208000000>;
523 opp-peak-kBps = <7216000 22425600>;
526 cpu6_opp14: opp-2323200000 {
527 opp-hz = /bits/ 64 <2323200000>;
528 opp-peak-kBps = <7216000 22425600>;
531 cpu6_opp15: opp-2400000000 {
532 opp-hz = /bits/ 64 <2400000000>;
533 opp-peak-kBps = <8532000 23347200>;
536 cpu6_opp16: opp-2553600000 {
537 opp-hz = /bits/ 64 <2553600000>;
538 opp-peak-kBps = <8532000 23347200>;
543 device_type = "memory";
544 /* We expect the bootloader to fill in the size */
545 reg = <0 0x80000000 0 0>;
549 compatible = "arm,armv8-pmuv3";
550 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
555 compatible = "qcom,scm-sc7180", "qcom,scm";
560 compatible = "qcom,tcsr-mutex";
561 syscon = <&tcsr_mutex_regs 0 0x1000>;
566 compatible = "qcom,smem";
567 memory-region = <&smem_mem>;
568 hwlocks = <&tcsr_mutex 3>;
572 compatible = "qcom,smp2p";
573 qcom,smem = <94>, <432>;
575 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
577 mboxes = <&apss_shared 6>;
579 qcom,local-pid = <0>;
580 qcom,remote-pid = <5>;
582 cdsp_smp2p_out: master-kernel {
583 qcom,entry-name = "master-kernel";
584 #qcom,smem-state-cells = <1>;
587 cdsp_smp2p_in: slave-kernel {
588 qcom,entry-name = "slave-kernel";
590 interrupt-controller;
591 #interrupt-cells = <2>;
596 compatible = "qcom,smp2p";
597 qcom,smem = <443>, <429>;
599 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
601 mboxes = <&apss_shared 10>;
603 qcom,local-pid = <0>;
604 qcom,remote-pid = <2>;
606 adsp_smp2p_out: master-kernel {
607 qcom,entry-name = "master-kernel";
608 #qcom,smem-state-cells = <1>;
611 adsp_smp2p_in: slave-kernel {
612 qcom,entry-name = "slave-kernel";
614 interrupt-controller;
615 #interrupt-cells = <2>;
620 compatible = "qcom,smp2p";
621 qcom,smem = <435>, <428>;
622 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
623 mboxes = <&apss_shared 14>;
624 qcom,local-pid = <0>;
625 qcom,remote-pid = <1>;
627 modem_smp2p_out: master-kernel {
628 qcom,entry-name = "master-kernel";
629 #qcom,smem-state-cells = <1>;
632 modem_smp2p_in: slave-kernel {
633 qcom,entry-name = "slave-kernel";
634 interrupt-controller;
635 #interrupt-cells = <2>;
638 ipa_smp2p_out: ipa-ap-to-modem {
639 qcom,entry-name = "ipa";
640 #qcom,smem-state-cells = <1>;
643 ipa_smp2p_in: ipa-modem-to-ap {
644 qcom,entry-name = "ipa";
645 interrupt-controller;
646 #interrupt-cells = <2>;
651 compatible = "arm,psci-1.0";
656 #address-cells = <2>;
658 ranges = <0 0 0 0 0x10 0>;
659 dma-ranges = <0 0 0 0 0x10 0>;
660 compatible = "simple-bus";
662 gcc: clock-controller@100000 {
663 compatible = "qcom,gcc-sc7180";
664 reg = <0 0x00100000 0 0x1f0000>;
665 clocks = <&rpmhcc RPMH_CXO_CLK>,
666 <&rpmhcc RPMH_CXO_CLK_A>,
668 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
671 #power-domain-cells = <1>;
674 qfprom: efuse@784000 {
675 compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
676 reg = <0 0x00784000 0 0x7a0>,
677 <0 0x00780000 0 0x7a0>,
678 <0 0x00782000 0 0x100>,
679 <0 0x00786000 0 0x1fff>;
681 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
682 clock-names = "core";
683 #address-cells = <1>;
686 qusb2p_hstx_trim: hstx-trim-primary@25b {
691 gpu_speed_bin: gpu_speed_bin@1d2 {
697 sdhc_1: sdhci@7c4000 {
698 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
699 reg = <0 0x7c4000 0 0x1000>,
700 <0 0x07c5000 0 0x1000>;
701 reg-names = "hc", "cqhci";
703 iommus = <&apps_smmu 0x60 0x0>;
704 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
705 <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
706 interrupt-names = "hc_irq", "pwr_irq";
708 clocks = <&gcc GCC_SDCC1_APPS_CLK>,
709 <&gcc GCC_SDCC1_AHB_CLK>,
710 <&rpmhcc RPMH_CXO_CLK>;
711 clock-names = "core", "iface", "xo";
712 interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
713 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
714 interconnect-names = "sdhc-ddr","cpu-sdhc";
715 power-domains = <&rpmhpd SC7180_CX>;
716 operating-points-v2 = <&sdhc1_opp_table>;
725 mmc-hs400-enhanced-strobe;
729 sdhc1_opp_table: sdhc1-opp-table {
730 compatible = "operating-points-v2";
733 opp-hz = /bits/ 64 <100000000>;
734 required-opps = <&rpmhpd_opp_low_svs>;
735 opp-peak-kBps = <1800000 600000>;
736 opp-avg-kBps = <100000 0>;
740 opp-hz = /bits/ 64 <384000000>;
741 required-opps = <&rpmhpd_opp_nom>;
742 opp-peak-kBps = <5400000 1600000>;
743 opp-avg-kBps = <390000 0>;
748 qup_opp_table: qup-opp-table {
749 compatible = "operating-points-v2";
752 opp-hz = /bits/ 64 <75000000>;
753 required-opps = <&rpmhpd_opp_low_svs>;
757 opp-hz = /bits/ 64 <100000000>;
758 required-opps = <&rpmhpd_opp_svs>;
762 opp-hz = /bits/ 64 <128000000>;
763 required-opps = <&rpmhpd_opp_nom>;
767 qupv3_id_0: geniqup@8c0000 {
768 compatible = "qcom,geni-se-qup";
769 reg = <0 0x008c0000 0 0x6000>;
770 clock-names = "m-ahb", "s-ahb";
771 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
772 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
773 #address-cells = <2>;
776 iommus = <&apps_smmu 0x43 0x0>;
780 compatible = "qcom,geni-i2c";
781 reg = <0 0x00880000 0 0x4000>;
783 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
784 pinctrl-names = "default";
785 pinctrl-0 = <&qup_i2c0_default>;
786 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
787 #address-cells = <1>;
789 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
790 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
791 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
792 interconnect-names = "qup-core", "qup-config",
794 power-domains = <&rpmhpd SC7180_CX>;
795 required-opps = <&rpmhpd_opp_low_svs>;
800 compatible = "qcom,geni-spi";
801 reg = <0 0x00880000 0 0x4000>;
803 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
804 pinctrl-names = "default";
805 pinctrl-0 = <&qup_spi0_default>;
806 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
807 #address-cells = <1>;
809 power-domains = <&rpmhpd SC7180_CX>;
810 operating-points-v2 = <&qup_opp_table>;
811 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
812 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
813 interconnect-names = "qup-core", "qup-config";
817 uart0: serial@880000 {
818 compatible = "qcom,geni-uart";
819 reg = <0 0x00880000 0 0x4000>;
821 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
822 pinctrl-names = "default";
823 pinctrl-0 = <&qup_uart0_default>;
824 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
825 power-domains = <&rpmhpd SC7180_CX>;
826 operating-points-v2 = <&qup_opp_table>;
827 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
828 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
829 interconnect-names = "qup-core", "qup-config";
834 compatible = "qcom,geni-i2c";
835 reg = <0 0x00884000 0 0x4000>;
837 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
838 pinctrl-names = "default";
839 pinctrl-0 = <&qup_i2c1_default>;
840 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
841 #address-cells = <1>;
843 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
844 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
845 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
846 interconnect-names = "qup-core", "qup-config",
848 power-domains = <&rpmhpd SC7180_CX>;
849 required-opps = <&rpmhpd_opp_low_svs>;
854 compatible = "qcom,geni-spi";
855 reg = <0 0x00884000 0 0x4000>;
857 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
858 pinctrl-names = "default";
859 pinctrl-0 = <&qup_spi1_default>;
860 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
861 #address-cells = <1>;
863 power-domains = <&rpmhpd SC7180_CX>;
864 operating-points-v2 = <&qup_opp_table>;
865 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
866 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
867 interconnect-names = "qup-core", "qup-config";
871 uart1: serial@884000 {
872 compatible = "qcom,geni-uart";
873 reg = <0 0x00884000 0 0x4000>;
875 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
876 pinctrl-names = "default";
877 pinctrl-0 = <&qup_uart1_default>;
878 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
879 power-domains = <&rpmhpd SC7180_CX>;
880 operating-points-v2 = <&qup_opp_table>;
881 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
882 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
883 interconnect-names = "qup-core", "qup-config";
888 compatible = "qcom,geni-i2c";
889 reg = <0 0x00888000 0 0x4000>;
891 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
892 pinctrl-names = "default";
893 pinctrl-0 = <&qup_i2c2_default>;
894 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
895 #address-cells = <1>;
897 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
898 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
899 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
900 interconnect-names = "qup-core", "qup-config",
902 power-domains = <&rpmhpd SC7180_CX>;
903 required-opps = <&rpmhpd_opp_low_svs>;
907 uart2: serial@888000 {
908 compatible = "qcom,geni-uart";
909 reg = <0 0x00888000 0 0x4000>;
911 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
912 pinctrl-names = "default";
913 pinctrl-0 = <&qup_uart2_default>;
914 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
915 power-domains = <&rpmhpd SC7180_CX>;
916 operating-points-v2 = <&qup_opp_table>;
917 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
918 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
919 interconnect-names = "qup-core", "qup-config";
924 compatible = "qcom,geni-i2c";
925 reg = <0 0x0088c000 0 0x4000>;
927 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
928 pinctrl-names = "default";
929 pinctrl-0 = <&qup_i2c3_default>;
930 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
931 #address-cells = <1>;
933 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
934 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
935 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
936 interconnect-names = "qup-core", "qup-config",
938 power-domains = <&rpmhpd SC7180_CX>;
939 required-opps = <&rpmhpd_opp_low_svs>;
944 compatible = "qcom,geni-spi";
945 reg = <0 0x0088c000 0 0x4000>;
947 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
948 pinctrl-names = "default";
949 pinctrl-0 = <&qup_spi3_default>;
950 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
951 #address-cells = <1>;
953 power-domains = <&rpmhpd SC7180_CX>;
954 operating-points-v2 = <&qup_opp_table>;
955 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
956 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
957 interconnect-names = "qup-core", "qup-config";
961 uart3: serial@88c000 {
962 compatible = "qcom,geni-uart";
963 reg = <0 0x0088c000 0 0x4000>;
965 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
966 pinctrl-names = "default";
967 pinctrl-0 = <&qup_uart3_default>;
968 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
969 power-domains = <&rpmhpd SC7180_CX>;
970 operating-points-v2 = <&qup_opp_table>;
971 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
972 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
973 interconnect-names = "qup-core", "qup-config";
978 compatible = "qcom,geni-i2c";
979 reg = <0 0x00890000 0 0x4000>;
981 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
982 pinctrl-names = "default";
983 pinctrl-0 = <&qup_i2c4_default>;
984 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
985 #address-cells = <1>;
987 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
988 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
989 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
990 interconnect-names = "qup-core", "qup-config",
992 power-domains = <&rpmhpd SC7180_CX>;
993 required-opps = <&rpmhpd_opp_low_svs>;
997 uart4: serial@890000 {
998 compatible = "qcom,geni-uart";
999 reg = <0 0x00890000 0 0x4000>;
1001 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
1002 pinctrl-names = "default";
1003 pinctrl-0 = <&qup_uart4_default>;
1004 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
1005 power-domains = <&rpmhpd SC7180_CX>;
1006 operating-points-v2 = <&qup_opp_table>;
1007 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1008 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1009 interconnect-names = "qup-core", "qup-config";
1010 status = "disabled";
1014 compatible = "qcom,geni-i2c";
1015 reg = <0 0x00894000 0 0x4000>;
1017 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1018 pinctrl-names = "default";
1019 pinctrl-0 = <&qup_i2c5_default>;
1020 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1021 #address-cells = <1>;
1023 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1024 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1025 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1026 interconnect-names = "qup-core", "qup-config",
1028 power-domains = <&rpmhpd SC7180_CX>;
1029 required-opps = <&rpmhpd_opp_low_svs>;
1030 status = "disabled";
1034 compatible = "qcom,geni-spi";
1035 reg = <0 0x00894000 0 0x4000>;
1037 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1038 pinctrl-names = "default";
1039 pinctrl-0 = <&qup_spi5_default>;
1040 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1041 #address-cells = <1>;
1043 power-domains = <&rpmhpd SC7180_CX>;
1044 operating-points-v2 = <&qup_opp_table>;
1045 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1046 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1047 interconnect-names = "qup-core", "qup-config";
1048 status = "disabled";
1051 uart5: serial@894000 {
1052 compatible = "qcom,geni-uart";
1053 reg = <0 0x00894000 0 0x4000>;
1055 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1056 pinctrl-names = "default";
1057 pinctrl-0 = <&qup_uart5_default>;
1058 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1059 power-domains = <&rpmhpd SC7180_CX>;
1060 operating-points-v2 = <&qup_opp_table>;
1061 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1062 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1063 interconnect-names = "qup-core", "qup-config";
1064 status = "disabled";
1068 qupv3_id_1: geniqup@ac0000 {
1069 compatible = "qcom,geni-se-qup";
1070 reg = <0 0x00ac0000 0 0x6000>;
1071 clock-names = "m-ahb", "s-ahb";
1072 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1073 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1074 #address-cells = <2>;
1077 iommus = <&apps_smmu 0x4c3 0x0>;
1078 status = "disabled";
1081 compatible = "qcom,geni-i2c";
1082 reg = <0 0x00a80000 0 0x4000>;
1084 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1085 pinctrl-names = "default";
1086 pinctrl-0 = <&qup_i2c6_default>;
1087 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1088 #address-cells = <1>;
1090 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1091 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1092 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1093 interconnect-names = "qup-core", "qup-config",
1095 power-domains = <&rpmhpd SC7180_CX>;
1096 required-opps = <&rpmhpd_opp_low_svs>;
1097 status = "disabled";
1101 compatible = "qcom,geni-spi";
1102 reg = <0 0x00a80000 0 0x4000>;
1104 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1105 pinctrl-names = "default";
1106 pinctrl-0 = <&qup_spi6_default>;
1107 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1108 #address-cells = <1>;
1110 power-domains = <&rpmhpd SC7180_CX>;
1111 operating-points-v2 = <&qup_opp_table>;
1112 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1113 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1114 interconnect-names = "qup-core", "qup-config";
1115 status = "disabled";
1118 uart6: serial@a80000 {
1119 compatible = "qcom,geni-uart";
1120 reg = <0 0x00a80000 0 0x4000>;
1122 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1123 pinctrl-names = "default";
1124 pinctrl-0 = <&qup_uart6_default>;
1125 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1126 power-domains = <&rpmhpd SC7180_CX>;
1127 operating-points-v2 = <&qup_opp_table>;
1128 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1129 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1130 interconnect-names = "qup-core", "qup-config";
1131 status = "disabled";
1135 compatible = "qcom,geni-i2c";
1136 reg = <0 0x00a84000 0 0x4000>;
1138 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1139 pinctrl-names = "default";
1140 pinctrl-0 = <&qup_i2c7_default>;
1141 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1142 #address-cells = <1>;
1144 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1145 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1146 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1147 interconnect-names = "qup-core", "qup-config",
1149 power-domains = <&rpmhpd SC7180_CX>;
1150 required-opps = <&rpmhpd_opp_low_svs>;
1151 status = "disabled";
1154 uart7: serial@a84000 {
1155 compatible = "qcom,geni-uart";
1156 reg = <0 0x00a84000 0 0x4000>;
1158 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1159 pinctrl-names = "default";
1160 pinctrl-0 = <&qup_uart7_default>;
1161 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1162 power-domains = <&rpmhpd SC7180_CX>;
1163 operating-points-v2 = <&qup_opp_table>;
1164 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1165 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1166 interconnect-names = "qup-core", "qup-config";
1167 status = "disabled";
1171 compatible = "qcom,geni-i2c";
1172 reg = <0 0x00a88000 0 0x4000>;
1174 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1175 pinctrl-names = "default";
1176 pinctrl-0 = <&qup_i2c8_default>;
1177 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1178 #address-cells = <1>;
1180 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1181 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1182 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1183 interconnect-names = "qup-core", "qup-config",
1185 power-domains = <&rpmhpd SC7180_CX>;
1186 required-opps = <&rpmhpd_opp_low_svs>;
1187 status = "disabled";
1191 compatible = "qcom,geni-spi";
1192 reg = <0 0x00a88000 0 0x4000>;
1194 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1195 pinctrl-names = "default";
1196 pinctrl-0 = <&qup_spi8_default>;
1197 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1198 #address-cells = <1>;
1200 power-domains = <&rpmhpd SC7180_CX>;
1201 operating-points-v2 = <&qup_opp_table>;
1202 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1203 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1204 interconnect-names = "qup-core", "qup-config";
1205 status = "disabled";
1208 uart8: serial@a88000 {
1209 compatible = "qcom,geni-debug-uart";
1210 reg = <0 0x00a88000 0 0x4000>;
1212 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1213 pinctrl-names = "default";
1214 pinctrl-0 = <&qup_uart8_default>;
1215 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1216 power-domains = <&rpmhpd SC7180_CX>;
1217 operating-points-v2 = <&qup_opp_table>;
1218 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1219 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1220 interconnect-names = "qup-core", "qup-config";
1221 status = "disabled";
1225 compatible = "qcom,geni-i2c";
1226 reg = <0 0x00a8c000 0 0x4000>;
1228 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1229 pinctrl-names = "default";
1230 pinctrl-0 = <&qup_i2c9_default>;
1231 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1232 #address-cells = <1>;
1234 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1235 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1236 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1237 interconnect-names = "qup-core", "qup-config",
1239 power-domains = <&rpmhpd SC7180_CX>;
1240 required-opps = <&rpmhpd_opp_low_svs>;
1241 status = "disabled";
1244 uart9: serial@a8c000 {
1245 compatible = "qcom,geni-uart";
1246 reg = <0 0x00a8c000 0 0x4000>;
1248 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1249 pinctrl-names = "default";
1250 pinctrl-0 = <&qup_uart9_default>;
1251 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1252 power-domains = <&rpmhpd SC7180_CX>;
1253 operating-points-v2 = <&qup_opp_table>;
1254 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1255 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1256 interconnect-names = "qup-core", "qup-config";
1257 status = "disabled";
1261 compatible = "qcom,geni-i2c";
1262 reg = <0 0x00a90000 0 0x4000>;
1264 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1265 pinctrl-names = "default";
1266 pinctrl-0 = <&qup_i2c10_default>;
1267 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1268 #address-cells = <1>;
1270 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1271 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1272 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1273 interconnect-names = "qup-core", "qup-config",
1275 power-domains = <&rpmhpd SC7180_CX>;
1276 required-opps = <&rpmhpd_opp_low_svs>;
1277 status = "disabled";
1281 compatible = "qcom,geni-spi";
1282 reg = <0 0x00a90000 0 0x4000>;
1284 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&qup_spi10_default>;
1287 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1288 #address-cells = <1>;
1290 power-domains = <&rpmhpd SC7180_CX>;
1291 operating-points-v2 = <&qup_opp_table>;
1292 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1293 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1294 interconnect-names = "qup-core", "qup-config";
1295 status = "disabled";
1298 uart10: serial@a90000 {
1299 compatible = "qcom,geni-uart";
1300 reg = <0 0x00a90000 0 0x4000>;
1302 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1303 pinctrl-names = "default";
1304 pinctrl-0 = <&qup_uart10_default>;
1305 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1306 power-domains = <&rpmhpd SC7180_CX>;
1307 operating-points-v2 = <&qup_opp_table>;
1308 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1309 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1310 interconnect-names = "qup-core", "qup-config";
1311 status = "disabled";
1315 compatible = "qcom,geni-i2c";
1316 reg = <0 0x00a94000 0 0x4000>;
1318 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1319 pinctrl-names = "default";
1320 pinctrl-0 = <&qup_i2c11_default>;
1321 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1322 #address-cells = <1>;
1324 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1325 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1326 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1327 interconnect-names = "qup-core", "qup-config",
1329 power-domains = <&rpmhpd SC7180_CX>;
1330 required-opps = <&rpmhpd_opp_low_svs>;
1331 status = "disabled";
1335 compatible = "qcom,geni-spi";
1336 reg = <0 0x00a94000 0 0x4000>;
1338 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1339 pinctrl-names = "default";
1340 pinctrl-0 = <&qup_spi11_default>;
1341 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1342 #address-cells = <1>;
1344 power-domains = <&rpmhpd SC7180_CX>;
1345 operating-points-v2 = <&qup_opp_table>;
1346 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1347 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1348 interconnect-names = "qup-core", "qup-config";
1349 status = "disabled";
1352 uart11: serial@a94000 {
1353 compatible = "qcom,geni-uart";
1354 reg = <0 0x00a94000 0 0x4000>;
1356 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1357 pinctrl-names = "default";
1358 pinctrl-0 = <&qup_uart11_default>;
1359 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1360 power-domains = <&rpmhpd SC7180_CX>;
1361 operating-points-v2 = <&qup_opp_table>;
1362 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1363 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1364 interconnect-names = "qup-core", "qup-config";
1365 status = "disabled";
1369 config_noc: interconnect@1500000 {
1370 compatible = "qcom,sc7180-config-noc";
1371 reg = <0 0x01500000 0 0x28000>;
1372 #interconnect-cells = <2>;
1373 qcom,bcm-voters = <&apps_bcm_voter>;
1376 system_noc: interconnect@1620000 {
1377 compatible = "qcom,sc7180-system-noc";
1378 reg = <0 0x01620000 0 0x17080>;
1379 #interconnect-cells = <2>;
1380 qcom,bcm-voters = <&apps_bcm_voter>;
1383 mc_virt: interconnect@1638000 {
1384 compatible = "qcom,sc7180-mc-virt";
1385 reg = <0 0x01638000 0 0x1000>;
1386 #interconnect-cells = <2>;
1387 qcom,bcm-voters = <&apps_bcm_voter>;
1390 qup_virt: interconnect@1650000 {
1391 compatible = "qcom,sc7180-qup-virt";
1392 reg = <0 0x01650000 0 0x1000>;
1393 #interconnect-cells = <2>;
1394 qcom,bcm-voters = <&apps_bcm_voter>;
1397 aggre1_noc: interconnect@16e0000 {
1398 compatible = "qcom,sc7180-aggre1-noc";
1399 reg = <0 0x016e0000 0 0x15080>;
1400 #interconnect-cells = <2>;
1401 qcom,bcm-voters = <&apps_bcm_voter>;
1404 aggre2_noc: interconnect@1705000 {
1405 compatible = "qcom,sc7180-aggre2-noc";
1406 reg = <0 0x01705000 0 0x9000>;
1407 #interconnect-cells = <2>;
1408 qcom,bcm-voters = <&apps_bcm_voter>;
1411 compute_noc: interconnect@170e000 {
1412 compatible = "qcom,sc7180-compute-noc";
1413 reg = <0 0x0170e000 0 0x6000>;
1414 #interconnect-cells = <2>;
1415 qcom,bcm-voters = <&apps_bcm_voter>;
1418 mmss_noc: interconnect@1740000 {
1419 compatible = "qcom,sc7180-mmss-noc";
1420 reg = <0 0x01740000 0 0x1c100>;
1421 #interconnect-cells = <2>;
1422 qcom,bcm-voters = <&apps_bcm_voter>;
1425 ipa_virt: interconnect@1e00000 {
1426 compatible = "qcom,sc7180-ipa-virt";
1427 reg = <0 0x01e00000 0 0x1000>;
1428 #interconnect-cells = <2>;
1429 qcom,bcm-voters = <&apps_bcm_voter>;
1433 compatible = "qcom,sc7180-ipa";
1435 iommus = <&apps_smmu 0x440 0x0>,
1436 <&apps_smmu 0x442 0x0>;
1437 reg = <0 0x1e40000 0 0x7000>,
1438 <0 0x1e47000 0 0x2000>,
1439 <0 0x1e04000 0 0x2c000>;
1440 reg-names = "ipa-reg",
1444 interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1445 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1446 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1447 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1448 interrupt-names = "ipa",
1453 clocks = <&rpmhcc RPMH_IPA_CLK>;
1454 clock-names = "core";
1456 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1457 <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1458 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1459 interconnect-names = "memory",
1463 qcom,smem-states = <&ipa_smp2p_out 0>,
1465 qcom,smem-state-names = "ipa-clock-enabled-valid",
1466 "ipa-clock-enabled";
1468 status = "disabled";
1471 tcsr_mutex_regs: syscon@1f40000 {
1472 compatible = "syscon";
1473 reg = <0 0x01f40000 0 0x40000>;
1476 tcsr_regs: syscon@1fc0000 {
1477 compatible = "syscon";
1478 reg = <0 0x01fc0000 0 0x40000>;
1481 tlmm: pinctrl@3500000 {
1482 compatible = "qcom,sc7180-pinctrl";
1483 reg = <0 0x03500000 0 0x300000>,
1484 <0 0x03900000 0 0x300000>,
1485 <0 0x03d00000 0 0x300000>;
1486 reg-names = "west", "north", "south";
1487 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1490 interrupt-controller;
1491 #interrupt-cells = <2>;
1492 gpio-ranges = <&tlmm 0 0 120>;
1493 wakeup-parent = <&pdc>;
1495 dp_hot_plug_det: dp-hot-plug-det {
1498 function = "dp_hot";
1502 qspi_clk: qspi-clk {
1505 function = "qspi_clk";
1509 qspi_cs0: qspi-cs0 {
1512 function = "qspi_cs";
1516 qspi_cs1: qspi-cs1 {
1519 function = "qspi_cs";
1523 qspi_data01: qspi-data01 {
1525 pins = "gpio64", "gpio65";
1526 function = "qspi_data";
1530 qspi_data12: qspi-data12 {
1532 pins = "gpio66", "gpio67";
1533 function = "qspi_data";
1537 qup_i2c0_default: qup-i2c0-default {
1539 pins = "gpio34", "gpio35";
1544 qup_i2c1_default: qup-i2c1-default {
1546 pins = "gpio0", "gpio1";
1551 qup_i2c2_default: qup-i2c2-default {
1553 pins = "gpio15", "gpio16";
1554 function = "qup02_i2c";
1558 qup_i2c3_default: qup-i2c3-default {
1560 pins = "gpio38", "gpio39";
1565 qup_i2c4_default: qup-i2c4-default {
1567 pins = "gpio115", "gpio116";
1568 function = "qup04_i2c";
1572 qup_i2c5_default: qup-i2c5-default {
1574 pins = "gpio25", "gpio26";
1579 qup_i2c6_default: qup-i2c6-default {
1581 pins = "gpio59", "gpio60";
1586 qup_i2c7_default: qup-i2c7-default {
1588 pins = "gpio6", "gpio7";
1589 function = "qup11_i2c";
1593 qup_i2c8_default: qup-i2c8-default {
1595 pins = "gpio42", "gpio43";
1600 qup_i2c9_default: qup-i2c9-default {
1602 pins = "gpio46", "gpio47";
1603 function = "qup13_i2c";
1607 qup_i2c10_default: qup-i2c10-default {
1609 pins = "gpio86", "gpio87";
1614 qup_i2c11_default: qup-i2c11-default {
1616 pins = "gpio53", "gpio54";
1621 qup_spi0_default: qup-spi0-default {
1623 pins = "gpio34", "gpio35",
1629 qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1631 pins = "gpio34", "gpio35",
1642 qup_spi1_default: qup-spi1-default {
1644 pins = "gpio0", "gpio1",
1650 qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1652 pins = "gpio0", "gpio1",
1663 qup_spi3_default: qup-spi3-default {
1665 pins = "gpio38", "gpio39",
1671 qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1673 pins = "gpio38", "gpio39",
1684 qup_spi5_default: qup-spi5-default {
1686 pins = "gpio25", "gpio26",
1692 qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1694 pins = "gpio25", "gpio26",
1705 qup_spi6_default: qup-spi6-default {
1707 pins = "gpio59", "gpio60",
1713 qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1715 pins = "gpio59", "gpio60",
1726 qup_spi8_default: qup-spi8-default {
1728 pins = "gpio42", "gpio43",
1734 qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1736 pins = "gpio42", "gpio43",
1747 qup_spi10_default: qup-spi10-default {
1749 pins = "gpio86", "gpio87",
1755 qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1757 pins = "gpio86", "gpio87",
1768 qup_spi11_default: qup-spi11-default {
1770 pins = "gpio53", "gpio54",
1776 qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1778 pins = "gpio53", "gpio54",
1789 qup_uart0_default: qup-uart0-default {
1791 pins = "gpio34", "gpio35",
1797 qup_uart1_default: qup-uart1-default {
1799 pins = "gpio0", "gpio1",
1805 qup_uart2_default: qup-uart2-default {
1807 pins = "gpio15", "gpio16";
1808 function = "qup02_uart";
1812 qup_uart3_default: qup-uart3-default {
1814 pins = "gpio38", "gpio39",
1820 qup_uart4_default: qup-uart4-default {
1822 pins = "gpio115", "gpio116";
1823 function = "qup04_uart";
1827 qup_uart5_default: qup-uart5-default {
1829 pins = "gpio25", "gpio26",
1835 qup_uart6_default: qup-uart6-default {
1837 pins = "gpio59", "gpio60",
1843 qup_uart7_default: qup-uart7-default {
1845 pins = "gpio6", "gpio7";
1846 function = "qup11_uart";
1850 qup_uart8_default: qup-uart8-default {
1852 pins = "gpio44", "gpio45";
1857 qup_uart9_default: qup-uart9-default {
1859 pins = "gpio46", "gpio47";
1860 function = "qup13_uart";
1864 qup_uart10_default: qup-uart10-default {
1866 pins = "gpio86", "gpio87",
1872 qup_uart11_default: qup-uart11-default {
1874 pins = "gpio53", "gpio54",
1880 sec_mi2s_active: sec-mi2s-active {
1882 pins = "gpio49", "gpio50", "gpio51";
1883 function = "mi2s_1";
1887 pri_mi2s_active: pri-mi2s-active {
1889 pins = "gpio53", "gpio54", "gpio55", "gpio56";
1890 function = "mi2s_0";
1894 pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1897 function = "lpass_ext";
1902 remoteproc_mpss: remoteproc@4080000 {
1903 compatible = "qcom,sc7180-mpss-pas";
1904 reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1905 reg-names = "qdsp6", "rmb";
1907 interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1908 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1909 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1910 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1911 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1912 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1913 interrupt-names = "wdog", "fatal", "ready", "handover",
1914 "stop-ack", "shutdown-ack";
1916 clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1917 <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1918 <&gcc GCC_MSS_NAV_AXI_CLK>,
1919 <&gcc GCC_MSS_SNOC_AXI_CLK>,
1920 <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1921 <&rpmhcc RPMH_CXO_CLK>;
1922 clock-names = "iface", "bus", "nav", "snoc_axi",
1925 power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1926 <&rpmhpd SC7180_CX>,
1927 <&rpmhpd SC7180_MX>,
1928 <&rpmhpd SC7180_MSS>;
1929 power-domain-names = "load_state", "cx", "mx", "mss";
1931 memory-region = <&mpss_mem>;
1933 qcom,smem-states = <&modem_smp2p_out 0>;
1934 qcom,smem-state-names = "stop";
1936 resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1937 <&pdc_reset PDC_MODEM_SYNC_RESET>;
1938 reset-names = "mss_restart", "pdc_reset";
1940 qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1941 qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1943 status = "disabled";
1946 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
1948 qcom,remote-pid = <1>;
1949 mboxes = <&apss_shared 12>;
1954 compatible = "qcom,adreno-618.0", "qcom,adreno";
1955 #stream-id-cells = <16>;
1956 reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
1957 <0 0x05061000 0 0x800>;
1958 reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
1959 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
1960 iommus = <&adreno_smmu 0>;
1961 operating-points-v2 = <&gpu_opp_table>;
1964 #cooling-cells = <2>;
1966 nvmem-cells = <&gpu_speed_bin>;
1967 nvmem-cell-names = "speed_bin";
1969 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
1970 interconnect-names = "gfx-mem";
1972 gpu_opp_table: opp-table {
1973 compatible = "operating-points-v2";
1976 opp-hz = /bits/ 64 <825000000>;
1977 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
1978 opp-peak-kBps = <8532000>;
1979 opp-supported-hw = <0x04>;
1983 opp-hz = /bits/ 64 <800000000>;
1984 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
1985 opp-peak-kBps = <8532000>;
1986 opp-supported-hw = <0x07>;
1990 opp-hz = /bits/ 64 <650000000>;
1991 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
1992 opp-peak-kBps = <7216000>;
1993 opp-supported-hw = <0x07>;
1997 opp-hz = /bits/ 64 <565000000>;
1998 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
1999 opp-peak-kBps = <5412000>;
2000 opp-supported-hw = <0x07>;
2004 opp-hz = /bits/ 64 <430000000>;
2005 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2006 opp-peak-kBps = <5412000>;
2007 opp-supported-hw = <0x07>;
2011 opp-hz = /bits/ 64 <355000000>;
2012 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2013 opp-peak-kBps = <3072000>;
2014 opp-supported-hw = <0x07>;
2018 opp-hz = /bits/ 64 <267000000>;
2019 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2020 opp-peak-kBps = <3072000>;
2021 opp-supported-hw = <0x07>;
2025 opp-hz = /bits/ 64 <180000000>;
2026 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2027 opp-peak-kBps = <1804000>;
2028 opp-supported-hw = <0x07>;
2033 adreno_smmu: iommu@5040000 {
2034 compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2035 reg = <0 0x05040000 0 0x10000>;
2037 #global-interrupts = <2>;
2038 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2039 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2040 <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2041 <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2042 <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2043 <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2044 <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2045 <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2046 <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2047 <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2049 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2050 <&gcc GCC_GPU_CFG_AHB_CLK>;
2051 clock-names = "bus", "iface";
2053 power-domains = <&gpucc CX_GDSC>;
2057 compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2058 reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2059 <0 0x0b490000 0 0x10000>;
2060 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2061 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2062 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2063 interrupt-names = "hfi", "gmu";
2064 clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2065 <&gpucc GPU_CC_CXO_CLK>,
2066 <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2067 <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2068 clock-names = "gmu", "cxo", "axi", "memnoc";
2069 power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2070 power-domain-names = "cx", "gx";
2071 iommus = <&adreno_smmu 5>;
2072 operating-points-v2 = <&gmu_opp_table>;
2074 gmu_opp_table: opp-table {
2075 compatible = "operating-points-v2";
2078 opp-hz = /bits/ 64 <200000000>;
2079 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2084 gpucc: clock-controller@5090000 {
2085 compatible = "qcom,sc7180-gpucc";
2086 reg = <0 0x05090000 0 0x9000>;
2087 clocks = <&rpmhcc RPMH_CXO_CLK>,
2088 <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2089 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2090 clock-names = "bi_tcxo",
2091 "gcc_gpu_gpll0_clk_src",
2092 "gcc_gpu_gpll0_div_clk_src";
2095 #power-domain-cells = <1>;
2099 compatible = "arm,coresight-stm", "arm,primecell";
2100 reg = <0 0x06002000 0 0x1000>,
2101 <0 0x16280000 0 0x180000>;
2102 reg-names = "stm-base", "stm-stimulus-base";
2104 clocks = <&aoss_qmp>;
2105 clock-names = "apb_pclk";
2110 remote-endpoint = <&funnel0_in7>;
2117 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2118 reg = <0 0x06041000 0 0x1000>;
2120 clocks = <&aoss_qmp>;
2121 clock-names = "apb_pclk";
2125 funnel0_out: endpoint {
2126 remote-endpoint = <&merge_funnel_in0>;
2132 #address-cells = <1>;
2137 funnel0_in7: endpoint {
2138 remote-endpoint = <&stm_out>;
2145 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2146 reg = <0 0x06042000 0 0x1000>;
2148 clocks = <&aoss_qmp>;
2149 clock-names = "apb_pclk";
2153 funnel1_out: endpoint {
2154 remote-endpoint = <&merge_funnel_in1>;
2160 #address-cells = <1>;
2165 funnel1_in4: endpoint {
2166 remote-endpoint = <&apss_merge_funnel_out>;
2173 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2174 reg = <0 0x06045000 0 0x1000>;
2176 clocks = <&aoss_qmp>;
2177 clock-names = "apb_pclk";
2181 merge_funnel_out: endpoint {
2182 remote-endpoint = <&swao_funnel_in>;
2188 #address-cells = <1>;
2193 merge_funnel_in0: endpoint {
2194 remote-endpoint = <&funnel0_out>;
2200 merge_funnel_in1: endpoint {
2201 remote-endpoint = <&funnel1_out>;
2207 replicator@6046000 {
2208 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2209 reg = <0 0x06046000 0 0x1000>;
2211 clocks = <&aoss_qmp>;
2212 clock-names = "apb_pclk";
2216 replicator_out: endpoint {
2217 remote-endpoint = <&etr_in>;
2224 replicator_in: endpoint {
2225 remote-endpoint = <&swao_replicator_out>;
2232 compatible = "arm,coresight-tmc", "arm,primecell";
2233 reg = <0 0x06048000 0 0x1000>;
2234 iommus = <&apps_smmu 0x04a0 0x20>;
2236 clocks = <&aoss_qmp>;
2237 clock-names = "apb_pclk";
2243 remote-endpoint = <&replicator_out>;
2250 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2251 reg = <0 0x06b04000 0 0x1000>;
2253 clocks = <&aoss_qmp>;
2254 clock-names = "apb_pclk";
2258 swao_funnel_out: endpoint {
2259 remote-endpoint = <&etf_in>;
2265 #address-cells = <1>;
2270 swao_funnel_in: endpoint {
2271 remote-endpoint = <&merge_funnel_out>;
2278 compatible = "arm,coresight-tmc", "arm,primecell";
2279 reg = <0 0x06b05000 0 0x1000>;
2281 clocks = <&aoss_qmp>;
2282 clock-names = "apb_pclk";
2287 remote-endpoint = <&swao_replicator_in>;
2295 remote-endpoint = <&swao_funnel_out>;
2301 replicator@6b06000 {
2302 compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2303 reg = <0 0x06b06000 0 0x1000>;
2305 clocks = <&aoss_qmp>;
2306 clock-names = "apb_pclk";
2307 qcom,replicator-loses-context;
2311 swao_replicator_out: endpoint {
2312 remote-endpoint = <&replicator_in>;
2319 swao_replicator_in: endpoint {
2320 remote-endpoint = <&etf_out>;
2327 compatible = "arm,coresight-etm4x", "arm,primecell";
2328 reg = <0 0x07040000 0 0x1000>;
2332 clocks = <&aoss_qmp>;
2333 clock-names = "apb_pclk";
2334 arm,coresight-loses-context-with-cpu;
2339 etm0_out: endpoint {
2340 remote-endpoint = <&apss_funnel_in0>;
2347 compatible = "arm,coresight-etm4x", "arm,primecell";
2348 reg = <0 0x07140000 0 0x1000>;
2352 clocks = <&aoss_qmp>;
2353 clock-names = "apb_pclk";
2354 arm,coresight-loses-context-with-cpu;
2359 etm1_out: endpoint {
2360 remote-endpoint = <&apss_funnel_in1>;
2367 compatible = "arm,coresight-etm4x", "arm,primecell";
2368 reg = <0 0x07240000 0 0x1000>;
2372 clocks = <&aoss_qmp>;
2373 clock-names = "apb_pclk";
2374 arm,coresight-loses-context-with-cpu;
2379 etm2_out: endpoint {
2380 remote-endpoint = <&apss_funnel_in2>;
2387 compatible = "arm,coresight-etm4x", "arm,primecell";
2388 reg = <0 0x07340000 0 0x1000>;
2392 clocks = <&aoss_qmp>;
2393 clock-names = "apb_pclk";
2394 arm,coresight-loses-context-with-cpu;
2399 etm3_out: endpoint {
2400 remote-endpoint = <&apss_funnel_in3>;
2407 compatible = "arm,coresight-etm4x", "arm,primecell";
2408 reg = <0 0x07440000 0 0x1000>;
2412 clocks = <&aoss_qmp>;
2413 clock-names = "apb_pclk";
2414 arm,coresight-loses-context-with-cpu;
2419 etm4_out: endpoint {
2420 remote-endpoint = <&apss_funnel_in4>;
2427 compatible = "arm,coresight-etm4x", "arm,primecell";
2428 reg = <0 0x07540000 0 0x1000>;
2432 clocks = <&aoss_qmp>;
2433 clock-names = "apb_pclk";
2434 arm,coresight-loses-context-with-cpu;
2439 etm5_out: endpoint {
2440 remote-endpoint = <&apss_funnel_in5>;
2447 compatible = "arm,coresight-etm4x", "arm,primecell";
2448 reg = <0 0x07640000 0 0x1000>;
2452 clocks = <&aoss_qmp>;
2453 clock-names = "apb_pclk";
2454 arm,coresight-loses-context-with-cpu;
2459 etm6_out: endpoint {
2460 remote-endpoint = <&apss_funnel_in6>;
2467 compatible = "arm,coresight-etm4x", "arm,primecell";
2468 reg = <0 0x07740000 0 0x1000>;
2472 clocks = <&aoss_qmp>;
2473 clock-names = "apb_pclk";
2474 arm,coresight-loses-context-with-cpu;
2479 etm7_out: endpoint {
2480 remote-endpoint = <&apss_funnel_in7>;
2486 funnel@7800000 { /* APSS Funnel */
2487 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2488 reg = <0 0x07800000 0 0x1000>;
2490 clocks = <&aoss_qmp>;
2491 clock-names = "apb_pclk";
2495 apss_funnel_out: endpoint {
2496 remote-endpoint = <&apss_merge_funnel_in>;
2502 #address-cells = <1>;
2507 apss_funnel_in0: endpoint {
2508 remote-endpoint = <&etm0_out>;
2514 apss_funnel_in1: endpoint {
2515 remote-endpoint = <&etm1_out>;
2521 apss_funnel_in2: endpoint {
2522 remote-endpoint = <&etm2_out>;
2528 apss_funnel_in3: endpoint {
2529 remote-endpoint = <&etm3_out>;
2535 apss_funnel_in4: endpoint {
2536 remote-endpoint = <&etm4_out>;
2542 apss_funnel_in5: endpoint {
2543 remote-endpoint = <&etm5_out>;
2549 apss_funnel_in6: endpoint {
2550 remote-endpoint = <&etm6_out>;
2556 apss_funnel_in7: endpoint {
2557 remote-endpoint = <&etm7_out>;
2564 compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2565 reg = <0 0x07810000 0 0x1000>;
2567 clocks = <&aoss_qmp>;
2568 clock-names = "apb_pclk";
2572 apss_merge_funnel_out: endpoint {
2573 remote-endpoint = <&funnel1_in4>;
2580 apss_merge_funnel_in: endpoint {
2581 remote-endpoint = <&apss_funnel_out>;
2587 sdhc_2: sdhci@8804000 {
2588 compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2589 reg = <0 0x08804000 0 0x1000>;
2591 iommus = <&apps_smmu 0x80 0>;
2592 interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2593 <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2594 interrupt-names = "hc_irq", "pwr_irq";
2596 clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2597 <&gcc GCC_SDCC2_AHB_CLK>,
2598 <&rpmhcc RPMH_CXO_CLK>;
2599 clock-names = "core", "iface", "xo";
2601 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2602 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2603 interconnect-names = "sdhc-ddr","cpu-sdhc";
2604 power-domains = <&rpmhpd SC7180_CX>;
2605 operating-points-v2 = <&sdhc2_opp_table>;
2609 status = "disabled";
2611 sdhc2_opp_table: sdhc2-opp-table {
2612 compatible = "operating-points-v2";
2615 opp-hz = /bits/ 64 <100000000>;
2616 required-opps = <&rpmhpd_opp_low_svs>;
2617 opp-peak-kBps = <1800000 600000>;
2618 opp-avg-kBps = <100000 0>;
2622 opp-hz = /bits/ 64 <202000000>;
2623 required-opps = <&rpmhpd_opp_nom>;
2624 opp-peak-kBps = <5400000 1600000>;
2625 opp-avg-kBps = <200000 0>;
2630 qspi_opp_table: qspi-opp-table {
2631 compatible = "operating-points-v2";
2634 opp-hz = /bits/ 64 <75000000>;
2635 required-opps = <&rpmhpd_opp_low_svs>;
2639 opp-hz = /bits/ 64 <150000000>;
2640 required-opps = <&rpmhpd_opp_svs>;
2644 opp-hz = /bits/ 64 <300000000>;
2645 required-opps = <&rpmhpd_opp_nom>;
2650 compatible = "qcom,qspi-v1";
2651 reg = <0 0x088dc000 0 0x600>;
2652 #address-cells = <1>;
2654 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2655 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2656 <&gcc GCC_QSPI_CORE_CLK>;
2657 clock-names = "iface", "core";
2658 interconnects = <&gem_noc MASTER_APPSS_PROC 0
2659 &config_noc SLAVE_QSPI_0 0>;
2660 interconnect-names = "qspi-config";
2661 power-domains = <&rpmhpd SC7180_CX>;
2662 operating-points-v2 = <&qspi_opp_table>;
2663 status = "disabled";
2666 usb_1_hsphy: phy@88e3000 {
2667 compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2668 reg = <0 0x088e3000 0 0x400>;
2669 status = "disabled";
2671 clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2672 <&rpmhcc RPMH_CXO_CLK>;
2673 clock-names = "cfg_ahb", "ref";
2674 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2676 nvmem-cells = <&qusb2p_hstx_trim>;
2679 usb_1_qmpphy: phy-wrapper@88e9000 {
2680 compatible = "qcom,sc7180-qmp-usb3-dp-phy";
2681 reg = <0 0x088e9000 0 0x18c>,
2682 <0 0x088e8000 0 0x3c>,
2683 <0 0x088ea000 0 0x18c>;
2684 status = "disabled";
2685 #address-cells = <2>;
2689 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2690 <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2691 <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2692 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2693 clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2695 resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2696 <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2697 reset-names = "phy", "common";
2699 usb_1_ssphy: usb3-phy@88e9200 {
2700 reg = <0 0x088e9200 0 0x128>,
2701 <0 0x088e9400 0 0x200>,
2702 <0 0x088e9c00 0 0x218>,
2703 <0 0x088e9600 0 0x128>,
2704 <0 0x088e9800 0 0x200>,
2705 <0 0x088e9a00 0 0x18>;
2708 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2709 clock-names = "pipe0";
2710 clock-output-names = "usb3_phy_pipe_clk_src";
2713 dp_phy: dp-phy@88ea200 {
2714 reg = <0 0x088ea200 0 0x200>,
2715 <0 0x088ea400 0 0x200>,
2716 <0 0x088eaa00 0 0x200>,
2717 <0 0x088ea600 0 0x200>,
2718 <0 0x088ea800 0 0x200>;
2724 dc_noc: interconnect@9160000 {
2725 compatible = "qcom,sc7180-dc-noc";
2726 reg = <0 0x09160000 0 0x03200>;
2727 #interconnect-cells = <2>;
2728 qcom,bcm-voters = <&apps_bcm_voter>;
2731 system-cache-controller@9200000 {
2732 compatible = "qcom,sc7180-llcc";
2733 reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2734 reg-names = "llcc_base", "llcc_broadcast_base";
2735 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2738 gem_noc: interconnect@9680000 {
2739 compatible = "qcom,sc7180-gem-noc";
2740 reg = <0 0x09680000 0 0x3e200>;
2741 #interconnect-cells = <2>;
2742 qcom,bcm-voters = <&apps_bcm_voter>;
2745 npu_noc: interconnect@9990000 {
2746 compatible = "qcom,sc7180-npu-noc";
2747 reg = <0 0x09990000 0 0x1600>;
2748 #interconnect-cells = <2>;
2749 qcom,bcm-voters = <&apps_bcm_voter>;
2752 usb_1: usb@a6f8800 {
2753 compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2754 reg = <0 0x0a6f8800 0 0x400>;
2755 status = "disabled";
2756 #address-cells = <2>;
2761 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2762 <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2763 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2764 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2765 <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2766 clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2769 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2770 <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2771 assigned-clock-rates = <19200000>, <150000000>;
2773 interrupts-extended = <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2774 <&pdc 6 IRQ_TYPE_LEVEL_HIGH>,
2775 <&pdc 8 IRQ_TYPE_LEVEL_HIGH>,
2776 <&pdc 9 IRQ_TYPE_LEVEL_HIGH>;
2777 interrupt-names = "hs_phy_irq", "ss_phy_irq",
2778 "dm_hs_phy_irq", "dp_hs_phy_irq";
2780 power-domains = <&gcc USB30_PRIM_GDSC>;
2782 resets = <&gcc GCC_USB30_PRIM_BCR>;
2784 interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2785 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2786 interconnect-names = "usb-ddr", "apps-usb";
2788 usb_1_dwc3: dwc3@a600000 {
2789 compatible = "snps,dwc3";
2790 reg = <0 0x0a600000 0 0xe000>;
2791 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2792 iommus = <&apps_smmu 0x540 0>;
2793 snps,dis_u2_susphy_quirk;
2794 snps,dis_enblslpm_quirk;
2795 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2796 phy-names = "usb2-phy", "usb3-phy";
2797 maximum-speed = "super-speed";
2801 venus: video-codec@aa00000 {
2802 compatible = "qcom,sc7180-venus";
2803 reg = <0 0x0aa00000 0 0xff000>;
2804 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2805 power-domains = <&videocc VENUS_GDSC>,
2806 <&videocc VCODEC0_GDSC>,
2807 <&rpmhpd SC7180_CX>;
2808 power-domain-names = "venus", "vcodec0", "cx";
2809 operating-points-v2 = <&venus_opp_table>;
2810 clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2811 <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2812 <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2813 <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2814 <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2815 clock-names = "core", "iface", "bus",
2816 "vcodec0_core", "vcodec0_bus";
2817 iommus = <&apps_smmu 0x0c00 0x60>;
2818 memory-region = <&venus_mem>;
2819 interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2820 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2821 interconnect-names = "video-mem", "cpu-cfg";
2824 compatible = "venus-decoder";
2828 compatible = "venus-encoder";
2831 venus_opp_table: venus-opp-table {
2832 compatible = "operating-points-v2";
2835 opp-hz = /bits/ 64 <150000000>;
2836 required-opps = <&rpmhpd_opp_low_svs>;
2840 opp-hz = /bits/ 64 <270000000>;
2841 required-opps = <&rpmhpd_opp_svs>;
2845 opp-hz = /bits/ 64 <340000000>;
2846 required-opps = <&rpmhpd_opp_svs_l1>;
2850 opp-hz = /bits/ 64 <434000000>;
2851 required-opps = <&rpmhpd_opp_nom>;
2855 opp-hz = /bits/ 64 <500000097>;
2856 required-opps = <&rpmhpd_opp_turbo>;
2861 videocc: clock-controller@ab00000 {
2862 compatible = "qcom,sc7180-videocc";
2863 reg = <0 0x0ab00000 0 0x10000>;
2864 clocks = <&rpmhcc RPMH_CXO_CLK>;
2865 clock-names = "bi_tcxo";
2868 #power-domain-cells = <1>;
2871 camnoc_virt: interconnect@ac00000 {
2872 compatible = "qcom,sc7180-camnoc-virt";
2873 reg = <0 0x0ac00000 0 0x1000>;
2874 #interconnect-cells = <2>;
2875 qcom,bcm-voters = <&apps_bcm_voter>;
2878 camcc: clock-controller@ad00000 {
2879 compatible = "qcom,sc7180-camcc";
2880 reg = <0 0x0ad00000 0 0x10000>;
2881 clocks = <&rpmhcc RPMH_CXO_CLK>,
2882 <&gcc GCC_CAMERA_AHB_CLK>,
2883 <&gcc GCC_CAMERA_XO_CLK>;
2884 clock-names = "bi_tcxo", "iface", "xo";
2887 #power-domain-cells = <1>;
2890 mdss: mdss@ae00000 {
2891 compatible = "qcom,sc7180-mdss";
2892 reg = <0 0x0ae00000 0 0x1000>;
2895 power-domains = <&dispcc MDSS_GDSC>;
2897 clocks = <&gcc GCC_DISP_AHB_CLK>,
2898 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2899 <&dispcc DISP_CC_MDSS_MDP_CLK>;
2900 clock-names = "iface", "ahb", "core";
2902 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2903 assigned-clock-rates = <300000000>;
2905 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2906 interrupt-controller;
2907 #interrupt-cells = <1>;
2909 interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2910 interconnect-names = "mdp0-mem";
2912 iommus = <&apps_smmu 0x800 0x2>;
2914 #address-cells = <2>;
2918 status = "disabled";
2921 compatible = "qcom,sc7180-dpu";
2922 reg = <0 0x0ae01000 0 0x8f000>,
2923 <0 0x0aeb0000 0 0x2008>;
2924 reg-names = "mdp", "vbif";
2926 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2927 <&dispcc DISP_CC_MDSS_AHB_CLK>,
2928 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2929 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2930 <&dispcc DISP_CC_MDSS_MDP_CLK>,
2931 <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2932 clock-names = "bus", "iface", "rot", "lut", "core",
2934 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2935 <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2936 <&dispcc DISP_CC_MDSS_ROT_CLK>,
2937 <&dispcc DISP_CC_MDSS_AHB_CLK>;
2938 assigned-clock-rates = <300000000>,
2942 operating-points-v2 = <&mdp_opp_table>;
2943 power-domains = <&rpmhpd SC7180_CX>;
2945 interrupt-parent = <&mdss>;
2948 status = "disabled";
2951 #address-cells = <1>;
2956 dpu_intf1_out: endpoint {
2957 remote-endpoint = <&dsi0_in>;
2963 dpu_intf0_out: endpoint {
2964 remote-endpoint = <&dp_in>;
2969 mdp_opp_table: mdp-opp-table {
2970 compatible = "operating-points-v2";
2973 opp-hz = /bits/ 64 <200000000>;
2974 required-opps = <&rpmhpd_opp_low_svs>;
2978 opp-hz = /bits/ 64 <300000000>;
2979 required-opps = <&rpmhpd_opp_svs>;
2983 opp-hz = /bits/ 64 <345000000>;
2984 required-opps = <&rpmhpd_opp_svs_l1>;
2988 opp-hz = /bits/ 64 <460000000>;
2989 required-opps = <&rpmhpd_opp_nom>;
2996 compatible = "qcom,mdss-dsi-ctrl";
2997 reg = <0 0x0ae94000 0 0x400>;
2998 reg-names = "dsi_ctrl";
3000 interrupt-parent = <&mdss>;
3003 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3004 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3005 <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3006 <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3007 <&dispcc DISP_CC_MDSS_AHB_CLK>,
3008 <&gcc GCC_DISP_HF_AXI_CLK>;
3009 clock-names = "byte",
3016 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
3017 assigned-clock-parents = <&dsi_phy 0>, <&dsi_phy 1>;
3019 operating-points-v2 = <&dsi_opp_table>;
3020 power-domains = <&rpmhpd SC7180_CX>;
3025 #address-cells = <1>;
3028 status = "disabled";
3031 #address-cells = <1>;
3037 remote-endpoint = <&dpu_intf1_out>;
3043 dsi0_out: endpoint {
3048 dsi_opp_table: dsi-opp-table {
3049 compatible = "operating-points-v2";
3052 opp-hz = /bits/ 64 <187500000>;
3053 required-opps = <&rpmhpd_opp_low_svs>;
3057 opp-hz = /bits/ 64 <300000000>;
3058 required-opps = <&rpmhpd_opp_svs>;
3062 opp-hz = /bits/ 64 <358000000>;
3063 required-opps = <&rpmhpd_opp_svs_l1>;
3068 dsi_phy: dsi-phy@ae94400 {
3069 compatible = "qcom,dsi-phy-10nm";
3070 reg = <0 0x0ae94400 0 0x200>,
3071 <0 0x0ae94600 0 0x280>,
3072 <0 0x0ae94a00 0 0x1e0>;
3073 reg-names = "dsi_phy",
3080 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3081 <&rpmhcc RPMH_CXO_CLK>;
3082 clock-names = "iface", "ref";
3084 status = "disabled";
3087 mdss_dp: displayport-controller@ae90000 {
3088 compatible = "qcom,sc7180-dp";
3089 status = "disabled";
3091 reg = <0 0x0ae90000 0 0x1400>;
3093 interrupt-parent = <&mdss>;
3096 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3097 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>,
3098 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>,
3099 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>,
3100 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>;
3101 clock-names = "core_iface", "core_aux", "ctrl_link",
3102 "ctrl_link_iface", "stream_pixel";
3104 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>,
3105 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>;
3106 assigned-clock-parents = <&dp_phy 0>, <&dp_phy 1>;
3110 operating-points-v2 = <&dp_opp_table>;
3111 power-domains = <&rpmhpd SC7180_CX>;
3113 #sound-dai-cells = <0>;
3116 #address-cells = <1>;
3121 remote-endpoint = <&dpu_intf0_out>;
3127 dp_out: endpoint { };
3131 dp_opp_table: opp-table {
3132 compatible = "operating-points-v2";
3135 opp-hz = /bits/ 64 <160000000>;
3136 required-opps = <&rpmhpd_opp_low_svs>;
3140 opp-hz = /bits/ 64 <270000000>;
3141 required-opps = <&rpmhpd_opp_svs>;
3145 opp-hz = /bits/ 64 <540000000>;
3146 required-opps = <&rpmhpd_opp_svs_l1>;
3150 opp-hz = /bits/ 64 <810000000>;
3151 required-opps = <&rpmhpd_opp_nom>;
3157 dispcc: clock-controller@af00000 {
3158 compatible = "qcom,sc7180-dispcc";
3159 reg = <0 0x0af00000 0 0x200000>;
3160 clocks = <&rpmhcc RPMH_CXO_CLK>,
3161 <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3166 clock-names = "bi_tcxo",
3167 "gcc_disp_gpll0_clk_src",
3168 "dsi0_phy_pll_out_byteclk",
3169 "dsi0_phy_pll_out_dsiclk",
3170 "dp_phy_pll_link_clk",
3171 "dp_phy_pll_vco_div_clk";
3174 #power-domain-cells = <1>;
3177 pdc: interrupt-controller@b220000 {
3178 compatible = "qcom,sc7180-pdc", "qcom,pdc";
3179 reg = <0 0x0b220000 0 0x30000>;
3180 qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3181 #interrupt-cells = <2>;
3182 interrupt-parent = <&intc>;
3183 interrupt-controller;
3186 pdc_reset: reset-controller@b2e0000 {
3187 compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3188 reg = <0 0x0b2e0000 0 0x20000>;
3192 tsens0: thermal-sensor@c263000 {
3193 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3194 reg = <0 0x0c263000 0 0x1ff>, /* TM */
3195 <0 0x0c222000 0 0x1ff>; /* SROT */
3196 #qcom,sensors = <15>;
3197 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3198 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3199 interrupt-names = "uplow","critical";
3200 #thermal-sensor-cells = <1>;
3203 tsens1: thermal-sensor@c265000 {
3204 compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3205 reg = <0 0x0c265000 0 0x1ff>, /* TM */
3206 <0 0x0c223000 0 0x1ff>; /* SROT */
3207 #qcom,sensors = <10>;
3208 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3209 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3210 interrupt-names = "uplow","critical";
3211 #thermal-sensor-cells = <1>;
3214 aoss_reset: reset-controller@c2a0000 {
3215 compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3216 reg = <0 0x0c2a0000 0 0x31000>;
3220 aoss_qmp: power-controller@c300000 {
3221 compatible = "qcom,sc7180-aoss-qmp";
3222 reg = <0 0x0c300000 0 0x100000>;
3223 interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3224 mboxes = <&apss_shared 0>;
3227 #power-domain-cells = <1>;
3230 spmi_bus: spmi@c440000 {
3231 compatible = "qcom,spmi-pmic-arb";
3232 reg = <0 0x0c440000 0 0x1100>,
3233 <0 0x0c600000 0 0x2000000>,
3234 <0 0x0e600000 0 0x100000>,
3235 <0 0x0e700000 0 0xa0000>,
3236 <0 0x0c40a000 0 0x26000>;
3237 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3238 interrupt-names = "periph_irq";
3239 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3242 #address-cells = <1>;
3244 interrupt-controller;
3245 #interrupt-cells = <4>;
3249 apps_smmu: iommu@15000000 {
3250 compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3251 reg = <0 0x15000000 0 0x100000>;
3253 #global-interrupts = <1>;
3254 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3255 <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3256 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3257 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3258 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3259 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3260 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3261 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3262 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3263 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3264 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3265 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3266 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3267 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3268 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3269 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3270 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3271 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3272 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3273 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3274 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3275 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3276 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3277 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3278 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3279 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3280 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3281 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3282 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3283 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3284 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3285 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3286 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3287 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3288 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3289 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3290 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3291 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3292 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3293 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3294 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3295 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3296 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3297 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3298 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3299 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3300 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3301 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3302 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3303 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3304 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3305 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3306 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3307 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3308 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3309 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3310 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3311 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3312 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3313 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3314 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3315 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3316 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3317 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3318 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3319 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3320 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3321 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3322 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3323 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3324 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3325 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3326 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3327 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3328 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3329 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3330 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3331 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3332 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3333 <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3334 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3337 intc: interrupt-controller@17a00000 {
3338 compatible = "arm,gic-v3";
3339 #address-cells = <2>;
3342 #interrupt-cells = <3>;
3343 interrupt-controller;
3344 reg = <0 0x17a00000 0 0x10000>, /* GICD */
3345 <0 0x17a60000 0 0x100000>; /* GICR * 8 */
3346 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3348 msi-controller@17a40000 {
3349 compatible = "arm,gic-v3-its";
3352 reg = <0 0x17a40000 0 0x20000>;
3353 status = "disabled";
3357 apss_shared: mailbox@17c00000 {
3358 compatible = "qcom,sc7180-apss-shared";
3359 reg = <0 0x17c00000 0 0x10000>;
3364 compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3365 reg = <0 0x17c10000 0 0x1000>;
3366 clocks = <&sleep_clk>;
3367 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3371 #address-cells = <2>;
3374 compatible = "arm,armv7-timer-mem";
3375 reg = <0 0x17c20000 0 0x1000>;
3379 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3380 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3381 reg = <0 0x17c21000 0 0x1000>,
3382 <0 0x17c22000 0 0x1000>;
3387 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3388 reg = <0 0x17c23000 0 0x1000>;
3389 status = "disabled";
3394 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3395 reg = <0 0x17c25000 0 0x1000>;
3396 status = "disabled";
3401 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3402 reg = <0 0x17c27000 0 0x1000>;
3403 status = "disabled";
3408 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3409 reg = <0 0x17c29000 0 0x1000>;
3410 status = "disabled";
3415 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3416 reg = <0 0x17c2b000 0 0x1000>;
3417 status = "disabled";
3422 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3423 reg = <0 0x17c2d000 0 0x1000>;
3424 status = "disabled";
3428 apps_rsc: rsc@18200000 {
3429 compatible = "qcom,rpmh-rsc";
3430 reg = <0 0x18200000 0 0x10000>,
3431 <0 0x18210000 0 0x10000>,
3432 <0 0x18220000 0 0x10000>;
3433 reg-names = "drv-0", "drv-1", "drv-2";
3434 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3435 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3436 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3437 qcom,tcs-offset = <0xd00>;
3439 qcom,tcs-config = <ACTIVE_TCS 2>,
3444 rpmhcc: clock-controller {
3445 compatible = "qcom,sc7180-rpmh-clk";
3446 clocks = <&xo_board>;
3451 rpmhpd: power-controller {
3452 compatible = "qcom,sc7180-rpmhpd";
3453 #power-domain-cells = <1>;
3454 operating-points-v2 = <&rpmhpd_opp_table>;
3456 rpmhpd_opp_table: opp-table {
3457 compatible = "operating-points-v2";
3459 rpmhpd_opp_ret: opp1 {
3460 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3463 rpmhpd_opp_min_svs: opp2 {
3464 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3467 rpmhpd_opp_low_svs: opp3 {
3468 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3471 rpmhpd_opp_svs: opp4 {
3472 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3475 rpmhpd_opp_svs_l1: opp5 {
3476 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3479 rpmhpd_opp_svs_l2: opp6 {
3483 rpmhpd_opp_nom: opp7 {
3484 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3487 rpmhpd_opp_nom_l1: opp8 {
3488 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3491 rpmhpd_opp_nom_l2: opp9 {
3492 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3495 rpmhpd_opp_turbo: opp10 {
3496 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3499 rpmhpd_opp_turbo_l1: opp11 {
3500 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3505 apps_bcm_voter: bcm_voter {
3506 compatible = "qcom,bcm-voter";
3510 osm_l3: interconnect@18321000 {
3511 compatible = "qcom,sc7180-osm-l3";
3512 reg = <0 0x18321000 0 0x1400>;
3514 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3515 clock-names = "xo", "alternate";
3517 #interconnect-cells = <1>;
3520 cpufreq_hw: cpufreq@18323000 {
3521 compatible = "qcom,cpufreq-hw";
3522 reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3523 reg-names = "freq-domain0", "freq-domain1";
3525 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3526 clock-names = "xo", "alternate";
3528 #freq-domain-cells = <1>;
3531 wifi: wifi@18800000 {
3532 compatible = "qcom,wcn3990-wifi";
3533 reg = <0 0x18800000 0 0x800000>;
3534 reg-names = "membase";
3535 iommus = <&apps_smmu 0xc0 0x1>;
3537 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3538 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3539 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3540 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3541 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3542 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3543 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3544 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3545 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3546 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3547 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3548 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3549 memory-region = <&wlan_mem>;
3550 qcom,msa-fixed-perm;
3551 status = "disabled";
3554 lpasscc: clock-controller@62d00000 {
3555 compatible = "qcom,sc7180-lpasscorecc";
3556 reg = <0 0x62d00000 0 0x50000>,
3557 <0 0x62780000 0 0x30000>;
3558 reg-names = "lpass_core_cc", "lpass_audio_cc";
3559 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3560 <&rpmhcc RPMH_CXO_CLK>;
3561 clock-names = "iface", "bi_tcxo";
3562 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3564 #power-domain-cells = <1>;
3567 lpass_cpu: lpass@62d87000 {
3568 compatible = "qcom,sc7180-lpass-cpu";
3570 reg = <0 0x62d87000 0 0x68000>, <0 0x62f00000 0 0x29000>;
3571 reg-names = "lpass-hdmiif", "lpass-lpaif";
3573 iommus = <&apps_smmu 0x1020 0>,
3574 <&apps_smmu 0x1021 0>,
3575 <&apps_smmu 0x1032 0>;
3577 power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3579 status = "disabled";
3581 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3582 <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3583 <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3584 <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3585 <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3586 <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3588 clock-names = "pcnoc-sway-clk", "audio-core",
3589 "mclk0", "pcnoc-mport-clk",
3590 "mi2s-bit-clk0", "mi2s-bit-clk1";
3593 #sound-dai-cells = <1>;
3594 #address-cells = <1>;
3597 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
3598 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
3599 interrupt-names = "lpass-irq-lpaif", "lpass-irq-hdmi";
3602 lpass_hm: clock-controller@63000000 {
3603 compatible = "qcom,sc7180-lpasshm";
3604 reg = <0 0x63000000 0 0x28>;
3605 clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3606 <&rpmhcc RPMH_CXO_CLK>;
3607 clock-names = "iface", "bi_tcxo";
3609 #power-domain-cells = <1>;
3614 cpu0_thermal: cpu0-thermal {
3615 polling-delay-passive = <250>;
3616 polling-delay = <0>;
3618 thermal-sensors = <&tsens0 1>;
3619 sustainable-power = <768>;
3622 cpu0_alert0: trip-point0 {
3623 temperature = <90000>;
3624 hysteresis = <2000>;
3628 cpu0_alert1: trip-point1 {
3629 temperature = <95000>;
3630 hysteresis = <2000>;
3634 cpu0_crit: cpu_crit {
3635 temperature = <110000>;
3636 hysteresis = <1000>;
3643 trip = <&cpu0_alert0>;
3644 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3645 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3646 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3647 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3648 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3649 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3652 trip = <&cpu0_alert1>;
3653 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3654 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3655 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3663 cpu1_thermal: cpu1-thermal {
3664 polling-delay-passive = <250>;
3665 polling-delay = <0>;
3667 thermal-sensors = <&tsens0 2>;
3668 sustainable-power = <768>;
3671 cpu1_alert0: trip-point0 {
3672 temperature = <90000>;
3673 hysteresis = <2000>;
3677 cpu1_alert1: trip-point1 {
3678 temperature = <95000>;
3679 hysteresis = <2000>;
3683 cpu1_crit: cpu_crit {
3684 temperature = <110000>;
3685 hysteresis = <1000>;
3692 trip = <&cpu1_alert0>;
3693 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3694 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3695 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3696 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3697 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3698 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3701 trip = <&cpu1_alert1>;
3702 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3703 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3704 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3705 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3706 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3707 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3712 cpu2_thermal: cpu2-thermal {
3713 polling-delay-passive = <250>;
3714 polling-delay = <0>;
3716 thermal-sensors = <&tsens0 3>;
3717 sustainable-power = <768>;
3720 cpu2_alert0: trip-point0 {
3721 temperature = <90000>;
3722 hysteresis = <2000>;
3726 cpu2_alert1: trip-point1 {
3727 temperature = <95000>;
3728 hysteresis = <2000>;
3732 cpu2_crit: cpu_crit {
3733 temperature = <110000>;
3734 hysteresis = <1000>;
3741 trip = <&cpu2_alert0>;
3742 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3743 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3744 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3745 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3746 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3747 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3750 trip = <&cpu2_alert1>;
3751 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3752 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3753 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3754 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3755 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3756 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3761 cpu3_thermal: cpu3-thermal {
3762 polling-delay-passive = <250>;
3763 polling-delay = <0>;
3765 thermal-sensors = <&tsens0 4>;
3766 sustainable-power = <768>;
3769 cpu3_alert0: trip-point0 {
3770 temperature = <90000>;
3771 hysteresis = <2000>;
3775 cpu3_alert1: trip-point1 {
3776 temperature = <95000>;
3777 hysteresis = <2000>;
3781 cpu3_crit: cpu_crit {
3782 temperature = <110000>;
3783 hysteresis = <1000>;
3790 trip = <&cpu3_alert0>;
3791 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3792 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3793 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3794 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3795 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3796 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3799 trip = <&cpu3_alert1>;
3800 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3801 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3802 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3803 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3804 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3805 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3810 cpu4_thermal: cpu4-thermal {
3811 polling-delay-passive = <250>;
3812 polling-delay = <0>;
3814 thermal-sensors = <&tsens0 5>;
3815 sustainable-power = <768>;
3818 cpu4_alert0: trip-point0 {
3819 temperature = <90000>;
3820 hysteresis = <2000>;
3824 cpu4_alert1: trip-point1 {
3825 temperature = <95000>;
3826 hysteresis = <2000>;
3830 cpu4_crit: cpu_crit {
3831 temperature = <110000>;
3832 hysteresis = <1000>;
3839 trip = <&cpu4_alert0>;
3840 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3841 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3842 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3843 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3844 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3845 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3848 trip = <&cpu4_alert1>;
3849 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3850 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3851 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3852 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3853 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3854 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3859 cpu5_thermal: cpu5-thermal {
3860 polling-delay-passive = <250>;
3861 polling-delay = <0>;
3863 thermal-sensors = <&tsens0 6>;
3864 sustainable-power = <768>;
3867 cpu5_alert0: trip-point0 {
3868 temperature = <90000>;
3869 hysteresis = <2000>;
3873 cpu5_alert1: trip-point1 {
3874 temperature = <95000>;
3875 hysteresis = <2000>;
3879 cpu5_crit: cpu_crit {
3880 temperature = <110000>;
3881 hysteresis = <1000>;
3888 trip = <&cpu5_alert0>;
3889 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3890 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3891 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3892 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3893 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3894 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3897 trip = <&cpu5_alert1>;
3898 cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3899 <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3900 <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3901 <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3902 <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3903 <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3908 cpu6_thermal: cpu6-thermal {
3909 polling-delay-passive = <250>;
3910 polling-delay = <0>;
3912 thermal-sensors = <&tsens0 9>;
3913 sustainable-power = <1202>;
3916 cpu6_alert0: trip-point0 {
3917 temperature = <90000>;
3918 hysteresis = <2000>;
3922 cpu6_alert1: trip-point1 {
3923 temperature = <95000>;
3924 hysteresis = <2000>;
3928 cpu6_crit: cpu_crit {
3929 temperature = <110000>;
3930 hysteresis = <1000>;
3937 trip = <&cpu6_alert0>;
3938 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3939 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3942 trip = <&cpu6_alert1>;
3943 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3944 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3949 cpu7_thermal: cpu7-thermal {
3950 polling-delay-passive = <250>;
3951 polling-delay = <0>;
3953 thermal-sensors = <&tsens0 10>;
3954 sustainable-power = <1202>;
3957 cpu7_alert0: trip-point0 {
3958 temperature = <90000>;
3959 hysteresis = <2000>;
3963 cpu7_alert1: trip-point1 {
3964 temperature = <95000>;
3965 hysteresis = <2000>;
3969 cpu7_crit: cpu_crit {
3970 temperature = <110000>;
3971 hysteresis = <1000>;
3978 trip = <&cpu7_alert0>;
3979 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3980 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3983 trip = <&cpu7_alert1>;
3984 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3985 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3990 cpu8_thermal: cpu8-thermal {
3991 polling-delay-passive = <250>;
3992 polling-delay = <0>;
3994 thermal-sensors = <&tsens0 11>;
3995 sustainable-power = <1202>;
3998 cpu8_alert0: trip-point0 {
3999 temperature = <90000>;
4000 hysteresis = <2000>;
4004 cpu8_alert1: trip-point1 {
4005 temperature = <95000>;
4006 hysteresis = <2000>;
4010 cpu8_crit: cpu_crit {
4011 temperature = <110000>;
4012 hysteresis = <1000>;
4019 trip = <&cpu8_alert0>;
4020 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4021 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4024 trip = <&cpu8_alert1>;
4025 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4026 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4031 cpu9_thermal: cpu9-thermal {
4032 polling-delay-passive = <250>;
4033 polling-delay = <0>;
4035 thermal-sensors = <&tsens0 12>;
4036 sustainable-power = <1202>;
4039 cpu9_alert0: trip-point0 {
4040 temperature = <90000>;
4041 hysteresis = <2000>;
4045 cpu9_alert1: trip-point1 {
4046 temperature = <95000>;
4047 hysteresis = <2000>;
4051 cpu9_crit: cpu_crit {
4052 temperature = <110000>;
4053 hysteresis = <1000>;
4060 trip = <&cpu9_alert0>;
4061 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4062 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4065 trip = <&cpu9_alert1>;
4066 cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067 <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4073 polling-delay-passive = <250>;
4074 polling-delay = <0>;
4076 thermal-sensors = <&tsens0 0>;
4079 aoss0_alert0: trip-point0 {
4080 temperature = <90000>;
4081 hysteresis = <2000>;
4085 aoss0_crit: aoss0_crit {
4086 temperature = <110000>;
4087 hysteresis = <2000>;
4094 polling-delay-passive = <250>;
4095 polling-delay = <0>;
4097 thermal-sensors = <&tsens0 7>;
4100 cpuss0_alert0: trip-point0 {
4101 temperature = <90000>;
4102 hysteresis = <2000>;
4105 cpuss0_crit: cluster0_crit {
4106 temperature = <110000>;
4107 hysteresis = <2000>;
4114 polling-delay-passive = <250>;
4115 polling-delay = <0>;
4117 thermal-sensors = <&tsens0 8>;
4120 cpuss1_alert0: trip-point0 {
4121 temperature = <90000>;
4122 hysteresis = <2000>;
4125 cpuss1_crit: cluster0_crit {
4126 temperature = <110000>;
4127 hysteresis = <2000>;
4134 polling-delay-passive = <250>;
4135 polling-delay = <0>;
4137 thermal-sensors = <&tsens0 13>;
4140 gpuss0_alert0: trip-point0 {
4141 temperature = <95000>;
4142 hysteresis = <2000>;
4146 gpuss0_crit: gpuss0_crit {
4147 temperature = <110000>;
4148 hysteresis = <2000>;
4155 trip = <&gpuss0_alert0>;
4156 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4162 polling-delay-passive = <250>;
4163 polling-delay = <0>;
4165 thermal-sensors = <&tsens0 14>;
4168 gpuss1_alert0: trip-point0 {
4169 temperature = <95000>;
4170 hysteresis = <2000>;
4174 gpuss1_crit: gpuss1_crit {
4175 temperature = <110000>;
4176 hysteresis = <2000>;
4183 trip = <&gpuss1_alert0>;
4184 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4190 polling-delay-passive = <250>;
4191 polling-delay = <0>;
4193 thermal-sensors = <&tsens1 0>;
4196 aoss1_alert0: trip-point0 {
4197 temperature = <90000>;
4198 hysteresis = <2000>;
4202 aoss1_crit: aoss1_crit {
4203 temperature = <110000>;
4204 hysteresis = <2000>;
4211 polling-delay-passive = <250>;
4212 polling-delay = <0>;
4214 thermal-sensors = <&tsens1 1>;
4217 cwlan_alert0: trip-point0 {
4218 temperature = <90000>;
4219 hysteresis = <2000>;
4223 cwlan_crit: cwlan_crit {
4224 temperature = <110000>;
4225 hysteresis = <2000>;
4232 polling-delay-passive = <250>;
4233 polling-delay = <0>;
4235 thermal-sensors = <&tsens1 2>;
4238 audio_alert0: trip-point0 {
4239 temperature = <90000>;
4240 hysteresis = <2000>;
4244 audio_crit: audio_crit {
4245 temperature = <110000>;
4246 hysteresis = <2000>;
4253 polling-delay-passive = <250>;
4254 polling-delay = <0>;
4256 thermal-sensors = <&tsens1 3>;
4259 ddr_alert0: trip-point0 {
4260 temperature = <90000>;
4261 hysteresis = <2000>;
4265 ddr_crit: ddr_crit {
4266 temperature = <110000>;
4267 hysteresis = <2000>;
4274 polling-delay-passive = <250>;
4275 polling-delay = <0>;
4277 thermal-sensors = <&tsens1 4>;
4280 q6_hvx_alert0: trip-point0 {
4281 temperature = <90000>;
4282 hysteresis = <2000>;
4286 q6_hvx_crit: q6_hvx_crit {
4287 temperature = <110000>;
4288 hysteresis = <2000>;
4295 polling-delay-passive = <250>;
4296 polling-delay = <0>;
4298 thermal-sensors = <&tsens1 5>;
4301 camera_alert0: trip-point0 {
4302 temperature = <90000>;
4303 hysteresis = <2000>;
4307 camera_crit: camera_crit {
4308 temperature = <110000>;
4309 hysteresis = <2000>;
4316 polling-delay-passive = <250>;
4317 polling-delay = <0>;
4319 thermal-sensors = <&tsens1 6>;
4322 mdm_alert0: trip-point0 {
4323 temperature = <90000>;
4324 hysteresis = <2000>;
4328 mdm_crit: mdm_crit {
4329 temperature = <110000>;
4330 hysteresis = <2000>;
4337 polling-delay-passive = <250>;
4338 polling-delay = <0>;
4340 thermal-sensors = <&tsens1 7>;
4343 mdm_dsp_alert0: trip-point0 {
4344 temperature = <90000>;
4345 hysteresis = <2000>;
4349 mdm_dsp_crit: mdm_dsp_crit {
4350 temperature = <110000>;
4351 hysteresis = <2000>;
4358 polling-delay-passive = <250>;
4359 polling-delay = <0>;
4361 thermal-sensors = <&tsens1 8>;
4364 npu_alert0: trip-point0 {
4365 temperature = <90000>;
4366 hysteresis = <2000>;
4370 npu_crit: npu_crit {
4371 temperature = <110000>;
4372 hysteresis = <2000>;
4379 polling-delay-passive = <250>;
4380 polling-delay = <0>;
4382 thermal-sensors = <&tsens1 9>;
4385 video_alert0: trip-point0 {
4386 temperature = <90000>;
4387 hysteresis = <2000>;
4391 video_crit: video_crit {
4392 temperature = <110000>;
4393 hysteresis = <2000>;
4401 compatible = "arm,armv8-timer";
4402 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4403 <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4404 <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4405 <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;