arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sc7180.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  18 #include <dt-bindings/power/qcom-aoss-qmp.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         aliases {
  34                 mmc1 = &sdhc_1;
  35                 mmc2 = &sdhc_2;
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi3 = &spi3;
  51                 spi5 = &spi5;
  52                 spi6 = &spi6;
  53                 spi8 = &spi8;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56         };
  57
  58         clocks {
  59                 xo_board: xo-board {
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <38400000>;
  62                         #clock-cells = <0>;
  63                 };
  64
  65                 sleep_clk: sleep-clk {
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32764>;
  68                         #clock-cells = <0>;
  69                 };
  70         };
  71
  72         reserved_memory: reserved-memory {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 hyp_mem: memory@80000000 {
  78                         reg = <0x0 0x80000000 0x0 0x600000>;
  79                         no-map;
  80                 };
  81
  82                 xbl_mem: memory@80600000 {
  83                         reg = <0x0 0x80600000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 aop_mem: memory@80800000 {
  88                         reg = <0x0 0x80800000 0x0 0x20000>;
  89                         no-map;
  90                 };
  91
  92                 aop_cmd_db_mem: memory@80820000 {
  93                         reg = <0x0 0x80820000 0x0 0x20000>;
  94                         compatible = "qcom,cmd-db";
  95                         no-map;
  96                 };
  97
  98                 sec_apps_mem: memory@808ff000 {
  99                         reg = <0x0 0x808ff000 0x0 0x1000>;
 100                         no-map;
 101                 };
 102
 103                 smem_mem: memory@80900000 {
 104                         reg = <0x0 0x80900000 0x0 0x200000>;
 105                         no-map;
 106                 };
 107
 108                 tz_mem: memory@80b00000 {
 109                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 110                         no-map;
 111                 };
 112
 113                 rmtfs_mem: memory@84400000 {
 114                         compatible = "qcom,rmtfs-mem";
 115                         reg = <0x0 0x84400000 0x0 0x200000>;
 116                         no-map;
 117
 118                         qcom,client-id = <1>;
 119                         qcom,vmid = <15>;
 120                 };
 121         };
 122
 123         cpus {
 124                 #address-cells = <2>;
 125                 #size-cells = <0>;
 126
 127                 CPU0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo468";
 130                         reg = <0x0 0x0>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 133                                            &LITTLE_CPU_SLEEP_1
 134                                            &CLUSTER_SLEEP_0>;
 135                         capacity-dmips-mhz = <1024>;
 136                         dynamic-power-coefficient = <100>;
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 139                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 140                         next-level-cache = <&L2_0>;
 141                         #cooling-cells = <2>;
 142                         qcom,freq-domain = <&cpufreq_hw 0>;
 143                         L2_0: l2-cache {
 144                                 compatible = "cache";
 145                                 next-level-cache = <&L3_0>;
 146                                 L3_0: l3-cache {
 147                                         compatible = "cache";
 148                                 };
 149                         };
 150                 };
 151
 152                 CPU1: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "qcom,kryo468";
 155                         reg = <0x0 0x100>;
 156                         enable-method = "psci";
 157                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 158                                            &LITTLE_CPU_SLEEP_1
 159                                            &CLUSTER_SLEEP_0>;
 160                         capacity-dmips-mhz = <1024>;
 161                         dynamic-power-coefficient = <100>;
 162                         next-level-cache = <&L2_100>;
 163                         operating-points-v2 = <&cpu0_opp_table>;
 164                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 165                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 166                         #cooling-cells = <2>;
 167                         qcom,freq-domain = <&cpufreq_hw 0>;
 168                         L2_100: l2-cache {
 169                                 compatible = "cache";
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172                 };
 173
 174                 CPU2: cpu@200 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo468";
 177                         reg = <0x0 0x200>;
 178                         enable-method = "psci";
 179                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 180                                            &LITTLE_CPU_SLEEP_1
 181                                            &CLUSTER_SLEEP_0>;
 182                         capacity-dmips-mhz = <1024>;
 183                         dynamic-power-coefficient = <100>;
 184                         next-level-cache = <&L2_200>;
 185                         operating-points-v2 = <&cpu0_opp_table>;
 186                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 187                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 188                         #cooling-cells = <2>;
 189                         qcom,freq-domain = <&cpufreq_hw 0>;
 190                         L2_200: l2-cache {
 191                                 compatible = "cache";
 192                                 next-level-cache = <&L3_0>;
 193                         };
 194                 };
 195
 196                 CPU3: cpu@300 {
 197                         device_type = "cpu";
 198                         compatible = "qcom,kryo468";
 199                         reg = <0x0 0x300>;
 200                         enable-method = "psci";
 201                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 202                                            &LITTLE_CPU_SLEEP_1
 203                                            &CLUSTER_SLEEP_0>;
 204                         capacity-dmips-mhz = <1024>;
 205                         dynamic-power-coefficient = <100>;
 206                         next-level-cache = <&L2_300>;
 207                         operating-points-v2 = <&cpu0_opp_table>;
 208                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 209                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 210                         #cooling-cells = <2>;
 211                         qcom,freq-domain = <&cpufreq_hw 0>;
 212                         L2_300: l2-cache {
 213                                 compatible = "cache";
 214                                 next-level-cache = <&L3_0>;
 215                         };
 216                 };
 217
 218                 CPU4: cpu@400 {
 219                         device_type = "cpu";
 220                         compatible = "qcom,kryo468";
 221                         reg = <0x0 0x400>;
 222                         enable-method = "psci";
 223                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 224                                            &LITTLE_CPU_SLEEP_1
 225                                            &CLUSTER_SLEEP_0>;
 226                         capacity-dmips-mhz = <1024>;
 227                         dynamic-power-coefficient = <100>;
 228                         next-level-cache = <&L2_400>;
 229                         operating-points-v2 = <&cpu0_opp_table>;
 230                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 231                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 232                         #cooling-cells = <2>;
 233                         qcom,freq-domain = <&cpufreq_hw 0>;
 234                         L2_400: l2-cache {
 235                                 compatible = "cache";
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 CPU5: cpu@500 {
 241                         device_type = "cpu";
 242                         compatible = "qcom,kryo468";
 243                         reg = <0x0 0x500>;
 244                         enable-method = "psci";
 245                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 246                                            &LITTLE_CPU_SLEEP_1
 247                                            &CLUSTER_SLEEP_0>;
 248                         capacity-dmips-mhz = <1024>;
 249                         dynamic-power-coefficient = <100>;
 250                         next-level-cache = <&L2_500>;
 251                         operating-points-v2 = <&cpu0_opp_table>;
 252                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 253                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 254                         #cooling-cells = <2>;
 255                         qcom,freq-domain = <&cpufreq_hw 0>;
 256                         L2_500: l2-cache {
 257                                 compatible = "cache";
 258                                 next-level-cache = <&L3_0>;
 259                         };
 260                 };
 261
 262                 CPU6: cpu@600 {
 263                         device_type = "cpu";
 264                         compatible = "qcom,kryo468";
 265                         reg = <0x0 0x600>;
 266                         enable-method = "psci";
 267                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 268                                            &BIG_CPU_SLEEP_1
 269                                            &CLUSTER_SLEEP_0>;
 270                         capacity-dmips-mhz = <1740>;
 271                         dynamic-power-coefficient = <405>;
 272                         next-level-cache = <&L2_600>;
 273                         operating-points-v2 = <&cpu6_opp_table>;
 274                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 275                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 276                         #cooling-cells = <2>;
 277                         qcom,freq-domain = <&cpufreq_hw 1>;
 278                         L2_600: l2-cache {
 279                                 compatible = "cache";
 280                                 next-level-cache = <&L3_0>;
 281                         };
 282                 };
 283
 284                 CPU7: cpu@700 {
 285                         device_type = "cpu";
 286                         compatible = "qcom,kryo468";
 287                         reg = <0x0 0x700>;
 288                         enable-method = "psci";
 289                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 290                                            &BIG_CPU_SLEEP_1
 291                                            &CLUSTER_SLEEP_0>;
 292                         capacity-dmips-mhz = <1740>;
 293                         dynamic-power-coefficient = <405>;
 294                         next-level-cache = <&L2_700>;
 295                         operating-points-v2 = <&cpu6_opp_table>;
 296                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 297                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 298                         #cooling-cells = <2>;
 299                         qcom,freq-domain = <&cpufreq_hw 1>;
 300                         L2_700: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 cpu-map {
 307                         cluster0 {
 308                                 core0 {
 309                                         cpu = <&CPU0>;
 310                                 };
 311
 312                                 core1 {
 313                                         cpu = <&CPU1>;
 314                                 };
 315
 316                                 core2 {
 317                                         cpu = <&CPU2>;
 318                                 };
 319
 320                                 core3 {
 321                                         cpu = <&CPU3>;
 322                                 };
 323
 324                                 core4 {
 325                                         cpu = <&CPU4>;
 326                                 };
 327
 328                                 core5 {
 329                                         cpu = <&CPU5>;
 330                                 };
 331
 332                                 core6 {
 333                                         cpu = <&CPU6>;
 334                                 };
 335
 336                                 core7 {
 337                                         cpu = <&CPU7>;
 338                                 };
 339                         };
 340                 };
 341
 342                 idle-states {
 343                         entry-method = "psci";
 344
 345                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 346                                 compatible = "arm,idle-state";
 347                                 idle-state-name = "little-power-down";
 348                                 arm,psci-suspend-param = <0x40000003>;
 349                                 entry-latency-us = <549>;
 350                                 exit-latency-us = <901>;
 351                                 min-residency-us = <1774>;
 352                                 local-timer-stop;
 353                         };
 354
 355                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 356                                 compatible = "arm,idle-state";
 357                                 idle-state-name = "little-rail-power-down";
 358                                 arm,psci-suspend-param = <0x40000004>;
 359                                 entry-latency-us = <702>;
 360                                 exit-latency-us = <915>;
 361                                 min-residency-us = <4001>;
 362                                 local-timer-stop;
 363                         };
 364
 365                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 366                                 compatible = "arm,idle-state";
 367                                 idle-state-name = "big-power-down";
 368                                 arm,psci-suspend-param = <0x40000003>;
 369                                 entry-latency-us = <523>;
 370                                 exit-latency-us = <1244>;
 371                                 min-residency-us = <2207>;
 372                                 local-timer-stop;
 373                         };
 374
 375                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 376                                 compatible = "arm,idle-state";
 377                                 idle-state-name = "big-rail-power-down";
 378                                 arm,psci-suspend-param = <0x40000004>;
 379                                 entry-latency-us = <526>;
 380                                 exit-latency-us = <1854>;
 381                                 min-residency-us = <5555>;
 382                                 local-timer-stop;
 383                         };
 384
 385                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 386                                 compatible = "arm,idle-state";
 387                                 idle-state-name = "cluster-power-down";
 388                                 arm,psci-suspend-param = <0x40003444>;
 389                                 entry-latency-us = <3263>;
 390                                 exit-latency-us = <6562>;
 391                                 min-residency-us = <9926>;
 392                                 local-timer-stop;
 393                         };
 394                 };
 395         };
 396
 397         cpu0_opp_table: cpu0_opp_table {
 398                 compatible = "operating-points-v2";
 399                 opp-shared;
 400
 401                 cpu0_opp1: opp-300000000 {
 402                         opp-hz = /bits/ 64 <300000000>;
 403                         opp-peak-kBps = <1200000 4800000>;
 404                 };
 405
 406                 cpu0_opp2: opp-576000000 {
 407                         opp-hz = /bits/ 64 <576000000>;
 408                         opp-peak-kBps = <1200000 4800000>;
 409                 };
 410
 411                 cpu0_opp3: opp-768000000 {
 412                         opp-hz = /bits/ 64 <768000000>;
 413                         opp-peak-kBps = <1200000 4800000>;
 414                 };
 415
 416                 cpu0_opp4: opp-1017600000 {
 417                         opp-hz = /bits/ 64 <1017600000>;
 418                         opp-peak-kBps = <1804000 8908800>;
 419                 };
 420
 421                 cpu0_opp5: opp-1248000000 {
 422                         opp-hz = /bits/ 64 <1248000000>;
 423                         opp-peak-kBps = <2188000 12902400>;
 424                 };
 425
 426                 cpu0_opp6: opp-1324800000 {
 427                         opp-hz = /bits/ 64 <1324800000>;
 428                         opp-peak-kBps = <2188000 12902400>;
 429                 };
 430
 431                 cpu0_opp7: opp-1516800000 {
 432                         opp-hz = /bits/ 64 <1516800000>;
 433                         opp-peak-kBps = <3072000 15052800>;
 434                 };
 435
 436                 cpu0_opp8: opp-1612800000 {
 437                         opp-hz = /bits/ 64 <1612800000>;
 438                         opp-peak-kBps = <3072000 15052800>;
 439                 };
 440
 441                 cpu0_opp9: opp-1708800000 {
 442                         opp-hz = /bits/ 64 <1708800000>;
 443                         opp-peak-kBps = <3072000 15052800>;
 444                 };
 445
 446                 cpu0_opp10: opp-1804800000 {
 447                         opp-hz = /bits/ 64 <1804800000>;
 448                         opp-peak-kBps = <4068000 22425600>;
 449                 };
 450         };
 451
 452         cpu6_opp_table: cpu6_opp_table {
 453                 compatible = "operating-points-v2";
 454                 opp-shared;
 455
 456                 cpu6_opp1: opp-300000000 {
 457                         opp-hz = /bits/ 64 <300000000>;
 458                         opp-peak-kBps = <2188000 8908800>;
 459                 };
 460
 461                 cpu6_opp2: opp-652800000 {
 462                         opp-hz = /bits/ 64 <652800000>;
 463                         opp-peak-kBps = <2188000 8908800>;
 464                 };
 465
 466                 cpu6_opp3: opp-825600000 {
 467                         opp-hz = /bits/ 64 <825600000>;
 468                         opp-peak-kBps = <2188000 8908800>;
 469                 };
 470
 471                 cpu6_opp4: opp-979200000 {
 472                         opp-hz = /bits/ 64 <979200000>;
 473                         opp-peak-kBps = <2188000 8908800>;
 474                 };
 475
 476                 cpu6_opp5: opp-1113600000 {
 477                         opp-hz = /bits/ 64 <1113600000>;
 478                         opp-peak-kBps = <2188000 8908800>;
 479                 };
 480
 481                 cpu6_opp6: opp-1267200000 {
 482                         opp-hz = /bits/ 64 <1267200000>;
 483                         opp-peak-kBps = <4068000 12902400>;
 484                 };
 485
 486                 cpu6_opp7: opp-1555200000 {
 487                         opp-hz = /bits/ 64 <1555200000>;
 488                         opp-peak-kBps = <4068000 15052800>;
 489                 };
 490
 491                 cpu6_opp8: opp-1708800000 {
 492                         opp-hz = /bits/ 64 <1708800000>;
 493                         opp-peak-kBps = <6220000 19353600>;
 494                 };
 495
 496                 cpu6_opp9: opp-1843200000 {
 497                         opp-hz = /bits/ 64 <1843200000>;
 498                         opp-peak-kBps = <6220000 19353600>;
 499                 };
 500
 501                 cpu6_opp10: opp-1900800000 {
 502                         opp-hz = /bits/ 64 <1900800000>;
 503                         opp-peak-kBps = <6220000 22425600>;
 504                 };
 505
 506                 cpu6_opp11: opp-1996800000 {
 507                         opp-hz = /bits/ 64 <1996800000>;
 508                         opp-peak-kBps = <6220000 22425600>;
 509                 };
 510
 511                 cpu6_opp12: opp-2112000000 {
 512                         opp-hz = /bits/ 64 <2112000000>;
 513                         opp-peak-kBps = <6220000 22425600>;
 514                 };
 515
 516                 cpu6_opp13: opp-2208000000 {
 517                         opp-hz = /bits/ 64 <2208000000>;
 518                         opp-peak-kBps = <7216000 22425600>;
 519                 };
 520
 521                 cpu6_opp14: opp-2323200000 {
 522                         opp-hz = /bits/ 64 <2323200000>;
 523                         opp-peak-kBps = <7216000 22425600>;
 524                 };
 525
 526                 cpu6_opp15: opp-2400000000 {
 527                         opp-hz = /bits/ 64 <2400000000>;
 528                         opp-peak-kBps = <8532000 23347200>;
 529                 };
 530
 531                 cpu6_opp16: opp-2553600000 {
 532                         opp-hz = /bits/ 64 <2553600000>;
 533                         opp-peak-kBps = <8532000 23347200>;
 534                 };
 535         };
 536
 537         memory@80000000 {
 538                 device_type = "memory";
 539                 /* We expect the bootloader to fill in the size */
 540                 reg = <0 0x80000000 0 0>;
 541         };
 542
 543         pmu {
 544                 compatible = "arm,armv8-pmuv3";
 545                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 546         };
 547
 548         firmware {
 549                 scm {
 550                         compatible = "qcom,scm-sc7180", "qcom,scm";
 551                 };
 552         };
 553
 554         tcsr_mutex: hwlock {
 555                 compatible = "qcom,tcsr-mutex";
 556                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 557                 #hwlock-cells = <1>;
 558         };
 559
 560         smem {
 561                 compatible = "qcom,smem";
 562                 memory-region = <&smem_mem>;
 563                 hwlocks = <&tcsr_mutex 3>;
 564         };
 565
 566         smp2p-cdsp {
 567                 compatible = "qcom,smp2p";
 568                 qcom,smem = <94>, <432>;
 569
 570                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 571
 572                 mboxes = <&apss_shared 6>;
 573
 574                 qcom,local-pid = <0>;
 575                 qcom,remote-pid = <5>;
 576
 577                 cdsp_smp2p_out: master-kernel {
 578                         qcom,entry-name = "master-kernel";
 579                         #qcom,smem-state-cells = <1>;
 580                 };
 581
 582                 cdsp_smp2p_in: slave-kernel {
 583                         qcom,entry-name = "slave-kernel";
 584
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                 };
 588         };
 589
 590         smp2p-lpass {
 591                 compatible = "qcom,smp2p";
 592                 qcom,smem = <443>, <429>;
 593
 594                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 595
 596                 mboxes = <&apss_shared 10>;
 597
 598                 qcom,local-pid = <0>;
 599                 qcom,remote-pid = <2>;
 600
 601                 adsp_smp2p_out: master-kernel {
 602                         qcom,entry-name = "master-kernel";
 603                         #qcom,smem-state-cells = <1>;
 604                 };
 605
 606                 adsp_smp2p_in: slave-kernel {
 607                         qcom,entry-name = "slave-kernel";
 608
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                 };
 612         };
 613
 614         smp2p-mpss {
 615                 compatible = "qcom,smp2p";
 616                 qcom,smem = <435>, <428>;
 617                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 618                 mboxes = <&apss_shared 14>;
 619                 qcom,local-pid = <0>;
 620                 qcom,remote-pid = <1>;
 621
 622                 modem_smp2p_out: master-kernel {
 623                         qcom,entry-name = "master-kernel";
 624                         #qcom,smem-state-cells = <1>;
 625                 };
 626
 627                 modem_smp2p_in: slave-kernel {
 628                         qcom,entry-name = "slave-kernel";
 629                         interrupt-controller;
 630                         #interrupt-cells = <2>;
 631                 };
 632
 633                 ipa_smp2p_out: ipa-ap-to-modem {
 634                         qcom,entry-name = "ipa";
 635                         #qcom,smem-state-cells = <1>;
 636                 };
 637
 638                 ipa_smp2p_in: ipa-modem-to-ap {
 639                         qcom,entry-name = "ipa";
 640                         interrupt-controller;
 641                         #interrupt-cells = <2>;
 642                 };
 643         };
 644
 645         psci {
 646                 compatible = "arm,psci-1.0";
 647                 method = "smc";
 648         };
 649
 650         soc: soc@0 {
 651                 #address-cells = <2>;
 652                 #size-cells = <2>;
 653                 ranges = <0 0 0 0 0x10 0>;
 654                 dma-ranges = <0 0 0 0 0x10 0>;
 655                 compatible = "simple-bus";
 656
 657                 gcc: clock-controller@100000 {
 658                         compatible = "qcom,gcc-sc7180";
 659                         reg = <0 0x00100000 0 0x1f0000>;
 660                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 661                                  <&rpmhcc RPMH_CXO_CLK_A>,
 662                                  <&sleep_clk>;
 663                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 664                         #clock-cells = <1>;
 665                         #reset-cells = <1>;
 666                         #power-domain-cells = <1>;
 667                 };
 668
 669                 qfprom: efuse@784000 {
 670                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 671                         reg = <0 0x00784000 0 0x8ff>,
 672                               <0 0x00780000 0 0x7a0>,
 673                               <0 0x00782000 0 0x100>,
 674                               <0 0x00786000 0 0x1fff>;
 675
 676                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 677                         clock-names = "core";
 678                         #address-cells = <1>;
 679                         #size-cells = <1>;
 680
 681                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 682                                 reg = <0x25b 0x1>;
 683                                 bits = <1 3>;
 684                         };
 685                 };
 686
 687                 sdhc_1: sdhci@7c4000 {
 688                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 689                         reg = <0 0x7c4000 0 0x1000>,
 690                                 <0 0x07c5000 0 0x1000>;
 691                         reg-names = "hc", "cqhci";
 692
 693                         iommus = <&apps_smmu 0x60 0x0>;
 694                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 695                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 696                         interrupt-names = "hc_irq", "pwr_irq";
 697
 698                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 699                                         <&gcc GCC_SDCC1_AHB_CLK>;
 700                         clock-names = "core", "iface";
 701                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 702                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 703                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 704                         power-domains = <&rpmhpd SC7180_CX>;
 705                         operating-points-v2 = <&sdhc1_opp_table>;
 706
 707                         bus-width = <8>;
 708                         non-removable;
 709                         supports-cqe;
 710
 711                         mmc-ddr-1_8v;
 712                         mmc-hs200-1_8v;
 713                         mmc-hs400-1_8v;
 714                         mmc-hs400-enhanced-strobe;
 715
 716                         status = "disabled";
 717
 718                         sdhc1_opp_table: sdhc1-opp-table {
 719                                 compatible = "operating-points-v2";
 720
 721                                 opp-100000000 {
 722                                         opp-hz = /bits/ 64 <100000000>;
 723                                         required-opps = <&rpmhpd_opp_low_svs>;
 724                                         opp-peak-kBps = <100000 100000>;
 725                                         opp-avg-kBps = <100000 50000>;
 726                                 };
 727
 728                                 opp-384000000 {
 729                                         opp-hz = /bits/ 64 <384000000>;
 730                                         required-opps = <&rpmhpd_opp_svs_l1>;
 731                                         opp-peak-kBps = <600000 900000>;
 732                                         opp-avg-kBps = <261438 300000>;
 733                                 };
 734                         };
 735                 };
 736
 737                 qup_opp_table: qup-opp-table {
 738                         compatible = "operating-points-v2";
 739
 740                         opp-75000000 {
 741                                 opp-hz = /bits/ 64 <75000000>;
 742                                 required-opps = <&rpmhpd_opp_low_svs>;
 743                         };
 744
 745                         opp-100000000 {
 746                                 opp-hz = /bits/ 64 <100000000>;
 747                                 required-opps = <&rpmhpd_opp_svs>;
 748                         };
 749
 750                         opp-128000000 {
 751                                 opp-hz = /bits/ 64 <128000000>;
 752                                 required-opps = <&rpmhpd_opp_nom>;
 753                         };
 754                 };
 755
 756                 qupv3_id_0: geniqup@8c0000 {
 757                         compatible = "qcom,geni-se-qup";
 758                         reg = <0 0x008c0000 0 0x6000>;
 759                         clock-names = "m-ahb", "s-ahb";
 760                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 761                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 762                         #address-cells = <2>;
 763                         #size-cells = <2>;
 764                         ranges;
 765                         iommus = <&apps_smmu 0x43 0x0>;
 766                         interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
 767                         interconnect-names = "qup-core";
 768                         status = "disabled";
 769
 770                         i2c0: i2c@880000 {
 771                                 compatible = "qcom,geni-i2c";
 772                                 reg = <0 0x00880000 0 0x4000>;
 773                                 clock-names = "se";
 774                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 775                                 pinctrl-names = "default";
 776                                 pinctrl-0 = <&qup_i2c0_default>;
 777                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 778                                 #address-cells = <1>;
 779                                 #size-cells = <0>;
 780                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 781                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 782                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 783                                 interconnect-names = "qup-core", "qup-config",
 784                                                         "qup-memory";
 785                                 status = "disabled";
 786                         };
 787
 788                         spi0: spi@880000 {
 789                                 compatible = "qcom,geni-spi";
 790                                 reg = <0 0x00880000 0 0x4000>;
 791                                 clock-names = "se";
 792                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 793                                 pinctrl-names = "default";
 794                                 pinctrl-0 = <&qup_spi0_default>;
 795                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 796                                 #address-cells = <1>;
 797                                 #size-cells = <0>;
 798                                 power-domains = <&rpmhpd SC7180_CX>;
 799                                 operating-points-v2 = <&qup_opp_table>;
 800                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 801                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 802                                 interconnect-names = "qup-core", "qup-config";
 803                                 status = "disabled";
 804                         };
 805
 806                         uart0: serial@880000 {
 807                                 compatible = "qcom,geni-uart";
 808                                 reg = <0 0x00880000 0 0x4000>;
 809                                 clock-names = "se";
 810                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 811                                 pinctrl-names = "default";
 812                                 pinctrl-0 = <&qup_uart0_default>;
 813                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 814                                 power-domains = <&rpmhpd SC7180_CX>;
 815                                 operating-points-v2 = <&qup_opp_table>;
 816                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 817                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 818                                 interconnect-names = "qup-core", "qup-config";
 819                                 status = "disabled";
 820                         };
 821
 822                         i2c1: i2c@884000 {
 823                                 compatible = "qcom,geni-i2c";
 824                                 reg = <0 0x00884000 0 0x4000>;
 825                                 clock-names = "se";
 826                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 827                                 pinctrl-names = "default";
 828                                 pinctrl-0 = <&qup_i2c1_default>;
 829                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 830                                 #address-cells = <1>;
 831                                 #size-cells = <0>;
 832                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 833                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 834                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 835                                 interconnect-names = "qup-core", "qup-config",
 836                                                         "qup-memory";
 837                                 status = "disabled";
 838                         };
 839
 840                         spi1: spi@884000 {
 841                                 compatible = "qcom,geni-spi";
 842                                 reg = <0 0x00884000 0 0x4000>;
 843                                 clock-names = "se";
 844                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 845                                 pinctrl-names = "default";
 846                                 pinctrl-0 = <&qup_spi1_default>;
 847                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 848                                 #address-cells = <1>;
 849                                 #size-cells = <0>;
 850                                 power-domains = <&rpmhpd SC7180_CX>;
 851                                 operating-points-v2 = <&qup_opp_table>;
 852                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 853                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 854                                 interconnect-names = "qup-core", "qup-config";
 855                                 status = "disabled";
 856                         };
 857
 858                         uart1: serial@884000 {
 859                                 compatible = "qcom,geni-uart";
 860                                 reg = <0 0x00884000 0 0x4000>;
 861                                 clock-names = "se";
 862                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 863                                 pinctrl-names = "default";
 864                                 pinctrl-0 = <&qup_uart1_default>;
 865                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 866                                 power-domains = <&rpmhpd SC7180_CX>;
 867                                 operating-points-v2 = <&qup_opp_table>;
 868                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 869                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 870                                 interconnect-names = "qup-core", "qup-config";
 871                                 status = "disabled";
 872                         };
 873
 874                         i2c2: i2c@888000 {
 875                                 compatible = "qcom,geni-i2c";
 876                                 reg = <0 0x00888000 0 0x4000>;
 877                                 clock-names = "se";
 878                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 879                                 pinctrl-names = "default";
 880                                 pinctrl-0 = <&qup_i2c2_default>;
 881                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 885                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 886                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 887                                 interconnect-names = "qup-core", "qup-config",
 888                                                         "qup-memory";
 889                                 status = "disabled";
 890                         };
 891
 892                         uart2: serial@888000 {
 893                                 compatible = "qcom,geni-uart";
 894                                 reg = <0 0x00888000 0 0x4000>;
 895                                 clock-names = "se";
 896                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 897                                 pinctrl-names = "default";
 898                                 pinctrl-0 = <&qup_uart2_default>;
 899                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 900                                 power-domains = <&rpmhpd SC7180_CX>;
 901                                 operating-points-v2 = <&qup_opp_table>;
 902                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 903                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 904                                 interconnect-names = "qup-core", "qup-config";
 905                                 status = "disabled";
 906                         };
 907
 908                         i2c3: i2c@88c000 {
 909                                 compatible = "qcom,geni-i2c";
 910                                 reg = <0 0x0088c000 0 0x4000>;
 911                                 clock-names = "se";
 912                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 913                                 pinctrl-names = "default";
 914                                 pinctrl-0 = <&qup_i2c3_default>;
 915                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 916                                 #address-cells = <1>;
 917                                 #size-cells = <0>;
 918                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 919                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 920                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 921                                 interconnect-names = "qup-core", "qup-config",
 922                                                         "qup-memory";
 923                                 status = "disabled";
 924                         };
 925
 926                         spi3: spi@88c000 {
 927                                 compatible = "qcom,geni-spi";
 928                                 reg = <0 0x0088c000 0 0x4000>;
 929                                 clock-names = "se";
 930                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 931                                 pinctrl-names = "default";
 932                                 pinctrl-0 = <&qup_spi3_default>;
 933                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936                                 power-domains = <&rpmhpd SC7180_CX>;
 937                                 operating-points-v2 = <&qup_opp_table>;
 938                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 939                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 940                                 interconnect-names = "qup-core", "qup-config";
 941                                 status = "disabled";
 942                         };
 943
 944                         uart3: serial@88c000 {
 945                                 compatible = "qcom,geni-uart";
 946                                 reg = <0 0x0088c000 0 0x4000>;
 947                                 clock-names = "se";
 948                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 949                                 pinctrl-names = "default";
 950                                 pinctrl-0 = <&qup_uart3_default>;
 951                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 952                                 power-domains = <&rpmhpd SC7180_CX>;
 953                                 operating-points-v2 = <&qup_opp_table>;
 954                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 955                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 956                                 interconnect-names = "qup-core", "qup-config";
 957                                 status = "disabled";
 958                         };
 959
 960                         i2c4: i2c@890000 {
 961                                 compatible = "qcom,geni-i2c";
 962                                 reg = <0 0x00890000 0 0x4000>;
 963                                 clock-names = "se";
 964                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 965                                 pinctrl-names = "default";
 966                                 pinctrl-0 = <&qup_i2c4_default>;
 967                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 968                                 #address-cells = <1>;
 969                                 #size-cells = <0>;
 970                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 971                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 972                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 973                                 interconnect-names = "qup-core", "qup-config",
 974                                                         "qup-memory";
 975                                 status = "disabled";
 976                         };
 977
 978                         uart4: serial@890000 {
 979                                 compatible = "qcom,geni-uart";
 980                                 reg = <0 0x00890000 0 0x4000>;
 981                                 clock-names = "se";
 982                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 983                                 pinctrl-names = "default";
 984                                 pinctrl-0 = <&qup_uart4_default>;
 985                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 986                                 power-domains = <&rpmhpd SC7180_CX>;
 987                                 operating-points-v2 = <&qup_opp_table>;
 988                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 989                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 990                                 interconnect-names = "qup-core", "qup-config";
 991                                 status = "disabled";
 992                         };
 993
 994                         i2c5: i2c@894000 {
 995                                 compatible = "qcom,geni-i2c";
 996                                 reg = <0 0x00894000 0 0x4000>;
 997                                 clock-names = "se";
 998                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 999                                 pinctrl-names = "default";
1000                                 pinctrl-0 = <&qup_i2c5_default>;
1001                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1002                                 #address-cells = <1>;
1003                                 #size-cells = <0>;
1004                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1005                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1006                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1007                                 interconnect-names = "qup-core", "qup-config",
1008                                                         "qup-memory";
1009                                 status = "disabled";
1010                         };
1011
1012                         spi5: spi@894000 {
1013                                 compatible = "qcom,geni-spi";
1014                                 reg = <0 0x00894000 0 0x4000>;
1015                                 clock-names = "se";
1016                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1017                                 pinctrl-names = "default";
1018                                 pinctrl-0 = <&qup_spi5_default>;
1019                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1020                                 #address-cells = <1>;
1021                                 #size-cells = <0>;
1022                                 power-domains = <&rpmhpd SC7180_CX>;
1023                                 operating-points-v2 = <&qup_opp_table>;
1024                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1025                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1026                                 interconnect-names = "qup-core", "qup-config";
1027                                 status = "disabled";
1028                         };
1029
1030                         uart5: serial@894000 {
1031                                 compatible = "qcom,geni-uart";
1032                                 reg = <0 0x00894000 0 0x4000>;
1033                                 clock-names = "se";
1034                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1035                                 pinctrl-names = "default";
1036                                 pinctrl-0 = <&qup_uart5_default>;
1037                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1038                                 power-domains = <&rpmhpd SC7180_CX>;
1039                                 operating-points-v2 = <&qup_opp_table>;
1040                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1041                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1042                                 interconnect-names = "qup-core", "qup-config";
1043                                 status = "disabled";
1044                         };
1045                 };
1046
1047                 qupv3_id_1: geniqup@ac0000 {
1048                         compatible = "qcom,geni-se-qup";
1049                         reg = <0 0x00ac0000 0 0x6000>;
1050                         clock-names = "m-ahb", "s-ahb";
1051                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1052                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1053                         #address-cells = <2>;
1054                         #size-cells = <2>;
1055                         ranges;
1056                         iommus = <&apps_smmu 0x4c3 0x0>;
1057                         interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
1058                         interconnect-names = "qup-core";
1059                         status = "disabled";
1060
1061                         i2c6: i2c@a80000 {
1062                                 compatible = "qcom,geni-i2c";
1063                                 reg = <0 0x00a80000 0 0x4000>;
1064                                 clock-names = "se";
1065                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1066                                 pinctrl-names = "default";
1067                                 pinctrl-0 = <&qup_i2c6_default>;
1068                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1072                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1073                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1074                                 interconnect-names = "qup-core", "qup-config",
1075                                                         "qup-memory";
1076                                 status = "disabled";
1077                         };
1078
1079                         spi6: spi@a80000 {
1080                                 compatible = "qcom,geni-spi";
1081                                 reg = <0 0x00a80000 0 0x4000>;
1082                                 clock-names = "se";
1083                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1084                                 pinctrl-names = "default";
1085                                 pinctrl-0 = <&qup_spi6_default>;
1086                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1087                                 #address-cells = <1>;
1088                                 #size-cells = <0>;
1089                                 power-domains = <&rpmhpd SC7180_CX>;
1090                                 operating-points-v2 = <&qup_opp_table>;
1091                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1092                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1093                                 interconnect-names = "qup-core", "qup-config";
1094                                 status = "disabled";
1095                         };
1096
1097                         uart6: serial@a80000 {
1098                                 compatible = "qcom,geni-uart";
1099                                 reg = <0 0x00a80000 0 0x4000>;
1100                                 clock-names = "se";
1101                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1102                                 pinctrl-names = "default";
1103                                 pinctrl-0 = <&qup_uart6_default>;
1104                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1105                                 power-domains = <&rpmhpd SC7180_CX>;
1106                                 operating-points-v2 = <&qup_opp_table>;
1107                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1108                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1109                                 interconnect-names = "qup-core", "qup-config";
1110                                 status = "disabled";
1111                         };
1112
1113                         i2c7: i2c@a84000 {
1114                                 compatible = "qcom,geni-i2c";
1115                                 reg = <0 0x00a84000 0 0x4000>;
1116                                 clock-names = "se";
1117                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1118                                 pinctrl-names = "default";
1119                                 pinctrl-0 = <&qup_i2c7_default>;
1120                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1121                                 #address-cells = <1>;
1122                                 #size-cells = <0>;
1123                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1124                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1125                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1126                                 interconnect-names = "qup-core", "qup-config",
1127                                                         "qup-memory";
1128                                 status = "disabled";
1129                         };
1130
1131                         uart7: serial@a84000 {
1132                                 compatible = "qcom,geni-uart";
1133                                 reg = <0 0x00a84000 0 0x4000>;
1134                                 clock-names = "se";
1135                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1136                                 pinctrl-names = "default";
1137                                 pinctrl-0 = <&qup_uart7_default>;
1138                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1139                                 power-domains = <&rpmhpd SC7180_CX>;
1140                                 operating-points-v2 = <&qup_opp_table>;
1141                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1142                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1143                                 interconnect-names = "qup-core", "qup-config";
1144                                 status = "disabled";
1145                         };
1146
1147                         i2c8: i2c@a88000 {
1148                                 compatible = "qcom,geni-i2c";
1149                                 reg = <0 0x00a88000 0 0x4000>;
1150                                 clock-names = "se";
1151                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1152                                 pinctrl-names = "default";
1153                                 pinctrl-0 = <&qup_i2c8_default>;
1154                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1155                                 #address-cells = <1>;
1156                                 #size-cells = <0>;
1157                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1158                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1159                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1160                                 interconnect-names = "qup-core", "qup-config",
1161                                                         "qup-memory";
1162                                 status = "disabled";
1163                         };
1164
1165                         spi8: spi@a88000 {
1166                                 compatible = "qcom,geni-spi";
1167                                 reg = <0 0x00a88000 0 0x4000>;
1168                                 clock-names = "se";
1169                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1170                                 pinctrl-names = "default";
1171                                 pinctrl-0 = <&qup_spi8_default>;
1172                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1173                                 #address-cells = <1>;
1174                                 #size-cells = <0>;
1175                                 power-domains = <&rpmhpd SC7180_CX>;
1176                                 operating-points-v2 = <&qup_opp_table>;
1177                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1178                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1179                                 interconnect-names = "qup-core", "qup-config";
1180                                 status = "disabled";
1181                         };
1182
1183                         uart8: serial@a88000 {
1184                                 compatible = "qcom,geni-debug-uart";
1185                                 reg = <0 0x00a88000 0 0x4000>;
1186                                 clock-names = "se";
1187                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1188                                 pinctrl-names = "default";
1189                                 pinctrl-0 = <&qup_uart8_default>;
1190                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1191                                 power-domains = <&rpmhpd SC7180_CX>;
1192                                 operating-points-v2 = <&qup_opp_table>;
1193                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1194                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1195                                 interconnect-names = "qup-core", "qup-config";
1196                                 status = "disabled";
1197                         };
1198
1199                         i2c9: i2c@a8c000 {
1200                                 compatible = "qcom,geni-i2c";
1201                                 reg = <0 0x00a8c000 0 0x4000>;
1202                                 clock-names = "se";
1203                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1204                                 pinctrl-names = "default";
1205                                 pinctrl-0 = <&qup_i2c9_default>;
1206                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1207                                 #address-cells = <1>;
1208                                 #size-cells = <0>;
1209                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1210                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1211                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1212                                 interconnect-names = "qup-core", "qup-config",
1213                                                         "qup-memory";
1214                                 status = "disabled";
1215                         };
1216
1217                         uart9: serial@a8c000 {
1218                                 compatible = "qcom,geni-uart";
1219                                 reg = <0 0x00a8c000 0 0x4000>;
1220                                 clock-names = "se";
1221                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1222                                 pinctrl-names = "default";
1223                                 pinctrl-0 = <&qup_uart9_default>;
1224                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1225                                 power-domains = <&rpmhpd SC7180_CX>;
1226                                 operating-points-v2 = <&qup_opp_table>;
1227                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1228                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1229                                 interconnect-names = "qup-core", "qup-config";
1230                                 status = "disabled";
1231                         };
1232
1233                         i2c10: i2c@a90000 {
1234                                 compatible = "qcom,geni-i2c";
1235                                 reg = <0 0x00a90000 0 0x4000>;
1236                                 clock-names = "se";
1237                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1238                                 pinctrl-names = "default";
1239                                 pinctrl-0 = <&qup_i2c10_default>;
1240                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1241                                 #address-cells = <1>;
1242                                 #size-cells = <0>;
1243                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1244                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1245                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1246                                 interconnect-names = "qup-core", "qup-config",
1247                                                         "qup-memory";
1248                                 status = "disabled";
1249                         };
1250
1251                         spi10: spi@a90000 {
1252                                 compatible = "qcom,geni-spi";
1253                                 reg = <0 0x00a90000 0 0x4000>;
1254                                 clock-names = "se";
1255                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1256                                 pinctrl-names = "default";
1257                                 pinctrl-0 = <&qup_spi10_default>;
1258                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1259                                 #address-cells = <1>;
1260                                 #size-cells = <0>;
1261                                 power-domains = <&rpmhpd SC7180_CX>;
1262                                 operating-points-v2 = <&qup_opp_table>;
1263                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1264                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1265                                 interconnect-names = "qup-core", "qup-config";
1266                                 status = "disabled";
1267                         };
1268
1269                         uart10: serial@a90000 {
1270                                 compatible = "qcom,geni-uart";
1271                                 reg = <0 0x00a90000 0 0x4000>;
1272                                 clock-names = "se";
1273                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1274                                 pinctrl-names = "default";
1275                                 pinctrl-0 = <&qup_uart10_default>;
1276                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1277                                 power-domains = <&rpmhpd SC7180_CX>;
1278                                 operating-points-v2 = <&qup_opp_table>;
1279                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1280                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1281                                 interconnect-names = "qup-core", "qup-config";
1282                                 status = "disabled";
1283                         };
1284
1285                         i2c11: i2c@a94000 {
1286                                 compatible = "qcom,geni-i2c";
1287                                 reg = <0 0x00a94000 0 0x4000>;
1288                                 clock-names = "se";
1289                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1290                                 pinctrl-names = "default";
1291                                 pinctrl-0 = <&qup_i2c11_default>;
1292                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1293                                 #address-cells = <1>;
1294                                 #size-cells = <0>;
1295                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1296                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1297                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1298                                 interconnect-names = "qup-core", "qup-config",
1299                                                         "qup-memory";
1300                                 status = "disabled";
1301                         };
1302
1303                         spi11: spi@a94000 {
1304                                 compatible = "qcom,geni-spi";
1305                                 reg = <0 0x00a94000 0 0x4000>;
1306                                 clock-names = "se";
1307                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1308                                 pinctrl-names = "default";
1309                                 pinctrl-0 = <&qup_spi11_default>;
1310                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1311                                 #address-cells = <1>;
1312                                 #size-cells = <0>;
1313                                 power-domains = <&rpmhpd SC7180_CX>;
1314                                 operating-points-v2 = <&qup_opp_table>;
1315                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1316                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1317                                 interconnect-names = "qup-core", "qup-config";
1318                                 status = "disabled";
1319                         };
1320
1321                         uart11: serial@a94000 {
1322                                 compatible = "qcom,geni-uart";
1323                                 reg = <0 0x00a94000 0 0x4000>;
1324                                 clock-names = "se";
1325                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1326                                 pinctrl-names = "default";
1327                                 pinctrl-0 = <&qup_uart11_default>;
1328                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1329                                 power-domains = <&rpmhpd SC7180_CX>;
1330                                 operating-points-v2 = <&qup_opp_table>;
1331                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1332                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1333                                 interconnect-names = "qup-core", "qup-config";
1334                                 status = "disabled";
1335                         };
1336                 };
1337
1338                 config_noc: interconnect@1500000 {
1339                         compatible = "qcom,sc7180-config-noc";
1340                         reg = <0 0x01500000 0 0x28000>;
1341                         #interconnect-cells = <2>;
1342                         qcom,bcm-voters = <&apps_bcm_voter>;
1343                 };
1344
1345                 system_noc: interconnect@1620000 {
1346                         compatible = "qcom,sc7180-system-noc";
1347                         reg = <0 0x01620000 0 0x17080>;
1348                         #interconnect-cells = <2>;
1349                         qcom,bcm-voters = <&apps_bcm_voter>;
1350                 };
1351
1352                 mc_virt: interconnect@1638000 {
1353                         compatible = "qcom,sc7180-mc-virt";
1354                         reg = <0 0x01638000 0 0x1000>;
1355                         #interconnect-cells = <2>;
1356                         qcom,bcm-voters = <&apps_bcm_voter>;
1357                 };
1358
1359                 qup_virt: interconnect@1650000 {
1360                         compatible = "qcom,sc7180-qup-virt";
1361                         reg = <0 0x01650000 0 0x1000>;
1362                         #interconnect-cells = <2>;
1363                         qcom,bcm-voters = <&apps_bcm_voter>;
1364                 };
1365
1366                 aggre1_noc: interconnect@16e0000 {
1367                         compatible = "qcom,sc7180-aggre1-noc";
1368                         reg = <0 0x016e0000 0 0x15080>;
1369                         #interconnect-cells = <2>;
1370                         qcom,bcm-voters = <&apps_bcm_voter>;
1371                 };
1372
1373                 aggre2_noc: interconnect@1705000 {
1374                         compatible = "qcom,sc7180-aggre2-noc";
1375                         reg = <0 0x01705000 0 0x9000>;
1376                         #interconnect-cells = <2>;
1377                         qcom,bcm-voters = <&apps_bcm_voter>;
1378                 };
1379
1380                 compute_noc: interconnect@170e000 {
1381                         compatible = "qcom,sc7180-compute-noc";
1382                         reg = <0 0x0170e000 0 0x6000>;
1383                         #interconnect-cells = <2>;
1384                         qcom,bcm-voters = <&apps_bcm_voter>;
1385                 };
1386
1387                 mmss_noc: interconnect@1740000 {
1388                         compatible = "qcom,sc7180-mmss-noc";
1389                         reg = <0 0x01740000 0 0x1c100>;
1390                         #interconnect-cells = <2>;
1391                         qcom,bcm-voters = <&apps_bcm_voter>;
1392                 };
1393
1394                 ipa_virt: interconnect@1e00000 {
1395                         compatible = "qcom,sc7180-ipa-virt";
1396                         reg = <0 0x01e00000 0 0x1000>;
1397                         #interconnect-cells = <2>;
1398                         qcom,bcm-voters = <&apps_bcm_voter>;
1399                 };
1400
1401                 ipa: ipa@1e40000 {
1402                         compatible = "qcom,sc7180-ipa";
1403
1404                         iommus = <&apps_smmu 0x440 0x3>;
1405                         reg = <0 0x1e40000 0 0x7000>,
1406                               <0 0x1e47000 0 0x2000>,
1407                               <0 0x1e04000 0 0x2c000>;
1408                         reg-names = "ipa-reg",
1409                                     "ipa-shared",
1410                                     "gsi";
1411
1412                         interrupts-extended = <&intc 0 311 IRQ_TYPE_EDGE_RISING>,
1413                                               <&intc 0 432 IRQ_TYPE_LEVEL_HIGH>,
1414                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1415                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1416                         interrupt-names = "ipa",
1417                                           "gsi",
1418                                           "ipa-clock-query",
1419                                           "ipa-setup-ready";
1420
1421                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1422                         clock-names = "core";
1423
1424                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1425                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1426                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1427                         interconnect-names = "memory",
1428                                              "imem",
1429                                              "config";
1430
1431                         qcom,smem-states = <&ipa_smp2p_out 0>,
1432                                            <&ipa_smp2p_out 1>;
1433                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1434                                                 "ipa-clock-enabled";
1435
1436                         modem-remoteproc = <&remoteproc_mpss>;
1437
1438                         status = "disabled";
1439                 };
1440
1441                 tcsr_mutex_regs: syscon@1f40000 {
1442                         compatible = "syscon";
1443                         reg = <0 0x01f40000 0 0x40000>;
1444                 };
1445
1446                 tcsr_regs: syscon@1fc0000 {
1447                         compatible = "syscon";
1448                         reg = <0 0x01fc0000 0 0x40000>;
1449                 };
1450
1451                 tlmm: pinctrl@3500000 {
1452                         compatible = "qcom,sc7180-pinctrl";
1453                         reg = <0 0x03500000 0 0x300000>,
1454                               <0 0x03900000 0 0x300000>,
1455                               <0 0x03d00000 0 0x300000>;
1456                         reg-names = "west", "north", "south";
1457                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1458                         gpio-controller;
1459                         #gpio-cells = <2>;
1460                         interrupt-controller;
1461                         #interrupt-cells = <2>;
1462                         gpio-ranges = <&tlmm 0 0 120>;
1463                         wakeup-parent = <&pdc>;
1464
1465                         dp_hot_plug_det: dp-hot-plug-det {
1466                                 pinmux {
1467                                         pins = "gpio117";
1468                                         function = "dp_hot";
1469                                 };
1470
1471                                 pinconf {
1472                                         pins = "gpio117";
1473                                         bias-disable;
1474                                         input-enable;
1475                                 };
1476                         };
1477
1478                         qspi_clk: qspi-clk {
1479                                 pinmux {
1480                                         pins = "gpio63";
1481                                         function = "qspi_clk";
1482                                 };
1483                         };
1484
1485                         qspi_cs0: qspi-cs0 {
1486                                 pinmux {
1487                                         pins = "gpio68";
1488                                         function = "qspi_cs";
1489                                 };
1490                         };
1491
1492                         qspi_cs1: qspi-cs1 {
1493                                 pinmux {
1494                                         pins = "gpio72";
1495                                         function = "qspi_cs";
1496                                 };
1497                         };
1498
1499                         qspi_data01: qspi-data01 {
1500                                 pinmux-data {
1501                                         pins = "gpio64", "gpio65";
1502                                         function = "qspi_data";
1503                                 };
1504                         };
1505
1506                         qspi_data12: qspi-data12 {
1507                                 pinmux-data {
1508                                         pins = "gpio66", "gpio67";
1509                                         function = "qspi_data";
1510                                 };
1511                         };
1512
1513                         qup_i2c0_default: qup-i2c0-default {
1514                                 pinmux {
1515                                         pins = "gpio34", "gpio35";
1516                                         function = "qup00";
1517                                 };
1518                         };
1519
1520                         qup_i2c1_default: qup-i2c1-default {
1521                                 pinmux {
1522                                         pins = "gpio0", "gpio1";
1523                                         function = "qup01";
1524                                 };
1525                         };
1526
1527                         qup_i2c2_default: qup-i2c2-default {
1528                                 pinmux {
1529                                         pins = "gpio15", "gpio16";
1530                                         function = "qup02_i2c";
1531                                 };
1532                         };
1533
1534                         qup_i2c3_default: qup-i2c3-default {
1535                                 pinmux {
1536                                         pins = "gpio38", "gpio39";
1537                                         function = "qup03";
1538                                 };
1539                         };
1540
1541                         qup_i2c4_default: qup-i2c4-default {
1542                                 pinmux {
1543                                         pins = "gpio115", "gpio116";
1544                                         function = "qup04_i2c";
1545                                 };
1546                         };
1547
1548                         qup_i2c5_default: qup-i2c5-default {
1549                                 pinmux {
1550                                         pins = "gpio25", "gpio26";
1551                                         function = "qup05";
1552                                 };
1553                         };
1554
1555                         qup_i2c6_default: qup-i2c6-default {
1556                                 pinmux {
1557                                         pins = "gpio59", "gpio60";
1558                                         function = "qup10";
1559                                 };
1560                         };
1561
1562                         qup_i2c7_default: qup-i2c7-default {
1563                                 pinmux {
1564                                         pins = "gpio6", "gpio7";
1565                                         function = "qup11_i2c";
1566                                 };
1567                         };
1568
1569                         qup_i2c8_default: qup-i2c8-default {
1570                                 pinmux {
1571                                         pins = "gpio42", "gpio43";
1572                                         function = "qup12";
1573                                 };
1574                         };
1575
1576                         qup_i2c9_default: qup-i2c9-default {
1577                                 pinmux {
1578                                         pins = "gpio46", "gpio47";
1579                                         function = "qup13_i2c";
1580                                 };
1581                         };
1582
1583                         qup_i2c10_default: qup-i2c10-default {
1584                                 pinmux {
1585                                         pins = "gpio86", "gpio87";
1586                                         function = "qup14";
1587                                 };
1588                         };
1589
1590                         qup_i2c11_default: qup-i2c11-default {
1591                                 pinmux {
1592                                         pins = "gpio53", "gpio54";
1593                                         function = "qup15";
1594                                 };
1595                         };
1596
1597                         qup_spi0_default: qup-spi0-default {
1598                                 pinmux {
1599                                         pins = "gpio34", "gpio35",
1600                                                "gpio36", "gpio37";
1601                                         function = "qup00";
1602                                 };
1603                         };
1604
1605                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1606                                 pinmux {
1607                                         pins = "gpio34", "gpio35",
1608                                                "gpio36";
1609                                         function = "qup00";
1610                                 };
1611
1612                                 pinmux-cs {
1613                                         pins = "gpio37";
1614                                         function = "gpio";
1615                                 };
1616                         };
1617
1618                         qup_spi1_default: qup-spi1-default {
1619                                 pinmux {
1620                                         pins = "gpio0", "gpio1",
1621                                                "gpio2", "gpio3";
1622                                         function = "qup01";
1623                                 };
1624                         };
1625
1626                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1627                                 pinmux {
1628                                         pins = "gpio0", "gpio1",
1629                                                "gpio2";
1630                                         function = "qup01";
1631                                 };
1632
1633                                 pinmux-cs {
1634                                         pins = "gpio3";
1635                                         function = "gpio";
1636                                 };
1637                         };
1638
1639                         qup_spi3_default: qup-spi3-default {
1640                                 pinmux {
1641                                         pins = "gpio38", "gpio39",
1642                                                "gpio40", "gpio41";
1643                                         function = "qup03";
1644                                 };
1645                         };
1646
1647                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1648                                 pinmux {
1649                                         pins = "gpio38", "gpio39",
1650                                                "gpio40";
1651                                         function = "qup03";
1652                                 };
1653
1654                                 pinmux-cs {
1655                                         pins = "gpio41";
1656                                         function = "gpio";
1657                                 };
1658                         };
1659
1660                         qup_spi5_default: qup-spi5-default {
1661                                 pinmux {
1662                                         pins = "gpio25", "gpio26",
1663                                                "gpio27", "gpio28";
1664                                         function = "qup05";
1665                                 };
1666                         };
1667
1668                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1669                                 pinmux {
1670                                         pins = "gpio25", "gpio26",
1671                                                "gpio27";
1672                                         function = "qup05";
1673                                 };
1674
1675                                 pinmux-cs {
1676                                         pins = "gpio28";
1677                                         function = "gpio";
1678                                 };
1679                         };
1680
1681                         qup_spi6_default: qup-spi6-default {
1682                                 pinmux {
1683                                         pins = "gpio59", "gpio60",
1684                                                "gpio61", "gpio62";
1685                                         function = "qup10";
1686                                 };
1687                         };
1688
1689                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1690                                 pinmux {
1691                                         pins = "gpio59", "gpio60",
1692                                                "gpio61";
1693                                         function = "qup10";
1694                                 };
1695
1696                                 pinmux-cs {
1697                                         pins = "gpio62";
1698                                         function = "gpio";
1699                                 };
1700                         };
1701
1702                         qup_spi8_default: qup-spi8-default {
1703                                 pinmux {
1704                                         pins = "gpio42", "gpio43",
1705                                                "gpio44", "gpio45";
1706                                         function = "qup12";
1707                                 };
1708                         };
1709
1710                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1711                                 pinmux {
1712                                         pins = "gpio42", "gpio43",
1713                                                "gpio44";
1714                                         function = "qup12";
1715                                 };
1716
1717                                 pinmux-cs {
1718                                         pins = "gpio45";
1719                                         function = "gpio";
1720                                 };
1721                         };
1722
1723                         qup_spi10_default: qup-spi10-default {
1724                                 pinmux {
1725                                         pins = "gpio86", "gpio87",
1726                                                "gpio88", "gpio89";
1727                                         function = "qup14";
1728                                 };
1729                         };
1730
1731                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1732                                 pinmux {
1733                                         pins = "gpio86", "gpio87",
1734                                                "gpio88";
1735                                         function = "qup14";
1736                                 };
1737
1738                                 pinmux-cs {
1739                                         pins = "gpio89";
1740                                         function = "gpio";
1741                                 };
1742                         };
1743
1744                         qup_spi11_default: qup-spi11-default {
1745                                 pinmux {
1746                                         pins = "gpio53", "gpio54",
1747                                                "gpio55", "gpio56";
1748                                         function = "qup15";
1749                                 };
1750                         };
1751
1752                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1753                                 pinmux {
1754                                         pins = "gpio53", "gpio54",
1755                                                "gpio55";
1756                                         function = "qup15";
1757                                 };
1758
1759                                 pinmux-cs {
1760                                         pins = "gpio56";
1761                                         function = "gpio";
1762                                 };
1763                         };
1764
1765                         qup_uart0_default: qup-uart0-default {
1766                                 pinmux {
1767                                         pins = "gpio34", "gpio35",
1768                                                "gpio36", "gpio37";
1769                                         function = "qup00";
1770                                 };
1771                         };
1772
1773                         qup_uart1_default: qup-uart1-default {
1774                                 pinmux {
1775                                         pins = "gpio0", "gpio1",
1776                                                "gpio2", "gpio3";
1777                                         function = "qup01";
1778                                 };
1779                         };
1780
1781                         qup_uart2_default: qup-uart2-default {
1782                                 pinmux {
1783                                         pins = "gpio15", "gpio16";
1784                                         function = "qup02_uart";
1785                                 };
1786                         };
1787
1788                         qup_uart3_default: qup-uart3-default {
1789                                 pinmux {
1790                                         pins = "gpio38", "gpio39",
1791                                                "gpio40", "gpio41";
1792                                         function = "qup03";
1793                                 };
1794                         };
1795
1796                         qup_uart4_default: qup-uart4-default {
1797                                 pinmux {
1798                                         pins = "gpio115", "gpio116";
1799                                         function = "qup04_uart";
1800                                 };
1801                         };
1802
1803                         qup_uart5_default: qup-uart5-default {
1804                                 pinmux {
1805                                         pins = "gpio25", "gpio26",
1806                                                "gpio27", "gpio28";
1807                                         function = "qup05";
1808                                 };
1809                         };
1810
1811                         qup_uart6_default: qup-uart6-default {
1812                                 pinmux {
1813                                         pins = "gpio59", "gpio60",
1814                                                "gpio61", "gpio62";
1815                                         function = "qup10";
1816                                 };
1817                         };
1818
1819                         qup_uart7_default: qup-uart7-default {
1820                                 pinmux {
1821                                         pins = "gpio6", "gpio7";
1822                                         function = "qup11_uart";
1823                                 };
1824                         };
1825
1826                         qup_uart8_default: qup-uart8-default {
1827                                 pinmux {
1828                                         pins = "gpio44", "gpio45";
1829                                         function = "qup12";
1830                                 };
1831                         };
1832
1833                         qup_uart9_default: qup-uart9-default {
1834                                 pinmux {
1835                                         pins = "gpio46", "gpio47";
1836                                         function = "qup13_uart";
1837                                 };
1838                         };
1839
1840                         qup_uart10_default: qup-uart10-default {
1841                                 pinmux {
1842                                         pins = "gpio86", "gpio87",
1843                                                "gpio88", "gpio89";
1844                                         function = "qup14";
1845                                 };
1846                         };
1847
1848                         qup_uart11_default: qup-uart11-default {
1849                                 pinmux {
1850                                         pins = "gpio53", "gpio54",
1851                                                "gpio55", "gpio56";
1852                                         function = "qup15";
1853                                 };
1854                         };
1855
1856                         sdc1_on: sdc1-on {
1857                                 pinconf-clk {
1858                                         pins = "sdc1_clk";
1859                                         bias-disable;
1860                                         drive-strength = <16>;
1861                                 };
1862
1863                                 pinconf-cmd {
1864                                         pins = "sdc1_cmd";
1865                                         bias-pull-up;
1866                                         drive-strength = <10>;
1867                                 };
1868
1869                                 pinconf-data {
1870                                         pins = "sdc1_data";
1871                                         bias-pull-up;
1872                                         drive-strength = <10>;
1873                                 };
1874
1875                                 pinconf-rclk {
1876                                         pins = "sdc1_rclk";
1877                                         bias-pull-down;
1878                                 };
1879                         };
1880
1881                         sdc1_off: sdc1-off {
1882                                 pinconf-clk {
1883                                         pins = "sdc1_clk";
1884                                         bias-disable;
1885                                         drive-strength = <2>;
1886                                 };
1887
1888                                 pinconf-cmd {
1889                                         pins = "sdc1_cmd";
1890                                         bias-pull-up;
1891                                         drive-strength = <2>;
1892                                 };
1893
1894                                 pinconf-data {
1895                                         pins = "sdc1_data";
1896                                         bias-pull-up;
1897                                         drive-strength = <2>;
1898                                 };
1899
1900                                 pinconf-rclk {
1901                                         pins = "sdc1_rclk";
1902                                         bias-pull-down;
1903                                 };
1904                         };
1905
1906                         sdc2_on: sdc2-on {
1907                                 pinconf-clk {
1908                                         pins = "sdc2_clk";
1909                                         bias-disable;
1910                                         drive-strength = <16>;
1911                                 };
1912
1913                                 pinconf-cmd {
1914                                         pins = "sdc2_cmd";
1915                                         bias-pull-up;
1916                                         drive-strength = <10>;
1917                                 };
1918
1919                                 pinconf-data {
1920                                         pins = "sdc2_data";
1921                                         bias-pull-up;
1922                                         drive-strength = <10>;
1923                                 };
1924
1925                                 pinconf-sd-cd {
1926                                         pins = "gpio69";
1927                                         bias-pull-up;
1928                                         drive-strength = <2>;
1929                                 };
1930                         };
1931
1932                         sdc2_off: sdc2-off {
1933                                 pinconf-clk {
1934                                         pins = "sdc2_clk";
1935                                         bias-disable;
1936                                         drive-strength = <2>;
1937                                 };
1938
1939                                 pinconf-cmd {
1940                                         pins = "sdc2_cmd";
1941                                         bias-pull-up;
1942                                         drive-strength = <2>;
1943                                 };
1944
1945                                 pinconf-data {
1946                                         pins = "sdc2_data";
1947                                         bias-pull-up;
1948                                         drive-strength = <2>;
1949                                 };
1950
1951                                 pinconf-sd-cd {
1952                                         pins = "gpio69";
1953                                         bias-disable;
1954                                         drive-strength = <2>;
1955                                 };
1956                         };
1957                 };
1958
1959                 remoteproc_mpss: remoteproc@4080000 {
1960                         compatible = "qcom,sc7180-mpss-pas";
1961                         reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1962                         reg-names = "qdsp6", "rmb";
1963
1964                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
1965                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1966                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
1967                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
1968                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
1969                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
1970                         interrupt-names = "wdog", "fatal", "ready", "handover",
1971                                           "stop-ack", "shutdown-ack";
1972
1973                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
1974                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
1975                                  <&gcc GCC_MSS_NAV_AXI_CLK>,
1976                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
1977                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
1978                                  <&rpmhcc RPMH_CXO_CLK>;
1979                         clock-names = "iface", "bus", "nav", "snoc_axi",
1980                                       "mnoc_axi", "xo";
1981
1982                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
1983                                         <&rpmhpd SC7180_CX>,
1984                                         <&rpmhpd SC7180_MX>,
1985                                         <&rpmhpd SC7180_MSS>;
1986                         power-domain-names = "load_state", "cx", "mx", "mss";
1987
1988                         memory-region = <&mpss_mem>;
1989
1990                         qcom,smem-states = <&modem_smp2p_out 0>;
1991                         qcom,smem-state-names = "stop";
1992
1993                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
1994                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
1995                         reset-names = "mss_restart", "pdc_reset";
1996
1997                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
1998                         qcom,spare-regs = <&tcsr_regs 0xb3e4>;
1999
2000                         status = "disabled";
2001
2002                         glink-edge {
2003                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2004                                 label = "modem";
2005                                 qcom,remote-pid = <1>;
2006                                 mboxes = <&apss_shared 12>;
2007                         };
2008                 };
2009
2010                 gpu: gpu@5000000 {
2011                         compatible = "qcom,adreno-618.0", "qcom,adreno";
2012                         #stream-id-cells = <16>;
2013                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2014                                 <0 0x05061000 0 0x800>;
2015                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2016                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2017                         iommus = <&adreno_smmu 0>;
2018                         operating-points-v2 = <&gpu_opp_table>;
2019                         qcom,gmu = <&gmu>;
2020
2021                         #cooling-cells = <2>;
2022
2023                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2024                         interconnect-names = "gfx-mem";
2025
2026                         gpu_opp_table: opp-table {
2027                                 compatible = "operating-points-v2";
2028
2029                                 opp-800000000 {
2030                                         opp-hz = /bits/ 64 <800000000>;
2031                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2032                                         opp-peak-kBps = <8532000>;
2033                                 };
2034
2035                                 opp-650000000 {
2036                                         opp-hz = /bits/ 64 <650000000>;
2037                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2038                                         opp-peak-kBps = <7216000>;
2039                                 };
2040
2041                                 opp-565000000 {
2042                                         opp-hz = /bits/ 64 <565000000>;
2043                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2044                                         opp-peak-kBps = <5412000>;
2045                                 };
2046
2047                                 opp-430000000 {
2048                                         opp-hz = /bits/ 64 <430000000>;
2049                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2050                                         opp-peak-kBps = <5412000>;
2051                                 };
2052
2053                                 opp-355000000 {
2054                                         opp-hz = /bits/ 64 <355000000>;
2055                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2056                                         opp-peak-kBps = <3072000>;
2057                                 };
2058
2059                                 opp-267000000 {
2060                                         opp-hz = /bits/ 64 <267000000>;
2061                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2062                                         opp-peak-kBps = <3072000>;
2063                                 };
2064
2065                                 opp-180000000 {
2066                                         opp-hz = /bits/ 64 <180000000>;
2067                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2068                                         opp-peak-kBps = <1804000>;
2069                                 };
2070                         };
2071                 };
2072
2073                 adreno_smmu: iommu@5040000 {
2074                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2075                         reg = <0 0x05040000 0 0x10000>;
2076                         #iommu-cells = <1>;
2077                         #global-interrupts = <2>;
2078                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2079                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2080                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2081                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2082                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2083                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2084                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2085                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2086                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2087                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2088
2089                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2090                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2091                         clock-names = "bus", "iface";
2092
2093                         power-domains = <&gpucc CX_GDSC>;
2094                 };
2095
2096                 gmu: gmu@506a000 {
2097                         compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2098                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2099                                 <0 0x0b490000 0 0x10000>;
2100                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2101                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2102                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2103                         interrupt-names = "hfi", "gmu";
2104                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2105                                <&gpucc GPU_CC_CXO_CLK>,
2106                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2107                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2108                         clock-names = "gmu", "cxo", "axi", "memnoc";
2109                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2110                         power-domain-names = "cx", "gx";
2111                         iommus = <&adreno_smmu 5>;
2112                         operating-points-v2 = <&gmu_opp_table>;
2113
2114                         gmu_opp_table: opp-table {
2115                                 compatible = "operating-points-v2";
2116
2117                                 opp-200000000 {
2118                                         opp-hz = /bits/ 64 <200000000>;
2119                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2120                                 };
2121                         };
2122                 };
2123
2124                 gpucc: clock-controller@5090000 {
2125                         compatible = "qcom,sc7180-gpucc";
2126                         reg = <0 0x05090000 0 0x9000>;
2127                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2128                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2129                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2130                         clock-names = "bi_tcxo",
2131                                       "gcc_gpu_gpll0_clk_src",
2132                                       "gcc_gpu_gpll0_div_clk_src";
2133                         #clock-cells = <1>;
2134                         #reset-cells = <1>;
2135                         #power-domain-cells = <1>;
2136                 };
2137
2138                 stm@6002000 {
2139                         compatible = "arm,coresight-stm", "arm,primecell";
2140                         reg = <0 0x06002000 0 0x1000>,
2141                               <0 0x16280000 0 0x180000>;
2142                         reg-names = "stm-base", "stm-stimulus-base";
2143
2144                         clocks = <&aoss_qmp>;
2145                         clock-names = "apb_pclk";
2146
2147                         out-ports {
2148                                 port {
2149                                         stm_out: endpoint {
2150                                                 remote-endpoint = <&funnel0_in7>;
2151                                         };
2152                                 };
2153                         };
2154                 };
2155
2156                 funnel@6041000 {
2157                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2158                         reg = <0 0x06041000 0 0x1000>;
2159
2160                         clocks = <&aoss_qmp>;
2161                         clock-names = "apb_pclk";
2162
2163                         out-ports {
2164                                 port {
2165                                         funnel0_out: endpoint {
2166                                                 remote-endpoint = <&merge_funnel_in0>;
2167                                         };
2168                                 };
2169                         };
2170
2171                         in-ports {
2172                                 #address-cells = <1>;
2173                                 #size-cells = <0>;
2174
2175                                 port@7 {
2176                                         reg = <7>;
2177                                         funnel0_in7: endpoint {
2178                                                 remote-endpoint = <&stm_out>;
2179                                         };
2180                                 };
2181                         };
2182                 };
2183
2184                 funnel@6042000 {
2185                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2186                         reg = <0 0x06042000 0 0x1000>;
2187
2188                         clocks = <&aoss_qmp>;
2189                         clock-names = "apb_pclk";
2190
2191                         out-ports {
2192                                 port {
2193                                         funnel1_out: endpoint {
2194                                                 remote-endpoint = <&merge_funnel_in1>;
2195                                         };
2196                                 };
2197                         };
2198
2199                         in-ports {
2200                                 #address-cells = <1>;
2201                                 #size-cells = <0>;
2202
2203                                 port@4 {
2204                                         reg = <4>;
2205                                         funnel1_in4: endpoint {
2206                                                 remote-endpoint = <&apss_merge_funnel_out>;
2207                                         };
2208                                 };
2209                         };
2210                 };
2211
2212                 funnel@6045000 {
2213                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2214                         reg = <0 0x06045000 0 0x1000>;
2215
2216                         clocks = <&aoss_qmp>;
2217                         clock-names = "apb_pclk";
2218
2219                         out-ports {
2220                                 port {
2221                                         merge_funnel_out: endpoint {
2222                                                 remote-endpoint = <&swao_funnel_in>;
2223                                         };
2224                                 };
2225                         };
2226
2227                         in-ports {
2228                                 #address-cells = <1>;
2229                                 #size-cells = <0>;
2230
2231                                 port@0 {
2232                                         reg = <0>;
2233                                         merge_funnel_in0: endpoint {
2234                                                 remote-endpoint = <&funnel0_out>;
2235                                         };
2236                                 };
2237
2238                                 port@1 {
2239                                         reg = <1>;
2240                                         merge_funnel_in1: endpoint {
2241                                                 remote-endpoint = <&funnel1_out>;
2242                                         };
2243                                 };
2244                         };
2245                 };
2246
2247                 replicator@6046000 {
2248                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2249                         reg = <0 0x06046000 0 0x1000>;
2250
2251                         clocks = <&aoss_qmp>;
2252                         clock-names = "apb_pclk";
2253
2254                         out-ports {
2255                                 port {
2256                                         replicator_out: endpoint {
2257                                                 remote-endpoint = <&etr_in>;
2258                                         };
2259                                 };
2260                         };
2261
2262                         in-ports {
2263                                 port {
2264                                         replicator_in: endpoint {
2265                                                 remote-endpoint = <&swao_replicator_out>;
2266                                         };
2267                                 };
2268                         };
2269                 };
2270
2271                 etr@6048000 {
2272                         compatible = "arm,coresight-tmc", "arm,primecell";
2273                         reg = <0 0x06048000 0 0x1000>;
2274                         iommus = <&apps_smmu 0x04a0 0x20>;
2275
2276                         clocks = <&aoss_qmp>;
2277                         clock-names = "apb_pclk";
2278                         arm,scatter-gather;
2279
2280                         in-ports {
2281                                 port {
2282                                         etr_in: endpoint {
2283                                                 remote-endpoint = <&replicator_out>;
2284                                         };
2285                                 };
2286                         };
2287                 };
2288
2289                 funnel@6b04000 {
2290                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2291                         reg = <0 0x06b04000 0 0x1000>;
2292
2293                         clocks = <&aoss_qmp>;
2294                         clock-names = "apb_pclk";
2295
2296                         out-ports {
2297                                 port {
2298                                         swao_funnel_out: endpoint {
2299                                                 remote-endpoint = <&etf_in>;
2300                                         };
2301                                 };
2302                         };
2303
2304                         in-ports {
2305                                 #address-cells = <1>;
2306                                 #size-cells = <0>;
2307
2308                                 port@7 {
2309                                         reg = <7>;
2310                                         swao_funnel_in: endpoint {
2311                                                 remote-endpoint = <&merge_funnel_out>;
2312                                         };
2313                                 };
2314                         };
2315                 };
2316
2317                 etf@6b05000 {
2318                         compatible = "arm,coresight-tmc", "arm,primecell";
2319                         reg = <0 0x06b05000 0 0x1000>;
2320
2321                         clocks = <&aoss_qmp>;
2322                         clock-names = "apb_pclk";
2323
2324                         out-ports {
2325                                 port {
2326                                         etf_out: endpoint {
2327                                                 remote-endpoint = <&swao_replicator_in>;
2328                                         };
2329                                 };
2330                         };
2331
2332                         in-ports {
2333                                 port {
2334                                         etf_in: endpoint {
2335                                                 remote-endpoint = <&swao_funnel_out>;
2336                                         };
2337                                 };
2338                         };
2339                 };
2340
2341                 replicator@6b06000 {
2342                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2343                         reg = <0 0x06b06000 0 0x1000>;
2344
2345                         clocks = <&aoss_qmp>;
2346                         clock-names = "apb_pclk";
2347                         qcom,replicator-loses-context;
2348
2349                         out-ports {
2350                                 port {
2351                                         swao_replicator_out: endpoint {
2352                                                 remote-endpoint = <&replicator_in>;
2353                                         };
2354                                 };
2355                         };
2356
2357                         in-ports {
2358                                 port {
2359                                         swao_replicator_in: endpoint {
2360                                                 remote-endpoint = <&etf_out>;
2361                                         };
2362                                 };
2363                         };
2364                 };
2365
2366                 etm@7040000 {
2367                         compatible = "arm,coresight-etm4x", "arm,primecell";
2368                         reg = <0 0x07040000 0 0x1000>;
2369
2370                         cpu = <&CPU0>;
2371
2372                         clocks = <&aoss_qmp>;
2373                         clock-names = "apb_pclk";
2374                         arm,coresight-loses-context-with-cpu;
2375                         qcom,skip-power-up;
2376
2377                         out-ports {
2378                                 port {
2379                                         etm0_out: endpoint {
2380                                                 remote-endpoint = <&apss_funnel_in0>;
2381                                         };
2382                                 };
2383                         };
2384                 };
2385
2386                 etm@7140000 {
2387                         compatible = "arm,coresight-etm4x", "arm,primecell";
2388                         reg = <0 0x07140000 0 0x1000>;
2389
2390                         cpu = <&CPU1>;
2391
2392                         clocks = <&aoss_qmp>;
2393                         clock-names = "apb_pclk";
2394                         arm,coresight-loses-context-with-cpu;
2395                         qcom,skip-power-up;
2396
2397                         out-ports {
2398                                 port {
2399                                         etm1_out: endpoint {
2400                                                 remote-endpoint = <&apss_funnel_in1>;
2401                                         };
2402                                 };
2403                         };
2404                 };
2405
2406                 etm@7240000 {
2407                         compatible = "arm,coresight-etm4x", "arm,primecell";
2408                         reg = <0 0x07240000 0 0x1000>;
2409
2410                         cpu = <&CPU2>;
2411
2412                         clocks = <&aoss_qmp>;
2413                         clock-names = "apb_pclk";
2414                         arm,coresight-loses-context-with-cpu;
2415                         qcom,skip-power-up;
2416
2417                         out-ports {
2418                                 port {
2419                                         etm2_out: endpoint {
2420                                                 remote-endpoint = <&apss_funnel_in2>;
2421                                         };
2422                                 };
2423                         };
2424                 };
2425
2426                 etm@7340000 {
2427                         compatible = "arm,coresight-etm4x", "arm,primecell";
2428                         reg = <0 0x07340000 0 0x1000>;
2429
2430                         cpu = <&CPU3>;
2431
2432                         clocks = <&aoss_qmp>;
2433                         clock-names = "apb_pclk";
2434                         arm,coresight-loses-context-with-cpu;
2435                         qcom,skip-power-up;
2436
2437                         out-ports {
2438                                 port {
2439                                         etm3_out: endpoint {
2440                                                 remote-endpoint = <&apss_funnel_in3>;
2441                                         };
2442                                 };
2443                         };
2444                 };
2445
2446                 etm@7440000 {
2447                         compatible = "arm,coresight-etm4x", "arm,primecell";
2448                         reg = <0 0x07440000 0 0x1000>;
2449
2450                         cpu = <&CPU4>;
2451
2452                         clocks = <&aoss_qmp>;
2453                         clock-names = "apb_pclk";
2454                         arm,coresight-loses-context-with-cpu;
2455                         qcom,skip-power-up;
2456
2457                         out-ports {
2458                                 port {
2459                                         etm4_out: endpoint {
2460                                                 remote-endpoint = <&apss_funnel_in4>;
2461                                         };
2462                                 };
2463                         };
2464                 };
2465
2466                 etm@7540000 {
2467                         compatible = "arm,coresight-etm4x", "arm,primecell";
2468                         reg = <0 0x07540000 0 0x1000>;
2469
2470                         cpu = <&CPU5>;
2471
2472                         clocks = <&aoss_qmp>;
2473                         clock-names = "apb_pclk";
2474                         arm,coresight-loses-context-with-cpu;
2475                         qcom,skip-power-up;
2476
2477                         out-ports {
2478                                 port {
2479                                         etm5_out: endpoint {
2480                                                 remote-endpoint = <&apss_funnel_in5>;
2481                                         };
2482                                 };
2483                         };
2484                 };
2485
2486                 etm@7640000 {
2487                         compatible = "arm,coresight-etm4x", "arm,primecell";
2488                         reg = <0 0x07640000 0 0x1000>;
2489
2490                         cpu = <&CPU6>;
2491
2492                         clocks = <&aoss_qmp>;
2493                         clock-names = "apb_pclk";
2494                         arm,coresight-loses-context-with-cpu;
2495                         qcom,skip-power-up;
2496
2497                         out-ports {
2498                                 port {
2499                                         etm6_out: endpoint {
2500                                                 remote-endpoint = <&apss_funnel_in6>;
2501                                         };
2502                                 };
2503                         };
2504                 };
2505
2506                 etm@7740000 {
2507                         compatible = "arm,coresight-etm4x", "arm,primecell";
2508                         reg = <0 0x07740000 0 0x1000>;
2509
2510                         cpu = <&CPU7>;
2511
2512                         clocks = <&aoss_qmp>;
2513                         clock-names = "apb_pclk";
2514                         arm,coresight-loses-context-with-cpu;
2515                         qcom,skip-power-up;
2516
2517                         out-ports {
2518                                 port {
2519                                         etm7_out: endpoint {
2520                                                 remote-endpoint = <&apss_funnel_in7>;
2521                                         };
2522                                 };
2523                         };
2524                 };
2525
2526                 funnel@7800000 { /* APSS Funnel */
2527                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2528                         reg = <0 0x07800000 0 0x1000>;
2529
2530                         clocks = <&aoss_qmp>;
2531                         clock-names = "apb_pclk";
2532
2533                         out-ports {
2534                                 port {
2535                                         apss_funnel_out: endpoint {
2536                                                 remote-endpoint = <&apss_merge_funnel_in>;
2537                                         };
2538                                 };
2539                         };
2540
2541                         in-ports {
2542                                 #address-cells = <1>;
2543                                 #size-cells = <0>;
2544
2545                                 port@0 {
2546                                         reg = <0>;
2547                                         apss_funnel_in0: endpoint {
2548                                                 remote-endpoint = <&etm0_out>;
2549                                         };
2550                                 };
2551
2552                                 port@1 {
2553                                         reg = <1>;
2554                                         apss_funnel_in1: endpoint {
2555                                                 remote-endpoint = <&etm1_out>;
2556                                         };
2557                                 };
2558
2559                                 port@2 {
2560                                         reg = <2>;
2561                                         apss_funnel_in2: endpoint {
2562                                                 remote-endpoint = <&etm2_out>;
2563                                         };
2564                                 };
2565
2566                                 port@3 {
2567                                         reg = <3>;
2568                                         apss_funnel_in3: endpoint {
2569                                                 remote-endpoint = <&etm3_out>;
2570                                         };
2571                                 };
2572
2573                                 port@4 {
2574                                         reg = <4>;
2575                                         apss_funnel_in4: endpoint {
2576                                                 remote-endpoint = <&etm4_out>;
2577                                         };
2578                                 };
2579
2580                                 port@5 {
2581                                         reg = <5>;
2582                                         apss_funnel_in5: endpoint {
2583                                                 remote-endpoint = <&etm5_out>;
2584                                         };
2585                                 };
2586
2587                                 port@6 {
2588                                         reg = <6>;
2589                                         apss_funnel_in6: endpoint {
2590                                                 remote-endpoint = <&etm6_out>;
2591                                         };
2592                                 };
2593
2594                                 port@7 {
2595                                         reg = <7>;
2596                                         apss_funnel_in7: endpoint {
2597                                                 remote-endpoint = <&etm7_out>;
2598                                         };
2599                                 };
2600                         };
2601                 };
2602
2603                 funnel@7810000 {
2604                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2605                         reg = <0 0x07810000 0 0x1000>;
2606
2607                         clocks = <&aoss_qmp>;
2608                         clock-names = "apb_pclk";
2609
2610                         out-ports {
2611                                 port {
2612                                         apss_merge_funnel_out: endpoint {
2613                                                 remote-endpoint = <&funnel1_in4>;
2614                                         };
2615                                 };
2616                         };
2617
2618                         in-ports {
2619                                 port {
2620                                         apss_merge_funnel_in: endpoint {
2621                                                 remote-endpoint = <&apss_funnel_out>;
2622                                         };
2623                                 };
2624                         };
2625                 };
2626
2627                 sdhc_2: sdhci@8804000 {
2628                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2629                         reg = <0 0x08804000 0 0x1000>;
2630
2631                         iommus = <&apps_smmu 0x80 0>;
2632                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2633                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2634                         interrupt-names = "hc_irq", "pwr_irq";
2635
2636                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2637                                         <&gcc GCC_SDCC2_AHB_CLK>;
2638                         clock-names = "core", "iface";
2639
2640                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2641                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2642                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2643                         power-domains = <&rpmhpd SC7180_CX>;
2644                         operating-points-v2 = <&sdhc2_opp_table>;
2645
2646                         bus-width = <4>;
2647
2648                         status = "disabled";
2649
2650                         sdhc2_opp_table: sdhc2-opp-table {
2651                                 compatible = "operating-points-v2";
2652
2653                                 opp-100000000 {
2654                                         opp-hz = /bits/ 64 <100000000>;
2655                                         required-opps = <&rpmhpd_opp_low_svs>;
2656                                         opp-peak-kBps = <160000 100000>;
2657                                         opp-avg-kBps = <80000 50000>;
2658                                 };
2659
2660                                 opp-202000000 {
2661                                         opp-hz = /bits/ 64 <202000000>;
2662                                         required-opps = <&rpmhpd_opp_svs_l1>;
2663                                         opp-peak-kBps = <200000 120000>;
2664                                         opp-avg-kBps = <100000 60000>;
2665                                 };
2666                         };
2667                 };
2668
2669                 qspi_opp_table: qspi-opp-table {
2670                         compatible = "operating-points-v2";
2671
2672                         opp-75000000 {
2673                                 opp-hz = /bits/ 64 <75000000>;
2674                                 required-opps = <&rpmhpd_opp_low_svs>;
2675                         };
2676
2677                         opp-150000000 {
2678                                 opp-hz = /bits/ 64 <150000000>;
2679                                 required-opps = <&rpmhpd_opp_svs>;
2680                         };
2681
2682                         opp-300000000 {
2683                                 opp-hz = /bits/ 64 <300000000>;
2684                                 required-opps = <&rpmhpd_opp_nom>;
2685                         };
2686                 };
2687
2688                 qspi: spi@88dc000 {
2689                         compatible = "qcom,qspi-v1";
2690                         reg = <0 0x088dc000 0 0x600>;
2691                         #address-cells = <1>;
2692                         #size-cells = <0>;
2693                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2694                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2695                                  <&gcc GCC_QSPI_CORE_CLK>;
2696                         clock-names = "iface", "core";
2697                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2698                                         &config_noc SLAVE_QSPI_0 0>;
2699                         interconnect-names = "qspi-config";
2700                         power-domains = <&rpmhpd SC7180_CX>;
2701                         operating-points-v2 = <&qspi_opp_table>;
2702                         status = "disabled";
2703                 };
2704
2705                 usb_1_hsphy: phy@88e3000 {
2706                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2707                         reg = <0 0x088e3000 0 0x400>;
2708                         status = "disabled";
2709                         #phy-cells = <0>;
2710                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2711                                  <&rpmhcc RPMH_CXO_CLK>;
2712                         clock-names = "cfg_ahb", "ref";
2713                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2714
2715                         nvmem-cells = <&qusb2p_hstx_trim>;
2716                 };
2717
2718                 usb_1_qmpphy: phy-wrapper@88e9000 {
2719                         compatible = "qcom,sc7180-qmp-usb3-phy";
2720                         reg = <0 0x088e9000 0 0x18c>,
2721                               <0 0x088e8000 0 0x38>;
2722                         reg-names = "reg-base", "dp_com";
2723                         status = "disabled";
2724                         #clock-cells = <1>;
2725                         #address-cells = <2>;
2726                         #size-cells = <2>;
2727                         ranges;
2728
2729                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2730                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2731                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2732                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2733                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2734
2735                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2736                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2737                         reset-names = "phy", "common";
2738
2739                         usb_1_ssphy: phy@88e9200 {
2740                                 reg = <0 0x088e9200 0 0x128>,
2741                                       <0 0x088e9400 0 0x200>,
2742                                       <0 0x088e9c00 0 0x218>,
2743                                       <0 0x088e9600 0 0x128>,
2744                                       <0 0x088e9800 0 0x200>,
2745                                       <0 0x088e9a00 0 0x18>;
2746                                 #clock-cells = <0>;
2747                                 #phy-cells = <0>;
2748                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2749                                 clock-names = "pipe0";
2750                                 clock-output-names = "usb3_phy_pipe_clk_src";
2751                         };
2752                 };
2753
2754                 dc_noc: interconnect@9160000 {
2755                         compatible = "qcom,sc7180-dc-noc";
2756                         reg = <0 0x09160000 0 0x03200>;
2757                         #interconnect-cells = <2>;
2758                         qcom,bcm-voters = <&apps_bcm_voter>;
2759                 };
2760
2761                 system-cache-controller@9200000 {
2762                         compatible = "qcom,sc7180-llcc";
2763                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2764                         reg-names = "llcc_base", "llcc_broadcast_base";
2765                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2766                 };
2767
2768                 gem_noc: interconnect@9680000 {
2769                         compatible = "qcom,sc7180-gem-noc";
2770                         reg = <0 0x09680000 0 0x3e200>;
2771                         #interconnect-cells = <2>;
2772                         qcom,bcm-voters = <&apps_bcm_voter>;
2773                 };
2774
2775                 npu_noc: interconnect@9990000 {
2776                         compatible = "qcom,sc7180-npu-noc";
2777                         reg = <0 0x09990000 0 0x1600>;
2778                         #interconnect-cells = <2>;
2779                         qcom,bcm-voters = <&apps_bcm_voter>;
2780                 };
2781
2782                 usb_1: usb@a6f8800 {
2783                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2784                         reg = <0 0x0a6f8800 0 0x400>;
2785                         status = "disabled";
2786                         #address-cells = <2>;
2787                         #size-cells = <2>;
2788                         ranges;
2789                         dma-ranges;
2790
2791                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2792                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2793                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2794                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2795                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2796                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2797                                       "sleep";
2798
2799                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2800                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2801                         assigned-clock-rates = <19200000>, <150000000>;
2802
2803                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2804                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2805                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2806                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2807                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2808                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2809
2810                         power-domains = <&gcc USB30_PRIM_GDSC>;
2811
2812                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2813
2814                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2815                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2816                         interconnect-names = "usb-ddr", "apps-usb";
2817
2818                         usb_1_dwc3: dwc3@a600000 {
2819                                 compatible = "snps,dwc3";
2820                                 reg = <0 0x0a600000 0 0xe000>;
2821                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2822                                 iommus = <&apps_smmu 0x540 0>;
2823                                 snps,dis_u2_susphy_quirk;
2824                                 snps,dis_enblslpm_quirk;
2825                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2826                                 phy-names = "usb2-phy", "usb3-phy";
2827                                 maximum-speed = "super-speed";
2828                         };
2829                 };
2830
2831                 venus: video-codec@aa00000 {
2832                         compatible = "qcom,sc7180-venus";
2833                         reg = <0 0x0aa00000 0 0xff000>;
2834                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2835                         power-domains = <&videocc VENUS_GDSC>,
2836                                         <&videocc VCODEC0_GDSC>,
2837                                         <&rpmhpd SC7180_CX>;
2838                         power-domain-names = "venus", "vcodec0", "cx";
2839                         operating-points-v2 = <&venus_opp_table>;
2840                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2841                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2842                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2843                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2844                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2845                         clock-names = "core", "iface", "bus",
2846                                       "vcodec0_core", "vcodec0_bus";
2847                         iommus = <&apps_smmu 0x0c00 0x60>;
2848                         memory-region = <&venus_mem>;
2849                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2850                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2851                         interconnect-names = "video-mem", "cpu-cfg";
2852
2853                         video-decoder {
2854                                 compatible = "venus-decoder";
2855                         };
2856
2857                         video-encoder {
2858                                 compatible = "venus-encoder";
2859                         };
2860
2861                         venus_opp_table: venus-opp-table {
2862                                 compatible = "operating-points-v2";
2863
2864                                 opp-150000000 {
2865                                         opp-hz = /bits/ 64 <150000000>;
2866                                         required-opps = <&rpmhpd_opp_low_svs>;
2867                                 };
2868
2869                                 opp-270000000 {
2870                                         opp-hz = /bits/ 64 <270000000>;
2871                                         required-opps = <&rpmhpd_opp_svs>;
2872                                 };
2873
2874                                 opp-340000000 {
2875                                         opp-hz = /bits/ 64 <340000000>;
2876                                         required-opps = <&rpmhpd_opp_svs_l1>;
2877                                 };
2878
2879                                 opp-434000000 {
2880                                         opp-hz = /bits/ 64 <434000000>;
2881                                         required-opps = <&rpmhpd_opp_nom>;
2882                                 };
2883
2884                                 opp-500000097 {
2885                                         opp-hz = /bits/ 64 <500000097>;
2886                                         required-opps = <&rpmhpd_opp_turbo>;
2887                                 };
2888                         };
2889                 };
2890
2891                 videocc: clock-controller@ab00000 {
2892                         compatible = "qcom,sc7180-videocc";
2893                         reg = <0 0x0ab00000 0 0x10000>;
2894                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2895                         clock-names = "bi_tcxo";
2896                         #clock-cells = <1>;
2897                         #reset-cells = <1>;
2898                         #power-domain-cells = <1>;
2899                 };
2900
2901                 camnoc_virt: interconnect@ac00000 {
2902                         compatible = "qcom,sc7180-camnoc-virt";
2903                         reg = <0 0x0ac00000 0 0x1000>;
2904                         #interconnect-cells = <2>;
2905                         qcom,bcm-voters = <&apps_bcm_voter>;
2906                 };
2907
2908                 camcc: clock-controller@ad00000 {
2909                         compatible = "qcom,sc7180-camcc";
2910                         reg = <0 0x0ad00000 0 0x10000>;
2911                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2912                                <&gcc GCC_CAMERA_AHB_CLK>,
2913                                <&gcc GCC_CAMERA_XO_CLK>;
2914                         clock-names = "bi_tcxo", "iface", "xo";
2915                         #clock-cells = <1>;
2916                         #reset-cells = <1>;
2917                         #power-domain-cells = <1>;
2918                 };
2919
2920                 mdss: mdss@ae00000 {
2921                         compatible = "qcom,sc7180-mdss";
2922                         reg = <0 0x0ae00000 0 0x1000>;
2923                         reg-names = "mdss";
2924
2925                         power-domains = <&dispcc MDSS_GDSC>;
2926
2927                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2928                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
2929                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2930                         clock-names = "iface", "ahb", "core";
2931
2932                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2933                         assigned-clock-rates = <300000000>;
2934
2935                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2936                         interrupt-controller;
2937                         #interrupt-cells = <1>;
2938
2939                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2940                         interconnect-names = "mdp0-mem";
2941
2942                         iommus = <&apps_smmu 0x800 0x2>;
2943
2944                         #address-cells = <2>;
2945                         #size-cells = <2>;
2946                         ranges;
2947
2948                         status = "disabled";
2949
2950                         mdp: mdp@ae01000 {
2951                                 compatible = "qcom,sc7180-dpu";
2952                                 reg = <0 0x0ae01000 0 0x8f000>,
2953                                       <0 0x0aeb0000 0 0x2008>;
2954                                 reg-names = "mdp", "vbif";
2955
2956                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2957                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2958                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
2959                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2960                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2961                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
2962                                 clock-names = "bus", "iface", "rot", "lut", "core",
2963                                               "vsync";
2964                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
2965                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
2966                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
2967                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
2968                                 assigned-clock-rates = <300000000>,
2969                                                        <19200000>,
2970                                                        <19200000>,
2971                                                        <19200000>;
2972                                 operating-points-v2 = <&mdp_opp_table>;
2973                                 power-domains = <&rpmhpd SC7180_CX>;
2974
2975                                 interrupt-parent = <&mdss>;
2976                                 interrupts = <0>;
2977
2978                                 status = "disabled";
2979
2980                                 ports {
2981                                         #address-cells = <1>;
2982                                         #size-cells = <0>;
2983
2984                                         port@0 {
2985                                                 reg = <0>;
2986                                                 dpu_intf1_out: endpoint {
2987                                                         remote-endpoint = <&dsi0_in>;
2988                                                 };
2989                                         };
2990                                 };
2991
2992                                 mdp_opp_table: mdp-opp-table {
2993                                         compatible = "operating-points-v2";
2994
2995                                         opp-200000000 {
2996                                                 opp-hz = /bits/ 64 <200000000>;
2997                                                 required-opps = <&rpmhpd_opp_low_svs>;
2998                                         };
2999
3000                                         opp-300000000 {
3001                                                 opp-hz = /bits/ 64 <300000000>;
3002                                                 required-opps = <&rpmhpd_opp_svs>;
3003                                         };
3004
3005                                         opp-345000000 {
3006                                                 opp-hz = /bits/ 64 <345000000>;
3007                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3008                                         };
3009
3010                                         opp-460000000 {
3011                                                 opp-hz = /bits/ 64 <460000000>;
3012                                                 required-opps = <&rpmhpd_opp_nom>;
3013                                         };
3014                                 };
3015
3016                         };
3017
3018                         dsi0: dsi@ae94000 {
3019                                 compatible = "qcom,mdss-dsi-ctrl";
3020                                 reg = <0 0x0ae94000 0 0x400>;
3021                                 reg-names = "dsi_ctrl";
3022
3023                                 interrupt-parent = <&mdss>;
3024                                 interrupts = <4>;
3025
3026                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3027                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3028                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3029                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3030                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3031                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3032                                 clock-names = "byte",
3033                                               "byte_intf",
3034                                               "pixel",
3035                                               "core",
3036                                               "iface",
3037                                               "bus";
3038
3039                                 operating-points-v2 = <&dsi_opp_table>;
3040                                 power-domains = <&rpmhpd SC7180_CX>;
3041
3042                                 phys = <&dsi_phy>;
3043                                 phy-names = "dsi";
3044
3045                                 #address-cells = <1>;
3046                                 #size-cells = <0>;
3047
3048                                 status = "disabled";
3049
3050                                 ports {
3051                                         #address-cells = <1>;
3052                                         #size-cells = <0>;
3053
3054                                         port@0 {
3055                                                 reg = <0>;
3056                                                 dsi0_in: endpoint {
3057                                                         remote-endpoint = <&dpu_intf1_out>;
3058                                                 };
3059                                         };
3060
3061                                         port@1 {
3062                                                 reg = <1>;
3063                                                 dsi0_out: endpoint {
3064                                                 };
3065                                         };
3066                                 };
3067
3068                                 dsi_opp_table: dsi-opp-table {
3069                                         compatible = "operating-points-v2";
3070
3071                                         opp-187500000 {
3072                                                 opp-hz = /bits/ 64 <187500000>;
3073                                                 required-opps = <&rpmhpd_opp_low_svs>;
3074                                         };
3075
3076                                         opp-300000000 {
3077                                                 opp-hz = /bits/ 64 <300000000>;
3078                                                 required-opps = <&rpmhpd_opp_svs>;
3079                                         };
3080
3081                                         opp-358000000 {
3082                                                 opp-hz = /bits/ 64 <358000000>;
3083                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3084                                         };
3085                                 };
3086                         };
3087
3088                         dsi_phy: dsi-phy@ae94400 {
3089                                 compatible = "qcom,dsi-phy-10nm";
3090                                 reg = <0 0x0ae94400 0 0x200>,
3091                                       <0 0x0ae94600 0 0x280>,
3092                                       <0 0x0ae94a00 0 0x1e0>;
3093                                 reg-names = "dsi_phy",
3094                                             "dsi_phy_lane",
3095                                             "dsi_pll";
3096
3097                                 #clock-cells = <1>;
3098                                 #phy-cells = <0>;
3099
3100                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3101                                          <&rpmhcc RPMH_CXO_CLK>;
3102                                 clock-names = "iface", "ref";
3103
3104                                 status = "disabled";
3105                         };
3106                 };
3107
3108                 dispcc: clock-controller@af00000 {
3109                         compatible = "qcom,sc7180-dispcc";
3110                         reg = <0 0x0af00000 0 0x200000>;
3111                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3112                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3113                                  <&dsi_phy 0>,
3114                                  <&dsi_phy 1>,
3115                                  <0>,
3116                                  <0>;
3117                         clock-names = "bi_tcxo",
3118                                       "gcc_disp_gpll0_clk_src",
3119                                       "dsi0_phy_pll_out_byteclk",
3120                                       "dsi0_phy_pll_out_dsiclk",
3121                                       "dp_phy_pll_link_clk",
3122                                       "dp_phy_pll_vco_div_clk";
3123                         #clock-cells = <1>;
3124                         #reset-cells = <1>;
3125                         #power-domain-cells = <1>;
3126                 };
3127
3128                 pdc: interrupt-controller@b220000 {
3129                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3130                         reg = <0 0x0b220000 0 0x30000>;
3131                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3132                         #interrupt-cells = <2>;
3133                         interrupt-parent = <&intc>;
3134                         interrupt-controller;
3135                 };
3136
3137                 pdc_reset: reset-controller@b2e0000 {
3138                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3139                         reg = <0 0x0b2e0000 0 0x20000>;
3140                         #reset-cells = <1>;
3141                 };
3142
3143                 tsens0: thermal-sensor@c263000 {
3144                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3145                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3146                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3147                         #qcom,sensors = <15>;
3148                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3149                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3150                         interrupt-names = "uplow","critical";
3151                         #thermal-sensor-cells = <1>;
3152                 };
3153
3154                 tsens1: thermal-sensor@c265000 {
3155                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3156                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3157                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3158                         #qcom,sensors = <10>;
3159                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3160                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3161                         interrupt-names = "uplow","critical";
3162                         #thermal-sensor-cells = <1>;
3163                 };
3164
3165                 aoss_reset: reset-controller@c2a0000 {
3166                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3167                         reg = <0 0x0c2a0000 0 0x31000>;
3168                         #reset-cells = <1>;
3169                 };
3170
3171                 aoss_qmp: qmp@c300000 {
3172                         compatible = "qcom,sc7180-aoss-qmp";
3173                         reg = <0 0x0c300000 0 0x100000>;
3174                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3175                         mboxes = <&apss_shared 0>;
3176
3177                         #clock-cells = <0>;
3178                         #power-domain-cells = <1>;
3179                 };
3180
3181                 spmi_bus: spmi@c440000 {
3182                         compatible = "qcom,spmi-pmic-arb";
3183                         reg = <0 0x0c440000 0 0x1100>,
3184                               <0 0x0c600000 0 0x2000000>,
3185                               <0 0x0e600000 0 0x100000>,
3186                               <0 0x0e700000 0 0xa0000>,
3187                               <0 0x0c40a000 0 0x26000>;
3188                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3189                         interrupt-names = "periph_irq";
3190                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3191                         qcom,ee = <0>;
3192                         qcom,channel = <0>;
3193                         #address-cells = <1>;
3194                         #size-cells = <1>;
3195                         interrupt-controller;
3196                         #interrupt-cells = <4>;
3197                         cell-index = <0>;
3198                 };
3199
3200                 apps_smmu: iommu@15000000 {
3201                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3202                         reg = <0 0x15000000 0 0x100000>;
3203                         #iommu-cells = <2>;
3204                         #global-interrupts = <1>;
3205                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3206                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3207                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3208                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3209                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3210                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3211                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3212                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3213                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3214                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3215                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3216                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3217                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3218                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3219                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3220                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3221                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3222                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3223                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3224                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3225                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3226                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3227                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3228                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3229                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3230                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3231                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3232                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3233                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3234                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3235                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3236                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3237                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3238                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3239                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3240                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3241                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3242                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3243                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3244                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3245                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3246                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3247                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3248                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3249                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3250                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3251                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3252                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3253                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3254                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3255                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3256                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3257                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3258                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3259                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3260                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3261                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3262                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3263                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3264                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3265                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3266                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3267                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3268                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3269                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3270                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3271                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3272                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3278                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3279                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3280                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3281                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3282                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3283                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3284                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3285                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3286                 };
3287
3288                 intc: interrupt-controller@17a00000 {
3289                         compatible = "arm,gic-v3";
3290                         #address-cells = <2>;
3291                         #size-cells = <2>;
3292                         ranges;
3293                         #interrupt-cells = <3>;
3294                         interrupt-controller;
3295                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3296                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3297                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3298
3299                         msi-controller@17a40000 {
3300                                 compatible = "arm,gic-v3-its";
3301                                 msi-controller;
3302                                 #msi-cells = <1>;
3303                                 reg = <0 0x17a40000 0 0x20000>;
3304                                 status = "disabled";
3305                         };
3306                 };
3307
3308                 apss_shared: mailbox@17c00000 {
3309                         compatible = "qcom,sc7180-apss-shared";
3310                         reg = <0 0x17c00000 0 0x10000>;
3311                         #mbox-cells = <1>;
3312                 };
3313
3314                 watchdog@17c10000 {
3315                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3316                         reg = <0 0x17c10000 0 0x1000>;
3317                         clocks = <&sleep_clk>;
3318                 };
3319
3320                 timer@17c20000{
3321                         #address-cells = <2>;
3322                         #size-cells = <2>;
3323                         ranges;
3324                         compatible = "arm,armv7-timer-mem";
3325                         reg = <0 0x17c20000 0 0x1000>;
3326
3327                         frame@17c21000 {
3328                                 frame-number = <0>;
3329                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3330                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3331                                 reg = <0 0x17c21000 0 0x1000>,
3332                                       <0 0x17c22000 0 0x1000>;
3333                         };
3334
3335                         frame@17c23000 {
3336                                 frame-number = <1>;
3337                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3338                                 reg = <0 0x17c23000 0 0x1000>;
3339                                 status = "disabled";
3340                         };
3341
3342                         frame@17c25000 {
3343                                 frame-number = <2>;
3344                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3345                                 reg = <0 0x17c25000 0 0x1000>;
3346                                 status = "disabled";
3347                         };
3348
3349                         frame@17c27000 {
3350                                 frame-number = <3>;
3351                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3352                                 reg = <0 0x17c27000 0 0x1000>;
3353                                 status = "disabled";
3354                         };
3355
3356                         frame@17c29000 {
3357                                 frame-number = <4>;
3358                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3359                                 reg = <0 0x17c29000 0 0x1000>;
3360                                 status = "disabled";
3361                         };
3362
3363                         frame@17c2b000 {
3364                                 frame-number = <5>;
3365                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3366                                 reg = <0 0x17c2b000 0 0x1000>;
3367                                 status = "disabled";
3368                         };
3369
3370                         frame@17c2d000 {
3371                                 frame-number = <6>;
3372                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3373                                 reg = <0 0x17c2d000 0 0x1000>;
3374                                 status = "disabled";
3375                         };
3376                 };
3377
3378                 apps_rsc: rsc@18200000 {
3379                         compatible = "qcom,rpmh-rsc";
3380                         reg = <0 0x18200000 0 0x10000>,
3381                               <0 0x18210000 0 0x10000>,
3382                               <0 0x18220000 0 0x10000>;
3383                         reg-names = "drv-0", "drv-1", "drv-2";
3384                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3385                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3386                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3387                         qcom,tcs-offset = <0xd00>;
3388                         qcom,drv-id = <2>;
3389                         qcom,tcs-config = <ACTIVE_TCS  2>,
3390                                           <SLEEP_TCS   3>,
3391                                           <WAKE_TCS    3>,
3392                                           <CONTROL_TCS 1>;
3393
3394                         rpmhcc: clock-controller {
3395                                 compatible = "qcom,sc7180-rpmh-clk";
3396                                 clocks = <&xo_board>;
3397                                 clock-names = "xo";
3398                                 #clock-cells = <1>;
3399                         };
3400
3401                         rpmhpd: power-controller {
3402                                 compatible = "qcom,sc7180-rpmhpd";
3403                                 #power-domain-cells = <1>;
3404                                 operating-points-v2 = <&rpmhpd_opp_table>;
3405
3406                                 rpmhpd_opp_table: opp-table {
3407                                         compatible = "operating-points-v2";
3408
3409                                         rpmhpd_opp_ret: opp1 {
3410                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3411                                         };
3412
3413                                         rpmhpd_opp_min_svs: opp2 {
3414                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3415                                         };
3416
3417                                         rpmhpd_opp_low_svs: opp3 {
3418                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3419                                         };
3420
3421                                         rpmhpd_opp_svs: opp4 {
3422                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3423                                         };
3424
3425                                         rpmhpd_opp_svs_l1: opp5 {
3426                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3427                                         };
3428
3429                                         rpmhpd_opp_svs_l2: opp6 {
3430                                                 opp-level = <224>;
3431                                         };
3432
3433                                         rpmhpd_opp_nom: opp7 {
3434                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3435                                         };
3436
3437                                         rpmhpd_opp_nom_l1: opp8 {
3438                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3439                                         };
3440
3441                                         rpmhpd_opp_nom_l2: opp9 {
3442                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3443                                         };
3444
3445                                         rpmhpd_opp_turbo: opp10 {
3446                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3447                                         };
3448
3449                                         rpmhpd_opp_turbo_l1: opp11 {
3450                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3451                                         };
3452                                 };
3453                         };
3454
3455                         apps_bcm_voter: bcm_voter {
3456                                 compatible = "qcom,bcm-voter";
3457                         };
3458                 };
3459
3460                 osm_l3: interconnect@18321000 {
3461                         compatible = "qcom,sc7180-osm-l3";
3462                         reg = <0 0x18321000 0 0x1400>;
3463
3464                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3465                         clock-names = "xo", "alternate";
3466
3467                         #interconnect-cells = <1>;
3468                 };
3469
3470                 cpufreq_hw: cpufreq@18323000 {
3471                         compatible = "qcom,cpufreq-hw";
3472                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3473                         reg-names = "freq-domain0", "freq-domain1";
3474
3475                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3476                         clock-names = "xo", "alternate";
3477
3478                         #freq-domain-cells = <1>;
3479                 };
3480
3481                 wifi: wifi@18800000 {
3482                         compatible = "qcom,wcn3990-wifi";
3483                         reg = <0 0x18800000 0 0x800000>;
3484                         reg-names = "membase";
3485                         iommus = <&apps_smmu 0xc0 0x1>;
3486                         interrupts =
3487                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3488                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3489                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3490                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3491                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3492                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3493                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3494                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3495                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3496                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3497                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3498                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3499                         memory-region = <&wlan_mem>;
3500                         qcom,msa-fixed-perm;
3501                         status = "disabled";
3502                 };
3503
3504                 lpasscc: clock-controller@62d00000 {
3505                         compatible = "qcom,sc7180-lpasscorecc";
3506                         reg = <0 0x62d00000 0 0x50000>,
3507                               <0 0x62780000 0 0x30000>;
3508                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3509                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3510                                  <&rpmhcc RPMH_CXO_CLK>;
3511                         clock-names = "iface", "bi_tcxo";
3512                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3513                         #clock-cells = <1>;
3514                         #power-domain-cells = <1>;
3515                 };
3516
3517                 lpass_hm: clock-controller@63000000 {
3518                         compatible = "qcom,sc7180-lpasshm";
3519                         reg = <0 0x63000000 0 0x28>;
3520                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3521                                  <&rpmhcc RPMH_CXO_CLK>;
3522                         clock-names = "iface", "bi_tcxo";
3523                         #clock-cells = <1>;
3524                         #power-domain-cells = <1>;
3525                 };
3526         };
3527
3528         thermal-zones {
3529                 cpu0-thermal {
3530                         polling-delay-passive = <250>;
3531                         polling-delay = <0>;
3532
3533                         thermal-sensors = <&tsens0 1>;
3534                         sustainable-power = <768>;
3535
3536                         trips {
3537                                 cpu0_alert0: trip-point0 {
3538                                         temperature = <90000>;
3539                                         hysteresis = <2000>;
3540                                         type = "passive";
3541                                 };
3542
3543                                 cpu0_alert1: trip-point1 {
3544                                         temperature = <95000>;
3545                                         hysteresis = <2000>;
3546                                         type = "passive";
3547                                 };
3548
3549                                 cpu0_crit: cpu_crit {
3550                                         temperature = <110000>;
3551                                         hysteresis = <1000>;
3552                                         type = "critical";
3553                                 };
3554                         };
3555
3556                         cooling-maps {
3557                                 map0 {
3558                                         trip = <&cpu0_alert0>;
3559                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3560                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3561                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3562                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3563                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3564                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3565                                 };
3566                                 map1 {
3567                                         trip = <&cpu0_alert1>;
3568                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3569                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3570                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3571                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3572                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3573                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3574                                 };
3575                         };
3576                 };
3577
3578                 cpu1-thermal {
3579                         polling-delay-passive = <250>;
3580                         polling-delay = <0>;
3581
3582                         thermal-sensors = <&tsens0 2>;
3583                         sustainable-power = <768>;
3584
3585                         trips {
3586                                 cpu1_alert0: trip-point0 {
3587                                         temperature = <90000>;
3588                                         hysteresis = <2000>;
3589                                         type = "passive";
3590                                 };
3591
3592                                 cpu1_alert1: trip-point1 {
3593                                         temperature = <95000>;
3594                                         hysteresis = <2000>;
3595                                         type = "passive";
3596                                 };
3597
3598                                 cpu1_crit: cpu_crit {
3599                                         temperature = <110000>;
3600                                         hysteresis = <1000>;
3601                                         type = "critical";
3602                                 };
3603                         };
3604
3605                         cooling-maps {
3606                                 map0 {
3607                                         trip = <&cpu1_alert0>;
3608                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3609                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3610                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3611                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3612                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3613                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3614                                 };
3615                                 map1 {
3616                                         trip = <&cpu1_alert1>;
3617                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3618                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3619                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3620                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3621                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3622                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3623                                 };
3624                         };
3625                 };
3626
3627                 cpu2-thermal {
3628                         polling-delay-passive = <250>;
3629                         polling-delay = <0>;
3630
3631                         thermal-sensors = <&tsens0 3>;
3632                         sustainable-power = <768>;
3633
3634                         trips {
3635                                 cpu2_alert0: trip-point0 {
3636                                         temperature = <90000>;
3637                                         hysteresis = <2000>;
3638                                         type = "passive";
3639                                 };
3640
3641                                 cpu2_alert1: trip-point1 {
3642                                         temperature = <95000>;
3643                                         hysteresis = <2000>;
3644                                         type = "passive";
3645                                 };
3646
3647                                 cpu2_crit: cpu_crit {
3648                                         temperature = <110000>;
3649                                         hysteresis = <1000>;
3650                                         type = "critical";
3651                                 };
3652                         };
3653
3654                         cooling-maps {
3655                                 map0 {
3656                                         trip = <&cpu2_alert0>;
3657                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3659                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3660                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3661                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3662                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3663                                 };
3664                                 map1 {
3665                                         trip = <&cpu2_alert1>;
3666                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3667                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3668                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3669                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3670                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3671                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3672                                 };
3673                         };
3674                 };
3675
3676                 cpu3-thermal {
3677                         polling-delay-passive = <250>;
3678                         polling-delay = <0>;
3679
3680                         thermal-sensors = <&tsens0 4>;
3681                         sustainable-power = <768>;
3682
3683                         trips {
3684                                 cpu3_alert0: trip-point0 {
3685                                         temperature = <90000>;
3686                                         hysteresis = <2000>;
3687                                         type = "passive";
3688                                 };
3689
3690                                 cpu3_alert1: trip-point1 {
3691                                         temperature = <95000>;
3692                                         hysteresis = <2000>;
3693                                         type = "passive";
3694                                 };
3695
3696                                 cpu3_crit: cpu_crit {
3697                                         temperature = <110000>;
3698                                         hysteresis = <1000>;
3699                                         type = "critical";
3700                                 };
3701                         };
3702
3703                         cooling-maps {
3704                                 map0 {
3705                                         trip = <&cpu3_alert0>;
3706                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3707                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3708                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3709                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3710                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3711                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3712                                 };
3713                                 map1 {
3714                                         trip = <&cpu3_alert1>;
3715                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3716                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3717                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3718                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3719                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3720                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3721                                 };
3722                         };
3723                 };
3724
3725                 cpu4-thermal {
3726                         polling-delay-passive = <250>;
3727                         polling-delay = <0>;
3728
3729                         thermal-sensors = <&tsens0 5>;
3730                         sustainable-power = <768>;
3731
3732                         trips {
3733                                 cpu4_alert0: trip-point0 {
3734                                         temperature = <90000>;
3735                                         hysteresis = <2000>;
3736                                         type = "passive";
3737                                 };
3738
3739                                 cpu4_alert1: trip-point1 {
3740                                         temperature = <95000>;
3741                                         hysteresis = <2000>;
3742                                         type = "passive";
3743                                 };
3744
3745                                 cpu4_crit: cpu_crit {
3746                                         temperature = <110000>;
3747                                         hysteresis = <1000>;
3748                                         type = "critical";
3749                                 };
3750                         };
3751
3752                         cooling-maps {
3753                                 map0 {
3754                                         trip = <&cpu4_alert0>;
3755                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3756                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3757                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3758                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3759                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3760                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3761                                 };
3762                                 map1 {
3763                                         trip = <&cpu4_alert1>;
3764                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3765                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3766                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3767                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3768                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3769                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3770                                 };
3771                         };
3772                 };
3773
3774                 cpu5-thermal {
3775                         polling-delay-passive = <250>;
3776                         polling-delay = <0>;
3777
3778                         thermal-sensors = <&tsens0 6>;
3779                         sustainable-power = <768>;
3780
3781                         trips {
3782                                 cpu5_alert0: trip-point0 {
3783                                         temperature = <90000>;
3784                                         hysteresis = <2000>;
3785                                         type = "passive";
3786                                 };
3787
3788                                 cpu5_alert1: trip-point1 {
3789                                         temperature = <95000>;
3790                                         hysteresis = <2000>;
3791                                         type = "passive";
3792                                 };
3793
3794                                 cpu5_crit: cpu_crit {
3795                                         temperature = <110000>;
3796                                         hysteresis = <1000>;
3797                                         type = "critical";
3798                                 };
3799                         };
3800
3801                         cooling-maps {
3802                                 map0 {
3803                                         trip = <&cpu5_alert0>;
3804                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3805                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3806                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3807                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3808                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3809                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3810                                 };
3811                                 map1 {
3812                                         trip = <&cpu5_alert1>;
3813                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3814                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3815                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3816                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3817                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3818                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3819                                 };
3820                         };
3821                 };
3822
3823                 cpu6-thermal {
3824                         polling-delay-passive = <250>;
3825                         polling-delay = <0>;
3826
3827                         thermal-sensors = <&tsens0 9>;
3828                         sustainable-power = <1202>;
3829
3830                         trips {
3831                                 cpu6_alert0: trip-point0 {
3832                                         temperature = <90000>;
3833                                         hysteresis = <2000>;
3834                                         type = "passive";
3835                                 };
3836
3837                                 cpu6_alert1: trip-point1 {
3838                                         temperature = <95000>;
3839                                         hysteresis = <2000>;
3840                                         type = "passive";
3841                                 };
3842
3843                                 cpu6_crit: cpu_crit {
3844                                         temperature = <110000>;
3845                                         hysteresis = <1000>;
3846                                         type = "critical";
3847                                 };
3848                         };
3849
3850                         cooling-maps {
3851                                 map0 {
3852                                         trip = <&cpu6_alert0>;
3853                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3854                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3855                                 };
3856                                 map1 {
3857                                         trip = <&cpu6_alert1>;
3858                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3859                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3860                                 };
3861                         };
3862                 };
3863
3864                 cpu7-thermal {
3865                         polling-delay-passive = <250>;
3866                         polling-delay = <0>;
3867
3868                         thermal-sensors = <&tsens0 10>;
3869                         sustainable-power = <1202>;
3870
3871                         trips {
3872                                 cpu7_alert0: trip-point0 {
3873                                         temperature = <90000>;
3874                                         hysteresis = <2000>;
3875                                         type = "passive";
3876                                 };
3877
3878                                 cpu7_alert1: trip-point1 {
3879                                         temperature = <95000>;
3880                                         hysteresis = <2000>;
3881                                         type = "passive";
3882                                 };
3883
3884                                 cpu7_crit: cpu_crit {
3885                                         temperature = <110000>;
3886                                         hysteresis = <1000>;
3887                                         type = "critical";
3888                                 };
3889                         };
3890
3891                         cooling-maps {
3892                                 map0 {
3893                                         trip = <&cpu7_alert0>;
3894                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3895                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3896                                 };
3897                                 map1 {
3898                                         trip = <&cpu7_alert1>;
3899                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3900                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3901                                 };
3902                         };
3903                 };
3904
3905                 cpu8-thermal {
3906                         polling-delay-passive = <250>;
3907                         polling-delay = <0>;
3908
3909                         thermal-sensors = <&tsens0 11>;
3910                         sustainable-power = <1202>;
3911
3912                         trips {
3913                                 cpu8_alert0: trip-point0 {
3914                                         temperature = <90000>;
3915                                         hysteresis = <2000>;
3916                                         type = "passive";
3917                                 };
3918
3919                                 cpu8_alert1: trip-point1 {
3920                                         temperature = <95000>;
3921                                         hysteresis = <2000>;
3922                                         type = "passive";
3923                                 };
3924
3925                                 cpu8_crit: cpu_crit {
3926                                         temperature = <110000>;
3927                                         hysteresis = <1000>;
3928                                         type = "critical";
3929                                 };
3930                         };
3931
3932                         cooling-maps {
3933                                 map0 {
3934                                         trip = <&cpu8_alert0>;
3935                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3936                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3937                                 };
3938                                 map1 {
3939                                         trip = <&cpu8_alert1>;
3940                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3941                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3942                                 };
3943                         };
3944                 };
3945
3946                 cpu9-thermal {
3947                         polling-delay-passive = <250>;
3948                         polling-delay = <0>;
3949
3950                         thermal-sensors = <&tsens0 12>;
3951                         sustainable-power = <1202>;
3952
3953                         trips {
3954                                 cpu9_alert0: trip-point0 {
3955                                         temperature = <90000>;
3956                                         hysteresis = <2000>;
3957                                         type = "passive";
3958                                 };
3959
3960                                 cpu9_alert1: trip-point1 {
3961                                         temperature = <95000>;
3962                                         hysteresis = <2000>;
3963                                         type = "passive";
3964                                 };
3965
3966                                 cpu9_crit: cpu_crit {
3967                                         temperature = <110000>;
3968                                         hysteresis = <1000>;
3969                                         type = "critical";
3970                                 };
3971                         };
3972
3973                         cooling-maps {
3974                                 map0 {
3975                                         trip = <&cpu9_alert0>;
3976                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3977                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3978                                 };
3979                                 map1 {
3980                                         trip = <&cpu9_alert1>;
3981                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3982                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3983                                 };
3984                         };
3985                 };
3986
3987                 aoss0-thermal {
3988                         polling-delay-passive = <250>;
3989                         polling-delay = <0>;
3990
3991                         thermal-sensors = <&tsens0 0>;
3992
3993                         trips {
3994                                 aoss0_alert0: trip-point0 {
3995                                         temperature = <90000>;
3996                                         hysteresis = <2000>;
3997                                         type = "hot";
3998                                 };
3999
4000                                 aoss0_crit: aoss0_crit {
4001                                         temperature = <110000>;
4002                                         hysteresis = <2000>;
4003                                         type = "critical";
4004                                 };
4005                         };
4006                 };
4007
4008                 cpuss0-thermal {
4009                         polling-delay-passive = <250>;
4010                         polling-delay = <0>;
4011
4012                         thermal-sensors = <&tsens0 7>;
4013
4014                         trips {
4015                                 cpuss0_alert0: trip-point0 {
4016                                         temperature = <90000>;
4017                                         hysteresis = <2000>;
4018                                         type = "hot";
4019                                 };
4020                                 cpuss0_crit: cluster0_crit {
4021                                         temperature = <110000>;
4022                                         hysteresis = <2000>;
4023                                         type = "critical";
4024                                 };
4025                         };
4026                 };
4027
4028                 cpuss1-thermal {
4029                         polling-delay-passive = <250>;
4030                         polling-delay = <0>;
4031
4032                         thermal-sensors = <&tsens0 8>;
4033
4034                         trips {
4035                                 cpuss1_alert0: trip-point0 {
4036                                         temperature = <90000>;
4037                                         hysteresis = <2000>;
4038                                         type = "hot";
4039                                 };
4040                                 cpuss1_crit: cluster0_crit {
4041                                         temperature = <110000>;
4042                                         hysteresis = <2000>;
4043                                         type = "critical";
4044                                 };
4045                         };
4046                 };
4047
4048                 gpuss0-thermal {
4049                         polling-delay-passive = <250>;
4050                         polling-delay = <0>;
4051
4052                         thermal-sensors = <&tsens0 13>;
4053
4054                         trips {
4055                                 gpuss0_alert0: trip-point0 {
4056                                         temperature = <95000>;
4057                                         hysteresis = <2000>;
4058                                         type = "passive";
4059                                 };
4060
4061                                 gpuss0_crit: gpuss0_crit {
4062                                         temperature = <110000>;
4063                                         hysteresis = <2000>;
4064                                         type = "critical";
4065                                 };
4066                         };
4067
4068                         cooling-maps {
4069                                 map0 {
4070                                         trip = <&gpuss0_alert0>;
4071                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4072                                 };
4073                         };
4074                 };
4075
4076                 gpuss1-thermal {
4077                         polling-delay-passive = <250>;
4078                         polling-delay = <0>;
4079
4080                         thermal-sensors = <&tsens0 14>;
4081
4082                         trips {
4083                                 gpuss1_alert0: trip-point0 {
4084                                         temperature = <95000>;
4085                                         hysteresis = <2000>;
4086                                         type = "passive";
4087                                 };
4088
4089                                 gpuss1_crit: gpuss1_crit {
4090                                         temperature = <110000>;
4091                                         hysteresis = <2000>;
4092                                         type = "critical";
4093                                 };
4094                         };
4095
4096                         cooling-maps {
4097                                 map0 {
4098                                         trip = <&gpuss1_alert0>;
4099                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4100                                 };
4101                         };
4102                 };
4103
4104                 aoss1-thermal {
4105                         polling-delay-passive = <250>;
4106                         polling-delay = <0>;
4107
4108                         thermal-sensors = <&tsens1 0>;
4109
4110                         trips {
4111                                 aoss1_alert0: trip-point0 {
4112                                         temperature = <90000>;
4113                                         hysteresis = <2000>;
4114                                         type = "hot";
4115                                 };
4116
4117                                 aoss1_crit: aoss1_crit {
4118                                         temperature = <110000>;
4119                                         hysteresis = <2000>;
4120                                         type = "critical";
4121                                 };
4122                         };
4123                 };
4124
4125                 cwlan-thermal {
4126                         polling-delay-passive = <250>;
4127                         polling-delay = <0>;
4128
4129                         thermal-sensors = <&tsens1 1>;
4130
4131                         trips {
4132                                 cwlan_alert0: trip-point0 {
4133                                         temperature = <90000>;
4134                                         hysteresis = <2000>;
4135                                         type = "hot";
4136                                 };
4137
4138                                 cwlan_crit: cwlan_crit {
4139                                         temperature = <110000>;
4140                                         hysteresis = <2000>;
4141                                         type = "critical";
4142                                 };
4143                         };
4144                 };
4145
4146                 audio-thermal {
4147                         polling-delay-passive = <250>;
4148                         polling-delay = <0>;
4149
4150                         thermal-sensors = <&tsens1 2>;
4151
4152                         trips {
4153                                 audio_alert0: trip-point0 {
4154                                         temperature = <90000>;
4155                                         hysteresis = <2000>;
4156                                         type = "hot";
4157                                 };
4158
4159                                 audio_crit: audio_crit {
4160                                         temperature = <110000>;
4161                                         hysteresis = <2000>;
4162                                         type = "critical";
4163                                 };
4164                         };
4165                 };
4166
4167                 ddr-thermal {
4168                         polling-delay-passive = <250>;
4169                         polling-delay = <0>;
4170
4171                         thermal-sensors = <&tsens1 3>;
4172
4173                         trips {
4174                                 ddr_alert0: trip-point0 {
4175                                         temperature = <90000>;
4176                                         hysteresis = <2000>;
4177                                         type = "hot";
4178                                 };
4179
4180                                 ddr_crit: ddr_crit {
4181                                         temperature = <110000>;
4182                                         hysteresis = <2000>;
4183                                         type = "critical";
4184                                 };
4185                         };
4186                 };
4187
4188                 q6-hvx-thermal {
4189                         polling-delay-passive = <250>;
4190                         polling-delay = <0>;
4191
4192                         thermal-sensors = <&tsens1 4>;
4193
4194                         trips {
4195                                 q6_hvx_alert0: trip-point0 {
4196                                         temperature = <90000>;
4197                                         hysteresis = <2000>;
4198                                         type = "hot";
4199                                 };
4200
4201                                 q6_hvx_crit: q6_hvx_crit {
4202                                         temperature = <110000>;
4203                                         hysteresis = <2000>;
4204                                         type = "critical";
4205                                 };
4206                         };
4207                 };
4208
4209                 camera-thermal {
4210                         polling-delay-passive = <250>;
4211                         polling-delay = <0>;
4212
4213                         thermal-sensors = <&tsens1 5>;
4214
4215                         trips {
4216                                 camera_alert0: trip-point0 {
4217                                         temperature = <90000>;
4218                                         hysteresis = <2000>;
4219                                         type = "hot";
4220                                 };
4221
4222                                 camera_crit: camera_crit {
4223                                         temperature = <110000>;
4224                                         hysteresis = <2000>;
4225                                         type = "critical";
4226                                 };
4227                         };
4228                 };
4229
4230                 mdm-core-thermal {
4231                         polling-delay-passive = <250>;
4232                         polling-delay = <0>;
4233
4234                         thermal-sensors = <&tsens1 6>;
4235
4236                         trips {
4237                                 mdm_alert0: trip-point0 {
4238                                         temperature = <90000>;
4239                                         hysteresis = <2000>;
4240                                         type = "hot";
4241                                 };
4242
4243                                 mdm_crit: mdm_crit {
4244                                         temperature = <110000>;
4245                                         hysteresis = <2000>;
4246                                         type = "critical";
4247                                 };
4248                         };
4249                 };
4250
4251                 mdm-dsp-thermal {
4252                         polling-delay-passive = <250>;
4253                         polling-delay = <0>;
4254
4255                         thermal-sensors = <&tsens1 7>;
4256
4257                         trips {
4258                                 mdm_dsp_alert0: trip-point0 {
4259                                         temperature = <90000>;
4260                                         hysteresis = <2000>;
4261                                         type = "hot";
4262                                 };
4263
4264                                 mdm_dsp_crit: mdm_dsp_crit {
4265                                         temperature = <110000>;
4266                                         hysteresis = <2000>;
4267                                         type = "critical";
4268                                 };
4269                         };
4270                 };
4271
4272                 npu-thermal {
4273                         polling-delay-passive = <250>;
4274                         polling-delay = <0>;
4275
4276                         thermal-sensors = <&tsens1 8>;
4277
4278                         trips {
4279                                 npu_alert0: trip-point0 {
4280                                         temperature = <90000>;
4281                                         hysteresis = <2000>;
4282                                         type = "hot";
4283                                 };
4284
4285                                 npu_crit: npu_crit {
4286                                         temperature = <110000>;
4287                                         hysteresis = <2000>;
4288                                         type = "critical";
4289                                 };
4290                         };
4291                 };
4292
4293                 video-thermal {
4294                         polling-delay-passive = <250>;
4295                         polling-delay = <0>;
4296
4297                         thermal-sensors = <&tsens1 9>;
4298
4299                         trips {
4300                                 video_alert0: trip-point0 {
4301                                         temperature = <90000>;
4302                                         hysteresis = <2000>;
4303                                         type = "hot";
4304                                 };
4305
4306                                 video_crit: video_crit {
4307                                         temperature = <110000>;
4308                                         hysteresis = <2000>;
4309                                         type = "critical";
4310                                 };
4311                         };
4312                 };
4313         };
4314
4315         timer {
4316                 compatible = "arm,armv8-timer";
4317                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4318                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4319                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4320                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4321         };
4322 };