arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sc7180.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  18 #include <dt-bindings/power/qcom-aoss-qmp.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         aliases {
  34                 mmc1 = &sdhc_1;
  35                 mmc2 = &sdhc_2;
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi3 = &spi3;
  51                 spi5 = &spi5;
  52                 spi6 = &spi6;
  53                 spi8 = &spi8;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56         };
  57
  58         clocks {
  59                 xo_board: xo-board {
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <38400000>;
  62                         #clock-cells = <0>;
  63                 };
  64
  65                 sleep_clk: sleep-clk {
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32764>;
  68                         #clock-cells = <0>;
  69                 };
  70         };
  71
  72         reserved_memory: reserved-memory {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 hyp_mem: memory@80000000 {
  78                         reg = <0x0 0x80000000 0x0 0x600000>;
  79                         no-map;
  80                 };
  81
  82                 xbl_mem: memory@80600000 {
  83                         reg = <0x0 0x80600000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 aop_mem: memory@80800000 {
  88                         reg = <0x0 0x80800000 0x0 0x20000>;
  89                         no-map;
  90                 };
  91
  92                 aop_cmd_db_mem: memory@80820000 {
  93                         reg = <0x0 0x80820000 0x0 0x20000>;
  94                         compatible = "qcom,cmd-db";
  95                         no-map;
  96                 };
  97
  98                 sec_apps_mem: memory@808ff000 {
  99                         reg = <0x0 0x808ff000 0x0 0x1000>;
 100                         no-map;
 101                 };
 102
 103                 smem_mem: memory@80900000 {
 104                         reg = <0x0 0x80900000 0x0 0x200000>;
 105                         no-map;
 106                 };
 107
 108                 tz_mem: memory@80b00000 {
 109                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 110                         no-map;
 111                 };
 112
 113                 rmtfs_mem: memory@84400000 {
 114                         compatible = "qcom,rmtfs-mem";
 115                         reg = <0x0 0x84400000 0x0 0x200000>;
 116                         no-map;
 117
 118                         qcom,client-id = <1>;
 119                         qcom,vmid = <15>;
 120                 };
 121         };
 122
 123         cpus {
 124                 #address-cells = <2>;
 125                 #size-cells = <0>;
 126
 127                 CPU0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo468";
 130                         reg = <0x0 0x0>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 133                                            &LITTLE_CPU_SLEEP_1
 134                                            &CLUSTER_SLEEP_0>;
 135                         capacity-dmips-mhz = <1024>;
 136                         dynamic-power-coefficient = <100>;
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 139                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 140                         next-level-cache = <&L2_0>;
 141                         #cooling-cells = <2>;
 142                         qcom,freq-domain = <&cpufreq_hw 0>;
 143                         L2_0: l2-cache {
 144                                 compatible = "cache";
 145                                 next-level-cache = <&L3_0>;
 146                                 L3_0: l3-cache {
 147                                         compatible = "cache";
 148                                 };
 149                         };
 150                 };
 151
 152                 CPU1: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "qcom,kryo468";
 155                         reg = <0x0 0x100>;
 156                         enable-method = "psci";
 157                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 158                                            &LITTLE_CPU_SLEEP_1
 159                                            &CLUSTER_SLEEP_0>;
 160                         capacity-dmips-mhz = <1024>;
 161                         dynamic-power-coefficient = <100>;
 162                         next-level-cache = <&L2_100>;
 163                         operating-points-v2 = <&cpu0_opp_table>;
 164                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 165                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 166                         #cooling-cells = <2>;
 167                         qcom,freq-domain = <&cpufreq_hw 0>;
 168                         L2_100: l2-cache {
 169                                 compatible = "cache";
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172                 };
 173
 174                 CPU2: cpu@200 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo468";
 177                         reg = <0x0 0x200>;
 178                         enable-method = "psci";
 179                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 180                                            &LITTLE_CPU_SLEEP_1
 181                                            &CLUSTER_SLEEP_0>;
 182                         capacity-dmips-mhz = <1024>;
 183                         dynamic-power-coefficient = <100>;
 184                         next-level-cache = <&L2_200>;
 185                         operating-points-v2 = <&cpu0_opp_table>;
 186                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 187                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 188                         #cooling-cells = <2>;
 189                         qcom,freq-domain = <&cpufreq_hw 0>;
 190                         L2_200: l2-cache {
 191                                 compatible = "cache";
 192                                 next-level-cache = <&L3_0>;
 193                         };
 194                 };
 195
 196                 CPU3: cpu@300 {
 197                         device_type = "cpu";
 198                         compatible = "qcom,kryo468";
 199                         reg = <0x0 0x300>;
 200                         enable-method = "psci";
 201                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 202                                            &LITTLE_CPU_SLEEP_1
 203                                            &CLUSTER_SLEEP_0>;
 204                         capacity-dmips-mhz = <1024>;
 205                         dynamic-power-coefficient = <100>;
 206                         next-level-cache = <&L2_300>;
 207                         operating-points-v2 = <&cpu0_opp_table>;
 208                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 209                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 210                         #cooling-cells = <2>;
 211                         qcom,freq-domain = <&cpufreq_hw 0>;
 212                         L2_300: l2-cache {
 213                                 compatible = "cache";
 214                                 next-level-cache = <&L3_0>;
 215                         };
 216                 };
 217
 218                 CPU4: cpu@400 {
 219                         device_type = "cpu";
 220                         compatible = "qcom,kryo468";
 221                         reg = <0x0 0x400>;
 222                         enable-method = "psci";
 223                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 224                                            &LITTLE_CPU_SLEEP_1
 225                                            &CLUSTER_SLEEP_0>;
 226                         capacity-dmips-mhz = <1024>;
 227                         dynamic-power-coefficient = <100>;
 228                         next-level-cache = <&L2_400>;
 229                         operating-points-v2 = <&cpu0_opp_table>;
 230                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 231                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 232                         #cooling-cells = <2>;
 233                         qcom,freq-domain = <&cpufreq_hw 0>;
 234                         L2_400: l2-cache {
 235                                 compatible = "cache";
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 CPU5: cpu@500 {
 241                         device_type = "cpu";
 242                         compatible = "qcom,kryo468";
 243                         reg = <0x0 0x500>;
 244                         enable-method = "psci";
 245                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 246                                            &LITTLE_CPU_SLEEP_1
 247                                            &CLUSTER_SLEEP_0>;
 248                         capacity-dmips-mhz = <1024>;
 249                         dynamic-power-coefficient = <100>;
 250                         next-level-cache = <&L2_500>;
 251                         operating-points-v2 = <&cpu0_opp_table>;
 252                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 253                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 254                         #cooling-cells = <2>;
 255                         qcom,freq-domain = <&cpufreq_hw 0>;
 256                         L2_500: l2-cache {
 257                                 compatible = "cache";
 258                                 next-level-cache = <&L3_0>;
 259                         };
 260                 };
 261
 262                 CPU6: cpu@600 {
 263                         device_type = "cpu";
 264                         compatible = "qcom,kryo468";
 265                         reg = <0x0 0x600>;
 266                         enable-method = "psci";
 267                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 268                                            &BIG_CPU_SLEEP_1
 269                                            &CLUSTER_SLEEP_0>;
 270                         capacity-dmips-mhz = <1740>;
 271                         dynamic-power-coefficient = <405>;
 272                         next-level-cache = <&L2_600>;
 273                         operating-points-v2 = <&cpu6_opp_table>;
 274                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 275                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 276                         #cooling-cells = <2>;
 277                         qcom,freq-domain = <&cpufreq_hw 1>;
 278                         L2_600: l2-cache {
 279                                 compatible = "cache";
 280                                 next-level-cache = <&L3_0>;
 281                         };
 282                 };
 283
 284                 CPU7: cpu@700 {
 285                         device_type = "cpu";
 286                         compatible = "qcom,kryo468";
 287                         reg = <0x0 0x700>;
 288                         enable-method = "psci";
 289                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 290                                            &BIG_CPU_SLEEP_1
 291                                            &CLUSTER_SLEEP_0>;
 292                         capacity-dmips-mhz = <1740>;
 293                         dynamic-power-coefficient = <405>;
 294                         next-level-cache = <&L2_700>;
 295                         operating-points-v2 = <&cpu6_opp_table>;
 296                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 297                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 298                         #cooling-cells = <2>;
 299                         qcom,freq-domain = <&cpufreq_hw 1>;
 300                         L2_700: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 cpu-map {
 307                         cluster0 {
 308                                 core0 {
 309                                         cpu = <&CPU0>;
 310                                 };
 311
 312                                 core1 {
 313                                         cpu = <&CPU1>;
 314                                 };
 315
 316                                 core2 {
 317                                         cpu = <&CPU2>;
 318                                 };
 319
 320                                 core3 {
 321                                         cpu = <&CPU3>;
 322                                 };
 323
 324                                 core4 {
 325                                         cpu = <&CPU4>;
 326                                 };
 327
 328                                 core5 {
 329                                         cpu = <&CPU5>;
 330                                 };
 331
 332                                 core6 {
 333                                         cpu = <&CPU6>;
 334                                 };
 335
 336                                 core7 {
 337                                         cpu = <&CPU7>;
 338                                 };
 339                         };
 340                 };
 341
 342                 idle-states {
 343                         entry-method = "psci";
 344
 345                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 346                                 compatible = "arm,idle-state";
 347                                 idle-state-name = "little-power-down";
 348                                 arm,psci-suspend-param = <0x40000003>;
 349                                 entry-latency-us = <549>;
 350                                 exit-latency-us = <901>;
 351                                 min-residency-us = <1774>;
 352                                 local-timer-stop;
 353                         };
 354
 355                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 356                                 compatible = "arm,idle-state";
 357                                 idle-state-name = "little-rail-power-down";
 358                                 arm,psci-suspend-param = <0x40000004>;
 359                                 entry-latency-us = <702>;
 360                                 exit-latency-us = <915>;
 361                                 min-residency-us = <4001>;
 362                                 local-timer-stop;
 363                         };
 364
 365                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 366                                 compatible = "arm,idle-state";
 367                                 idle-state-name = "big-power-down";
 368                                 arm,psci-suspend-param = <0x40000003>;
 369                                 entry-latency-us = <523>;
 370                                 exit-latency-us = <1244>;
 371                                 min-residency-us = <2207>;
 372                                 local-timer-stop;
 373                         };
 374
 375                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 376                                 compatible = "arm,idle-state";
 377                                 idle-state-name = "big-rail-power-down";
 378                                 arm,psci-suspend-param = <0x40000004>;
 379                                 entry-latency-us = <526>;
 380                                 exit-latency-us = <1854>;
 381                                 min-residency-us = <5555>;
 382                                 local-timer-stop;
 383                         };
 384
 385                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 386                                 compatible = "arm,idle-state";
 387                                 idle-state-name = "cluster-power-down";
 388                                 arm,psci-suspend-param = <0x40003444>;
 389                                 entry-latency-us = <3263>;
 390                                 exit-latency-us = <6562>;
 391                                 min-residency-us = <9926>;
 392                                 local-timer-stop;
 393                         };
 394                 };
 395         };
 396
 397         cpu0_opp_table: cpu0_opp_table {
 398                 compatible = "operating-points-v2";
 399                 opp-shared;
 400
 401                 cpu0_opp1: opp-300000000 {
 402                         opp-hz = /bits/ 64 <300000000>;
 403                         opp-peak-kBps = <1200000 4800000>;
 404                 };
 405
 406                 cpu0_opp2: opp-576000000 {
 407                         opp-hz = /bits/ 64 <576000000>;
 408                         opp-peak-kBps = <1200000 4800000>;
 409                 };
 410
 411                 cpu0_opp3: opp-768000000 {
 412                         opp-hz = /bits/ 64 <768000000>;
 413                         opp-peak-kBps = <1200000 4800000>;
 414                 };
 415
 416                 cpu0_opp4: opp-1017600000 {
 417                         opp-hz = /bits/ 64 <1017600000>;
 418                         opp-peak-kBps = <1804000 8908800>;
 419                 };
 420
 421                 cpu0_opp5: opp-1248000000 {
 422                         opp-hz = /bits/ 64 <1248000000>;
 423                         opp-peak-kBps = <2188000 12902400>;
 424                 };
 425
 426                 cpu0_opp6: opp-1324800000 {
 427                         opp-hz = /bits/ 64 <1324800000>;
 428                         opp-peak-kBps = <2188000 12902400>;
 429                 };
 430
 431                 cpu0_opp7: opp-1516800000 {
 432                         opp-hz = /bits/ 64 <1516800000>;
 433                         opp-peak-kBps = <3072000 15052800>;
 434                 };
 435
 436                 cpu0_opp8: opp-1612800000 {
 437                         opp-hz = /bits/ 64 <1612800000>;
 438                         opp-peak-kBps = <3072000 15052800>;
 439                 };
 440
 441                 cpu0_opp9: opp-1708800000 {
 442                         opp-hz = /bits/ 64 <1708800000>;
 443                         opp-peak-kBps = <3072000 15052800>;
 444                 };
 445
 446                 cpu0_opp10: opp-1804800000 {
 447                         opp-hz = /bits/ 64 <1804800000>;
 448                         opp-peak-kBps = <4068000 22425600>;
 449                 };
 450         };
 451
 452         cpu6_opp_table: cpu6_opp_table {
 453                 compatible = "operating-points-v2";
 454                 opp-shared;
 455
 456                 cpu6_opp1: opp-300000000 {
 457                         opp-hz = /bits/ 64 <300000000>;
 458                         opp-peak-kBps = <2188000 8908800>;
 459                 };
 460
 461                 cpu6_opp2: opp-652800000 {
 462                         opp-hz = /bits/ 64 <652800000>;
 463                         opp-peak-kBps = <2188000 8908800>;
 464                 };
 465
 466                 cpu6_opp3: opp-825600000 {
 467                         opp-hz = /bits/ 64 <825600000>;
 468                         opp-peak-kBps = <2188000 8908800>;
 469                 };
 470
 471                 cpu6_opp4: opp-979200000 {
 472                         opp-hz = /bits/ 64 <979200000>;
 473                         opp-peak-kBps = <2188000 8908800>;
 474                 };
 475
 476                 cpu6_opp5: opp-1113600000 {
 477                         opp-hz = /bits/ 64 <1113600000>;
 478                         opp-peak-kBps = <2188000 8908800>;
 479                 };
 480
 481                 cpu6_opp6: opp-1267200000 {
 482                         opp-hz = /bits/ 64 <1267200000>;
 483                         opp-peak-kBps = <4068000 12902400>;
 484                 };
 485
 486                 cpu6_opp7: opp-1555200000 {
 487                         opp-hz = /bits/ 64 <1555200000>;
 488                         opp-peak-kBps = <4068000 15052800>;
 489                 };
 490
 491                 cpu6_opp8: opp-1708800000 {
 492                         opp-hz = /bits/ 64 <1708800000>;
 493                         opp-peak-kBps = <6220000 19353600>;
 494                 };
 495
 496                 cpu6_opp9: opp-1843200000 {
 497                         opp-hz = /bits/ 64 <1843200000>;
 498                         opp-peak-kBps = <6220000 19353600>;
 499                 };
 500
 501                 cpu6_opp10: opp-1900800000 {
 502                         opp-hz = /bits/ 64 <1900800000>;
 503                         opp-peak-kBps = <6220000 22425600>;
 504                 };
 505
 506                 cpu6_opp11: opp-1996800000 {
 507                         opp-hz = /bits/ 64 <1996800000>;
 508                         opp-peak-kBps = <6220000 22425600>;
 509                 };
 510
 511                 cpu6_opp12: opp-2112000000 {
 512                         opp-hz = /bits/ 64 <2112000000>;
 513                         opp-peak-kBps = <6220000 22425600>;
 514                 };
 515
 516                 cpu6_opp13: opp-2208000000 {
 517                         opp-hz = /bits/ 64 <2208000000>;
 518                         opp-peak-kBps = <7216000 22425600>;
 519                 };
 520
 521                 cpu6_opp14: opp-2323200000 {
 522                         opp-hz = /bits/ 64 <2323200000>;
 523                         opp-peak-kBps = <7216000 22425600>;
 524                 };
 525
 526                 cpu6_opp15: opp-2400000000 {
 527                         opp-hz = /bits/ 64 <2400000000>;
 528                         opp-peak-kBps = <8532000 23347200>;
 529                 };
 530
 531                 cpu6_opp16: opp-2553600000 {
 532                         opp-hz = /bits/ 64 <2553600000>;
 533                         opp-peak-kBps = <8532000 23347200>;
 534                 };
 535         };
 536
 537         memory@80000000 {
 538                 device_type = "memory";
 539                 /* We expect the bootloader to fill in the size */
 540                 reg = <0 0x80000000 0 0>;
 541         };
 542
 543         pmu {
 544                 compatible = "arm,armv8-pmuv3";
 545                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 546         };
 547
 548         firmware {
 549                 scm {
 550                         compatible = "qcom,scm-sc7180", "qcom,scm";
 551                 };
 552         };
 553
 554         tcsr_mutex: hwlock {
 555                 compatible = "qcom,tcsr-mutex";
 556                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 557                 #hwlock-cells = <1>;
 558         };
 559
 560         smem {
 561                 compatible = "qcom,smem";
 562                 memory-region = <&smem_mem>;
 563                 hwlocks = <&tcsr_mutex 3>;
 564         };
 565
 566         smp2p-cdsp {
 567                 compatible = "qcom,smp2p";
 568                 qcom,smem = <94>, <432>;
 569
 570                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 571
 572                 mboxes = <&apss_shared 6>;
 573
 574                 qcom,local-pid = <0>;
 575                 qcom,remote-pid = <5>;
 576
 577                 cdsp_smp2p_out: master-kernel {
 578                         qcom,entry-name = "master-kernel";
 579                         #qcom,smem-state-cells = <1>;
 580                 };
 581
 582                 cdsp_smp2p_in: slave-kernel {
 583                         qcom,entry-name = "slave-kernel";
 584
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                 };
 588         };
 589
 590         smp2p-lpass {
 591                 compatible = "qcom,smp2p";
 592                 qcom,smem = <443>, <429>;
 593
 594                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 595
 596                 mboxes = <&apss_shared 10>;
 597
 598                 qcom,local-pid = <0>;
 599                 qcom,remote-pid = <2>;
 600
 601                 adsp_smp2p_out: master-kernel {
 602                         qcom,entry-name = "master-kernel";
 603                         #qcom,smem-state-cells = <1>;
 604                 };
 605
 606                 adsp_smp2p_in: slave-kernel {
 607                         qcom,entry-name = "slave-kernel";
 608
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                 };
 612         };
 613
 614         smp2p-mpss {
 615                 compatible = "qcom,smp2p";
 616                 qcom,smem = <435>, <428>;
 617                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 618                 mboxes = <&apss_shared 14>;
 619                 qcom,local-pid = <0>;
 620                 qcom,remote-pid = <1>;
 621
 622                 modem_smp2p_out: master-kernel {
 623                         qcom,entry-name = "master-kernel";
 624                         #qcom,smem-state-cells = <1>;
 625                 };
 626
 627                 modem_smp2p_in: slave-kernel {
 628                         qcom,entry-name = "slave-kernel";
 629                         interrupt-controller;
 630                         #interrupt-cells = <2>;
 631                 };
 632
 633                 ipa_smp2p_out: ipa-ap-to-modem {
 634                         qcom,entry-name = "ipa";
 635                         #qcom,smem-state-cells = <1>;
 636                 };
 637
 638                 ipa_smp2p_in: ipa-modem-to-ap {
 639                         qcom,entry-name = "ipa";
 640                         interrupt-controller;
 641                         #interrupt-cells = <2>;
 642                 };
 643         };
 644
 645         psci {
 646                 compatible = "arm,psci-1.0";
 647                 method = "smc";
 648         };
 649
 650         soc: soc@0 {
 651                 #address-cells = <2>;
 652                 #size-cells = <2>;
 653                 ranges = <0 0 0 0 0x10 0>;
 654                 dma-ranges = <0 0 0 0 0x10 0>;
 655                 compatible = "simple-bus";
 656
 657                 gcc: clock-controller@100000 {
 658                         compatible = "qcom,gcc-sc7180";
 659                         reg = <0 0x00100000 0 0x1f0000>;
 660                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 661                                  <&rpmhcc RPMH_CXO_CLK_A>,
 662                                  <&sleep_clk>;
 663                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 664                         #clock-cells = <1>;
 665                         #reset-cells = <1>;
 666                         #power-domain-cells = <1>;
 667                 };
 668
 669                 qfprom: efuse@784000 {
 670                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 671                         reg = <0 0x00784000 0 0x8ff>,
 672                               <0 0x00780000 0 0x7a0>,
 673                               <0 0x00782000 0 0x100>,
 674                               <0 0x00786000 0 0x1fff>;
 675
 676                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 677                         clock-names = "core";
 678                         #address-cells = <1>;
 679                         #size-cells = <1>;
 680
 681                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 682                                 reg = <0x25b 0x1>;
 683                                 bits = <1 3>;
 684                         };
 685
 686                         gpu_speed_bin: gpu_speed_bin@1d2 {
 687                                 reg = <0x1d2 0x2>;
 688                                 bits = <5 8>;
 689                         };
 690                 };
 691
 692                 sdhc_1: sdhci@7c4000 {
 693                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 694                         reg = <0 0x7c4000 0 0x1000>,
 695                                 <0 0x07c5000 0 0x1000>;
 696                         reg-names = "hc", "cqhci";
 697
 698                         iommus = <&apps_smmu 0x60 0x0>;
 699                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 700                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 701                         interrupt-names = "hc_irq", "pwr_irq";
 702
 703                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 704                                         <&gcc GCC_SDCC1_AHB_CLK>;
 705                         clock-names = "core", "iface";
 706                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 707                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 708                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 709                         power-domains = <&rpmhpd SC7180_CX>;
 710                         operating-points-v2 = <&sdhc1_opp_table>;
 711
 712                         bus-width = <8>;
 713                         non-removable;
 714                         supports-cqe;
 715
 716                         mmc-ddr-1_8v;
 717                         mmc-hs200-1_8v;
 718                         mmc-hs400-1_8v;
 719                         mmc-hs400-enhanced-strobe;
 720
 721                         status = "disabled";
 722
 723                         sdhc1_opp_table: sdhc1-opp-table {
 724                                 compatible = "operating-points-v2";
 725
 726                                 opp-100000000 {
 727                                         opp-hz = /bits/ 64 <100000000>;
 728                                         required-opps = <&rpmhpd_opp_low_svs>;
 729                                         opp-peak-kBps = <100000 100000>;
 730                                         opp-avg-kBps = <100000 50000>;
 731                                 };
 732
 733                                 opp-384000000 {
 734                                         opp-hz = /bits/ 64 <384000000>;
 735                                         required-opps = <&rpmhpd_opp_svs_l1>;
 736                                         opp-peak-kBps = <600000 900000>;
 737                                         opp-avg-kBps = <261438 300000>;
 738                                 };
 739                         };
 740                 };
 741
 742                 qup_opp_table: qup-opp-table {
 743                         compatible = "operating-points-v2";
 744
 745                         opp-75000000 {
 746                                 opp-hz = /bits/ 64 <75000000>;
 747                                 required-opps = <&rpmhpd_opp_low_svs>;
 748                         };
 749
 750                         opp-100000000 {
 751                                 opp-hz = /bits/ 64 <100000000>;
 752                                 required-opps = <&rpmhpd_opp_svs>;
 753                         };
 754
 755                         opp-128000000 {
 756                                 opp-hz = /bits/ 64 <128000000>;
 757                                 required-opps = <&rpmhpd_opp_nom>;
 758                         };
 759                 };
 760
 761                 qupv3_id_0: geniqup@8c0000 {
 762                         compatible = "qcom,geni-se-qup";
 763                         reg = <0 0x008c0000 0 0x6000>;
 764                         clock-names = "m-ahb", "s-ahb";
 765                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 766                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 767                         #address-cells = <2>;
 768                         #size-cells = <2>;
 769                         ranges;
 770                         iommus = <&apps_smmu 0x43 0x0>;
 771                         interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
 772                         interconnect-names = "qup-core";
 773                         status = "disabled";
 774
 775                         i2c0: i2c@880000 {
 776                                 compatible = "qcom,geni-i2c";
 777                                 reg = <0 0x00880000 0 0x4000>;
 778                                 clock-names = "se";
 779                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 780                                 pinctrl-names = "default";
 781                                 pinctrl-0 = <&qup_i2c0_default>;
 782                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 783                                 #address-cells = <1>;
 784                                 #size-cells = <0>;
 785                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 786                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 787                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 788                                 interconnect-names = "qup-core", "qup-config",
 789                                                         "qup-memory";
 790                                 status = "disabled";
 791                         };
 792
 793                         spi0: spi@880000 {
 794                                 compatible = "qcom,geni-spi";
 795                                 reg = <0 0x00880000 0 0x4000>;
 796                                 clock-names = "se";
 797                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 798                                 pinctrl-names = "default";
 799                                 pinctrl-0 = <&qup_spi0_default>;
 800                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 801                                 #address-cells = <1>;
 802                                 #size-cells = <0>;
 803                                 power-domains = <&rpmhpd SC7180_CX>;
 804                                 operating-points-v2 = <&qup_opp_table>;
 805                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 806                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 807                                 interconnect-names = "qup-core", "qup-config";
 808                                 status = "disabled";
 809                         };
 810
 811                         uart0: serial@880000 {
 812                                 compatible = "qcom,geni-uart";
 813                                 reg = <0 0x00880000 0 0x4000>;
 814                                 clock-names = "se";
 815                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 816                                 pinctrl-names = "default";
 817                                 pinctrl-0 = <&qup_uart0_default>;
 818                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 819                                 power-domains = <&rpmhpd SC7180_CX>;
 820                                 operating-points-v2 = <&qup_opp_table>;
 821                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 822                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 823                                 interconnect-names = "qup-core", "qup-config";
 824                                 status = "disabled";
 825                         };
 826
 827                         i2c1: i2c@884000 {
 828                                 compatible = "qcom,geni-i2c";
 829                                 reg = <0 0x00884000 0 0x4000>;
 830                                 clock-names = "se";
 831                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 832                                 pinctrl-names = "default";
 833                                 pinctrl-0 = <&qup_i2c1_default>;
 834                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 835                                 #address-cells = <1>;
 836                                 #size-cells = <0>;
 837                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 838                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 839                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 840                                 interconnect-names = "qup-core", "qup-config",
 841                                                         "qup-memory";
 842                                 status = "disabled";
 843                         };
 844
 845                         spi1: spi@884000 {
 846                                 compatible = "qcom,geni-spi";
 847                                 reg = <0 0x00884000 0 0x4000>;
 848                                 clock-names = "se";
 849                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 850                                 pinctrl-names = "default";
 851                                 pinctrl-0 = <&qup_spi1_default>;
 852                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 853                                 #address-cells = <1>;
 854                                 #size-cells = <0>;
 855                                 power-domains = <&rpmhpd SC7180_CX>;
 856                                 operating-points-v2 = <&qup_opp_table>;
 857                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 858                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 859                                 interconnect-names = "qup-core", "qup-config";
 860                                 status = "disabled";
 861                         };
 862
 863                         uart1: serial@884000 {
 864                                 compatible = "qcom,geni-uart";
 865                                 reg = <0 0x00884000 0 0x4000>;
 866                                 clock-names = "se";
 867                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 868                                 pinctrl-names = "default";
 869                                 pinctrl-0 = <&qup_uart1_default>;
 870                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 871                                 power-domains = <&rpmhpd SC7180_CX>;
 872                                 operating-points-v2 = <&qup_opp_table>;
 873                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 874                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 875                                 interconnect-names = "qup-core", "qup-config";
 876                                 status = "disabled";
 877                         };
 878
 879                         i2c2: i2c@888000 {
 880                                 compatible = "qcom,geni-i2c";
 881                                 reg = <0 0x00888000 0 0x4000>;
 882                                 clock-names = "se";
 883                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 884                                 pinctrl-names = "default";
 885                                 pinctrl-0 = <&qup_i2c2_default>;
 886                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 887                                 #address-cells = <1>;
 888                                 #size-cells = <0>;
 889                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 890                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 891                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 892                                 interconnect-names = "qup-core", "qup-config",
 893                                                         "qup-memory";
 894                                 status = "disabled";
 895                         };
 896
 897                         uart2: serial@888000 {
 898                                 compatible = "qcom,geni-uart";
 899                                 reg = <0 0x00888000 0 0x4000>;
 900                                 clock-names = "se";
 901                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 902                                 pinctrl-names = "default";
 903                                 pinctrl-0 = <&qup_uart2_default>;
 904                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 905                                 power-domains = <&rpmhpd SC7180_CX>;
 906                                 operating-points-v2 = <&qup_opp_table>;
 907                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 908                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 909                                 interconnect-names = "qup-core", "qup-config";
 910                                 status = "disabled";
 911                         };
 912
 913                         i2c3: i2c@88c000 {
 914                                 compatible = "qcom,geni-i2c";
 915                                 reg = <0 0x0088c000 0 0x4000>;
 916                                 clock-names = "se";
 917                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 918                                 pinctrl-names = "default";
 919                                 pinctrl-0 = <&qup_i2c3_default>;
 920                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 921                                 #address-cells = <1>;
 922                                 #size-cells = <0>;
 923                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 924                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 925                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 926                                 interconnect-names = "qup-core", "qup-config",
 927                                                         "qup-memory";
 928                                 status = "disabled";
 929                         };
 930
 931                         spi3: spi@88c000 {
 932                                 compatible = "qcom,geni-spi";
 933                                 reg = <0 0x0088c000 0 0x4000>;
 934                                 clock-names = "se";
 935                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 936                                 pinctrl-names = "default";
 937                                 pinctrl-0 = <&qup_spi3_default>;
 938                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 939                                 #address-cells = <1>;
 940                                 #size-cells = <0>;
 941                                 power-domains = <&rpmhpd SC7180_CX>;
 942                                 operating-points-v2 = <&qup_opp_table>;
 943                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 944                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 945                                 interconnect-names = "qup-core", "qup-config";
 946                                 status = "disabled";
 947                         };
 948
 949                         uart3: serial@88c000 {
 950                                 compatible = "qcom,geni-uart";
 951                                 reg = <0 0x0088c000 0 0x4000>;
 952                                 clock-names = "se";
 953                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 954                                 pinctrl-names = "default";
 955                                 pinctrl-0 = <&qup_uart3_default>;
 956                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 957                                 power-domains = <&rpmhpd SC7180_CX>;
 958                                 operating-points-v2 = <&qup_opp_table>;
 959                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 960                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 961                                 interconnect-names = "qup-core", "qup-config";
 962                                 status = "disabled";
 963                         };
 964
 965                         i2c4: i2c@890000 {
 966                                 compatible = "qcom,geni-i2c";
 967                                 reg = <0 0x00890000 0 0x4000>;
 968                                 clock-names = "se";
 969                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 970                                 pinctrl-names = "default";
 971                                 pinctrl-0 = <&qup_i2c4_default>;
 972                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 973                                 #address-cells = <1>;
 974                                 #size-cells = <0>;
 975                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 976                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 977                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 978                                 interconnect-names = "qup-core", "qup-config",
 979                                                         "qup-memory";
 980                                 status = "disabled";
 981                         };
 982
 983                         uart4: serial@890000 {
 984                                 compatible = "qcom,geni-uart";
 985                                 reg = <0 0x00890000 0 0x4000>;
 986                                 clock-names = "se";
 987                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 988                                 pinctrl-names = "default";
 989                                 pinctrl-0 = <&qup_uart4_default>;
 990                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 991                                 power-domains = <&rpmhpd SC7180_CX>;
 992                                 operating-points-v2 = <&qup_opp_table>;
 993                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 994                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 995                                 interconnect-names = "qup-core", "qup-config";
 996                                 status = "disabled";
 997                         };
 998
 999                         i2c5: i2c@894000 {
1000                                 compatible = "qcom,geni-i2c";
1001                                 reg = <0 0x00894000 0 0x4000>;
1002                                 clock-names = "se";
1003                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1004                                 pinctrl-names = "default";
1005                                 pinctrl-0 = <&qup_i2c5_default>;
1006                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1007                                 #address-cells = <1>;
1008                                 #size-cells = <0>;
1009                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1010                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1011                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1012                                 interconnect-names = "qup-core", "qup-config",
1013                                                         "qup-memory";
1014                                 status = "disabled";
1015                         };
1016
1017                         spi5: spi@894000 {
1018                                 compatible = "qcom,geni-spi";
1019                                 reg = <0 0x00894000 0 0x4000>;
1020                                 clock-names = "se";
1021                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1022                                 pinctrl-names = "default";
1023                                 pinctrl-0 = <&qup_spi5_default>;
1024                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1025                                 #address-cells = <1>;
1026                                 #size-cells = <0>;
1027                                 power-domains = <&rpmhpd SC7180_CX>;
1028                                 operating-points-v2 = <&qup_opp_table>;
1029                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1030                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1031                                 interconnect-names = "qup-core", "qup-config";
1032                                 status = "disabled";
1033                         };
1034
1035                         uart5: serial@894000 {
1036                                 compatible = "qcom,geni-uart";
1037                                 reg = <0 0x00894000 0 0x4000>;
1038                                 clock-names = "se";
1039                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1040                                 pinctrl-names = "default";
1041                                 pinctrl-0 = <&qup_uart5_default>;
1042                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1043                                 power-domains = <&rpmhpd SC7180_CX>;
1044                                 operating-points-v2 = <&qup_opp_table>;
1045                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1046                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1047                                 interconnect-names = "qup-core", "qup-config";
1048                                 status = "disabled";
1049                         };
1050                 };
1051
1052                 qupv3_id_1: geniqup@ac0000 {
1053                         compatible = "qcom,geni-se-qup";
1054                         reg = <0 0x00ac0000 0 0x6000>;
1055                         clock-names = "m-ahb", "s-ahb";
1056                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1057                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1058                         #address-cells = <2>;
1059                         #size-cells = <2>;
1060                         ranges;
1061                         iommus = <&apps_smmu 0x4c3 0x0>;
1062                         interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
1063                         interconnect-names = "qup-core";
1064                         status = "disabled";
1065
1066                         i2c6: i2c@a80000 {
1067                                 compatible = "qcom,geni-i2c";
1068                                 reg = <0 0x00a80000 0 0x4000>;
1069                                 clock-names = "se";
1070                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1071                                 pinctrl-names = "default";
1072                                 pinctrl-0 = <&qup_i2c6_default>;
1073                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1074                                 #address-cells = <1>;
1075                                 #size-cells = <0>;
1076                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1077                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1078                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1079                                 interconnect-names = "qup-core", "qup-config",
1080                                                         "qup-memory";
1081                                 status = "disabled";
1082                         };
1083
1084                         spi6: spi@a80000 {
1085                                 compatible = "qcom,geni-spi";
1086                                 reg = <0 0x00a80000 0 0x4000>;
1087                                 clock-names = "se";
1088                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1089                                 pinctrl-names = "default";
1090                                 pinctrl-0 = <&qup_spi6_default>;
1091                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1092                                 #address-cells = <1>;
1093                                 #size-cells = <0>;
1094                                 power-domains = <&rpmhpd SC7180_CX>;
1095                                 operating-points-v2 = <&qup_opp_table>;
1096                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1097                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1098                                 interconnect-names = "qup-core", "qup-config";
1099                                 status = "disabled";
1100                         };
1101
1102                         uart6: serial@a80000 {
1103                                 compatible = "qcom,geni-uart";
1104                                 reg = <0 0x00a80000 0 0x4000>;
1105                                 clock-names = "se";
1106                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1107                                 pinctrl-names = "default";
1108                                 pinctrl-0 = <&qup_uart6_default>;
1109                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1110                                 power-domains = <&rpmhpd SC7180_CX>;
1111                                 operating-points-v2 = <&qup_opp_table>;
1112                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1113                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1114                                 interconnect-names = "qup-core", "qup-config";
1115                                 status = "disabled";
1116                         };
1117
1118                         i2c7: i2c@a84000 {
1119                                 compatible = "qcom,geni-i2c";
1120                                 reg = <0 0x00a84000 0 0x4000>;
1121                                 clock-names = "se";
1122                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1123                                 pinctrl-names = "default";
1124                                 pinctrl-0 = <&qup_i2c7_default>;
1125                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1126                                 #address-cells = <1>;
1127                                 #size-cells = <0>;
1128                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1129                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1130                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1131                                 interconnect-names = "qup-core", "qup-config",
1132                                                         "qup-memory";
1133                                 status = "disabled";
1134                         };
1135
1136                         uart7: serial@a84000 {
1137                                 compatible = "qcom,geni-uart";
1138                                 reg = <0 0x00a84000 0 0x4000>;
1139                                 clock-names = "se";
1140                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1141                                 pinctrl-names = "default";
1142                                 pinctrl-0 = <&qup_uart7_default>;
1143                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1144                                 power-domains = <&rpmhpd SC7180_CX>;
1145                                 operating-points-v2 = <&qup_opp_table>;
1146                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1147                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1148                                 interconnect-names = "qup-core", "qup-config";
1149                                 status = "disabled";
1150                         };
1151
1152                         i2c8: i2c@a88000 {
1153                                 compatible = "qcom,geni-i2c";
1154                                 reg = <0 0x00a88000 0 0x4000>;
1155                                 clock-names = "se";
1156                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1157                                 pinctrl-names = "default";
1158                                 pinctrl-0 = <&qup_i2c8_default>;
1159                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1160                                 #address-cells = <1>;
1161                                 #size-cells = <0>;
1162                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1163                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1164                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1165                                 interconnect-names = "qup-core", "qup-config",
1166                                                         "qup-memory";
1167                                 status = "disabled";
1168                         };
1169
1170                         spi8: spi@a88000 {
1171                                 compatible = "qcom,geni-spi";
1172                                 reg = <0 0x00a88000 0 0x4000>;
1173                                 clock-names = "se";
1174                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1175                                 pinctrl-names = "default";
1176                                 pinctrl-0 = <&qup_spi8_default>;
1177                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1178                                 #address-cells = <1>;
1179                                 #size-cells = <0>;
1180                                 power-domains = <&rpmhpd SC7180_CX>;
1181                                 operating-points-v2 = <&qup_opp_table>;
1182                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1183                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1184                                 interconnect-names = "qup-core", "qup-config";
1185                                 status = "disabled";
1186                         };
1187
1188                         uart8: serial@a88000 {
1189                                 compatible = "qcom,geni-debug-uart";
1190                                 reg = <0 0x00a88000 0 0x4000>;
1191                                 clock-names = "se";
1192                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1193                                 pinctrl-names = "default";
1194                                 pinctrl-0 = <&qup_uart8_default>;
1195                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1196                                 power-domains = <&rpmhpd SC7180_CX>;
1197                                 operating-points-v2 = <&qup_opp_table>;
1198                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1199                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1200                                 interconnect-names = "qup-core", "qup-config";
1201                                 status = "disabled";
1202                         };
1203
1204                         i2c9: i2c@a8c000 {
1205                                 compatible = "qcom,geni-i2c";
1206                                 reg = <0 0x00a8c000 0 0x4000>;
1207                                 clock-names = "se";
1208                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1209                                 pinctrl-names = "default";
1210                                 pinctrl-0 = <&qup_i2c9_default>;
1211                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1212                                 #address-cells = <1>;
1213                                 #size-cells = <0>;
1214                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1215                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1216                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1217                                 interconnect-names = "qup-core", "qup-config",
1218                                                         "qup-memory";
1219                                 status = "disabled";
1220                         };
1221
1222                         uart9: serial@a8c000 {
1223                                 compatible = "qcom,geni-uart";
1224                                 reg = <0 0x00a8c000 0 0x4000>;
1225                                 clock-names = "se";
1226                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1227                                 pinctrl-names = "default";
1228                                 pinctrl-0 = <&qup_uart9_default>;
1229                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1230                                 power-domains = <&rpmhpd SC7180_CX>;
1231                                 operating-points-v2 = <&qup_opp_table>;
1232                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1233                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1234                                 interconnect-names = "qup-core", "qup-config";
1235                                 status = "disabled";
1236                         };
1237
1238                         i2c10: i2c@a90000 {
1239                                 compatible = "qcom,geni-i2c";
1240                                 reg = <0 0x00a90000 0 0x4000>;
1241                                 clock-names = "se";
1242                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1243                                 pinctrl-names = "default";
1244                                 pinctrl-0 = <&qup_i2c10_default>;
1245                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1246                                 #address-cells = <1>;
1247                                 #size-cells = <0>;
1248                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1249                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1250                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1251                                 interconnect-names = "qup-core", "qup-config",
1252                                                         "qup-memory";
1253                                 status = "disabled";
1254                         };
1255
1256                         spi10: spi@a90000 {
1257                                 compatible = "qcom,geni-spi";
1258                                 reg = <0 0x00a90000 0 0x4000>;
1259                                 clock-names = "se";
1260                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1261                                 pinctrl-names = "default";
1262                                 pinctrl-0 = <&qup_spi10_default>;
1263                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1264                                 #address-cells = <1>;
1265                                 #size-cells = <0>;
1266                                 power-domains = <&rpmhpd SC7180_CX>;
1267                                 operating-points-v2 = <&qup_opp_table>;
1268                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1269                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1270                                 interconnect-names = "qup-core", "qup-config";
1271                                 status = "disabled";
1272                         };
1273
1274                         uart10: serial@a90000 {
1275                                 compatible = "qcom,geni-uart";
1276                                 reg = <0 0x00a90000 0 0x4000>;
1277                                 clock-names = "se";
1278                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1279                                 pinctrl-names = "default";
1280                                 pinctrl-0 = <&qup_uart10_default>;
1281                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1282                                 power-domains = <&rpmhpd SC7180_CX>;
1283                                 operating-points-v2 = <&qup_opp_table>;
1284                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1285                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1286                                 interconnect-names = "qup-core", "qup-config";
1287                                 status = "disabled";
1288                         };
1289
1290                         i2c11: i2c@a94000 {
1291                                 compatible = "qcom,geni-i2c";
1292                                 reg = <0 0x00a94000 0 0x4000>;
1293                                 clock-names = "se";
1294                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1295                                 pinctrl-names = "default";
1296                                 pinctrl-0 = <&qup_i2c11_default>;
1297                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1298                                 #address-cells = <1>;
1299                                 #size-cells = <0>;
1300                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1301                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1302                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1303                                 interconnect-names = "qup-core", "qup-config",
1304                                                         "qup-memory";
1305                                 status = "disabled";
1306                         };
1307
1308                         spi11: spi@a94000 {
1309                                 compatible = "qcom,geni-spi";
1310                                 reg = <0 0x00a94000 0 0x4000>;
1311                                 clock-names = "se";
1312                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1313                                 pinctrl-names = "default";
1314                                 pinctrl-0 = <&qup_spi11_default>;
1315                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1316                                 #address-cells = <1>;
1317                                 #size-cells = <0>;
1318                                 power-domains = <&rpmhpd SC7180_CX>;
1319                                 operating-points-v2 = <&qup_opp_table>;
1320                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1321                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1322                                 interconnect-names = "qup-core", "qup-config";
1323                                 status = "disabled";
1324                         };
1325
1326                         uart11: serial@a94000 {
1327                                 compatible = "qcom,geni-uart";
1328                                 reg = <0 0x00a94000 0 0x4000>;
1329                                 clock-names = "se";
1330                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1331                                 pinctrl-names = "default";
1332                                 pinctrl-0 = <&qup_uart11_default>;
1333                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1334                                 power-domains = <&rpmhpd SC7180_CX>;
1335                                 operating-points-v2 = <&qup_opp_table>;
1336                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1337                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1338                                 interconnect-names = "qup-core", "qup-config";
1339                                 status = "disabled";
1340                         };
1341                 };
1342
1343                 config_noc: interconnect@1500000 {
1344                         compatible = "qcom,sc7180-config-noc";
1345                         reg = <0 0x01500000 0 0x28000>;
1346                         #interconnect-cells = <2>;
1347                         qcom,bcm-voters = <&apps_bcm_voter>;
1348                 };
1349
1350                 system_noc: interconnect@1620000 {
1351                         compatible = "qcom,sc7180-system-noc";
1352                         reg = <0 0x01620000 0 0x17080>;
1353                         #interconnect-cells = <2>;
1354                         qcom,bcm-voters = <&apps_bcm_voter>;
1355                 };
1356
1357                 mc_virt: interconnect@1638000 {
1358                         compatible = "qcom,sc7180-mc-virt";
1359                         reg = <0 0x01638000 0 0x1000>;
1360                         #interconnect-cells = <2>;
1361                         qcom,bcm-voters = <&apps_bcm_voter>;
1362                 };
1363
1364                 qup_virt: interconnect@1650000 {
1365                         compatible = "qcom,sc7180-qup-virt";
1366                         reg = <0 0x01650000 0 0x1000>;
1367                         #interconnect-cells = <2>;
1368                         qcom,bcm-voters = <&apps_bcm_voter>;
1369                 };
1370
1371                 aggre1_noc: interconnect@16e0000 {
1372                         compatible = "qcom,sc7180-aggre1-noc";
1373                         reg = <0 0x016e0000 0 0x15080>;
1374                         #interconnect-cells = <2>;
1375                         qcom,bcm-voters = <&apps_bcm_voter>;
1376                 };
1377
1378                 aggre2_noc: interconnect@1705000 {
1379                         compatible = "qcom,sc7180-aggre2-noc";
1380                         reg = <0 0x01705000 0 0x9000>;
1381                         #interconnect-cells = <2>;
1382                         qcom,bcm-voters = <&apps_bcm_voter>;
1383                 };
1384
1385                 compute_noc: interconnect@170e000 {
1386                         compatible = "qcom,sc7180-compute-noc";
1387                         reg = <0 0x0170e000 0 0x6000>;
1388                         #interconnect-cells = <2>;
1389                         qcom,bcm-voters = <&apps_bcm_voter>;
1390                 };
1391
1392                 mmss_noc: interconnect@1740000 {
1393                         compatible = "qcom,sc7180-mmss-noc";
1394                         reg = <0 0x01740000 0 0x1c100>;
1395                         #interconnect-cells = <2>;
1396                         qcom,bcm-voters = <&apps_bcm_voter>;
1397                 };
1398
1399                 ipa_virt: interconnect@1e00000 {
1400                         compatible = "qcom,sc7180-ipa-virt";
1401                         reg = <0 0x01e00000 0 0x1000>;
1402                         #interconnect-cells = <2>;
1403                         qcom,bcm-voters = <&apps_bcm_voter>;
1404                 };
1405
1406                 ipa: ipa@1e40000 {
1407                         compatible = "qcom,sc7180-ipa";
1408
1409                         iommus = <&apps_smmu 0x440 0x0>,
1410                                  <&apps_smmu 0x442 0x0>;
1411                         reg = <0 0x1e40000 0 0x7000>,
1412                               <0 0x1e47000 0 0x2000>,
1413                               <0 0x1e04000 0 0x2c000>;
1414                         reg-names = "ipa-reg",
1415                                     "ipa-shared",
1416                                     "gsi";
1417
1418                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1419                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1420                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1421                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1422                         interrupt-names = "ipa",
1423                                           "gsi",
1424                                           "ipa-clock-query",
1425                                           "ipa-setup-ready";
1426
1427                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1428                         clock-names = "core";
1429
1430                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1431                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1432                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1433                         interconnect-names = "memory",
1434                                              "imem",
1435                                              "config";
1436
1437                         qcom,smem-states = <&ipa_smp2p_out 0>,
1438                                            <&ipa_smp2p_out 1>;
1439                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1440                                                 "ipa-clock-enabled";
1441
1442                         status = "disabled";
1443                 };
1444
1445                 tcsr_mutex_regs: syscon@1f40000 {
1446                         compatible = "syscon";
1447                         reg = <0 0x01f40000 0 0x40000>;
1448                 };
1449
1450                 tcsr_regs: syscon@1fc0000 {
1451                         compatible = "syscon";
1452                         reg = <0 0x01fc0000 0 0x40000>;
1453                 };
1454
1455                 tlmm: pinctrl@3500000 {
1456                         compatible = "qcom,sc7180-pinctrl";
1457                         reg = <0 0x03500000 0 0x300000>,
1458                               <0 0x03900000 0 0x300000>,
1459                               <0 0x03d00000 0 0x300000>;
1460                         reg-names = "west", "north", "south";
1461                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1462                         gpio-controller;
1463                         #gpio-cells = <2>;
1464                         interrupt-controller;
1465                         #interrupt-cells = <2>;
1466                         gpio-ranges = <&tlmm 0 0 120>;
1467                         wakeup-parent = <&pdc>;
1468
1469                         dp_hot_plug_det: dp-hot-plug-det {
1470                                 pinmux {
1471                                         pins = "gpio117";
1472                                         function = "dp_hot";
1473                                 };
1474                         };
1475
1476                         qspi_clk: qspi-clk {
1477                                 pinmux {
1478                                         pins = "gpio63";
1479                                         function = "qspi_clk";
1480                                 };
1481                         };
1482
1483                         qspi_cs0: qspi-cs0 {
1484                                 pinmux {
1485                                         pins = "gpio68";
1486                                         function = "qspi_cs";
1487                                 };
1488                         };
1489
1490                         qspi_cs1: qspi-cs1 {
1491                                 pinmux {
1492                                         pins = "gpio72";
1493                                         function = "qspi_cs";
1494                                 };
1495                         };
1496
1497                         qspi_data01: qspi-data01 {
1498                                 pinmux-data {
1499                                         pins = "gpio64", "gpio65";
1500                                         function = "qspi_data";
1501                                 };
1502                         };
1503
1504                         qspi_data12: qspi-data12 {
1505                                 pinmux-data {
1506                                         pins = "gpio66", "gpio67";
1507                                         function = "qspi_data";
1508                                 };
1509                         };
1510
1511                         qup_i2c0_default: qup-i2c0-default {
1512                                 pinmux {
1513                                         pins = "gpio34", "gpio35";
1514                                         function = "qup00";
1515                                 };
1516                         };
1517
1518                         qup_i2c1_default: qup-i2c1-default {
1519                                 pinmux {
1520                                         pins = "gpio0", "gpio1";
1521                                         function = "qup01";
1522                                 };
1523                         };
1524
1525                         qup_i2c2_default: qup-i2c2-default {
1526                                 pinmux {
1527                                         pins = "gpio15", "gpio16";
1528                                         function = "qup02_i2c";
1529                                 };
1530                         };
1531
1532                         qup_i2c3_default: qup-i2c3-default {
1533                                 pinmux {
1534                                         pins = "gpio38", "gpio39";
1535                                         function = "qup03";
1536                                 };
1537                         };
1538
1539                         qup_i2c4_default: qup-i2c4-default {
1540                                 pinmux {
1541                                         pins = "gpio115", "gpio116";
1542                                         function = "qup04_i2c";
1543                                 };
1544                         };
1545
1546                         qup_i2c5_default: qup-i2c5-default {
1547                                 pinmux {
1548                                         pins = "gpio25", "gpio26";
1549                                         function = "qup05";
1550                                 };
1551                         };
1552
1553                         qup_i2c6_default: qup-i2c6-default {
1554                                 pinmux {
1555                                         pins = "gpio59", "gpio60";
1556                                         function = "qup10";
1557                                 };
1558                         };
1559
1560                         qup_i2c7_default: qup-i2c7-default {
1561                                 pinmux {
1562                                         pins = "gpio6", "gpio7";
1563                                         function = "qup11_i2c";
1564                                 };
1565                         };
1566
1567                         qup_i2c8_default: qup-i2c8-default {
1568                                 pinmux {
1569                                         pins = "gpio42", "gpio43";
1570                                         function = "qup12";
1571                                 };
1572                         };
1573
1574                         qup_i2c9_default: qup-i2c9-default {
1575                                 pinmux {
1576                                         pins = "gpio46", "gpio47";
1577                                         function = "qup13_i2c";
1578                                 };
1579                         };
1580
1581                         qup_i2c10_default: qup-i2c10-default {
1582                                 pinmux {
1583                                         pins = "gpio86", "gpio87";
1584                                         function = "qup14";
1585                                 };
1586                         };
1587
1588                         qup_i2c11_default: qup-i2c11-default {
1589                                 pinmux {
1590                                         pins = "gpio53", "gpio54";
1591                                         function = "qup15";
1592                                 };
1593                         };
1594
1595                         qup_spi0_default: qup-spi0-default {
1596                                 pinmux {
1597                                         pins = "gpio34", "gpio35",
1598                                                "gpio36", "gpio37";
1599                                         function = "qup00";
1600                                 };
1601                         };
1602
1603                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1604                                 pinmux {
1605                                         pins = "gpio34", "gpio35",
1606                                                "gpio36";
1607                                         function = "qup00";
1608                                 };
1609
1610                                 pinmux-cs {
1611                                         pins = "gpio37";
1612                                         function = "gpio";
1613                                 };
1614                         };
1615
1616                         qup_spi1_default: qup-spi1-default {
1617                                 pinmux {
1618                                         pins = "gpio0", "gpio1",
1619                                                "gpio2", "gpio3";
1620                                         function = "qup01";
1621                                 };
1622                         };
1623
1624                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1625                                 pinmux {
1626                                         pins = "gpio0", "gpio1",
1627                                                "gpio2";
1628                                         function = "qup01";
1629                                 };
1630
1631                                 pinmux-cs {
1632                                         pins = "gpio3";
1633                                         function = "gpio";
1634                                 };
1635                         };
1636
1637                         qup_spi3_default: qup-spi3-default {
1638                                 pinmux {
1639                                         pins = "gpio38", "gpio39",
1640                                                "gpio40", "gpio41";
1641                                         function = "qup03";
1642                                 };
1643                         };
1644
1645                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1646                                 pinmux {
1647                                         pins = "gpio38", "gpio39",
1648                                                "gpio40";
1649                                         function = "qup03";
1650                                 };
1651
1652                                 pinmux-cs {
1653                                         pins = "gpio41";
1654                                         function = "gpio";
1655                                 };
1656                         };
1657
1658                         qup_spi5_default: qup-spi5-default {
1659                                 pinmux {
1660                                         pins = "gpio25", "gpio26",
1661                                                "gpio27", "gpio28";
1662                                         function = "qup05";
1663                                 };
1664                         };
1665
1666                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1667                                 pinmux {
1668                                         pins = "gpio25", "gpio26",
1669                                                "gpio27";
1670                                         function = "qup05";
1671                                 };
1672
1673                                 pinmux-cs {
1674                                         pins = "gpio28";
1675                                         function = "gpio";
1676                                 };
1677                         };
1678
1679                         qup_spi6_default: qup-spi6-default {
1680                                 pinmux {
1681                                         pins = "gpio59", "gpio60",
1682                                                "gpio61", "gpio62";
1683                                         function = "qup10";
1684                                 };
1685                         };
1686
1687                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1688                                 pinmux {
1689                                         pins = "gpio59", "gpio60",
1690                                                "gpio61";
1691                                         function = "qup10";
1692                                 };
1693
1694                                 pinmux-cs {
1695                                         pins = "gpio62";
1696                                         function = "gpio";
1697                                 };
1698                         };
1699
1700                         qup_spi8_default: qup-spi8-default {
1701                                 pinmux {
1702                                         pins = "gpio42", "gpio43",
1703                                                "gpio44", "gpio45";
1704                                         function = "qup12";
1705                                 };
1706                         };
1707
1708                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1709                                 pinmux {
1710                                         pins = "gpio42", "gpio43",
1711                                                "gpio44";
1712                                         function = "qup12";
1713                                 };
1714
1715                                 pinmux-cs {
1716                                         pins = "gpio45";
1717                                         function = "gpio";
1718                                 };
1719                         };
1720
1721                         qup_spi10_default: qup-spi10-default {
1722                                 pinmux {
1723                                         pins = "gpio86", "gpio87",
1724                                                "gpio88", "gpio89";
1725                                         function = "qup14";
1726                                 };
1727                         };
1728
1729                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1730                                 pinmux {
1731                                         pins = "gpio86", "gpio87",
1732                                                "gpio88";
1733                                         function = "qup14";
1734                                 };
1735
1736                                 pinmux-cs {
1737                                         pins = "gpio89";
1738                                         function = "gpio";
1739                                 };
1740                         };
1741
1742                         qup_spi11_default: qup-spi11-default {
1743                                 pinmux {
1744                                         pins = "gpio53", "gpio54",
1745                                                "gpio55", "gpio56";
1746                                         function = "qup15";
1747                                 };
1748                         };
1749
1750                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1751                                 pinmux {
1752                                         pins = "gpio53", "gpio54",
1753                                                "gpio55";
1754                                         function = "qup15";
1755                                 };
1756
1757                                 pinmux-cs {
1758                                         pins = "gpio56";
1759                                         function = "gpio";
1760                                 };
1761                         };
1762
1763                         qup_uart0_default: qup-uart0-default {
1764                                 pinmux {
1765                                         pins = "gpio34", "gpio35",
1766                                                "gpio36", "gpio37";
1767                                         function = "qup00";
1768                                 };
1769                         };
1770
1771                         qup_uart1_default: qup-uart1-default {
1772                                 pinmux {
1773                                         pins = "gpio0", "gpio1",
1774                                                "gpio2", "gpio3";
1775                                         function = "qup01";
1776                                 };
1777                         };
1778
1779                         qup_uart2_default: qup-uart2-default {
1780                                 pinmux {
1781                                         pins = "gpio15", "gpio16";
1782                                         function = "qup02_uart";
1783                                 };
1784                         };
1785
1786                         qup_uart3_default: qup-uart3-default {
1787                                 pinmux {
1788                                         pins = "gpio38", "gpio39",
1789                                                "gpio40", "gpio41";
1790                                         function = "qup03";
1791                                 };
1792                         };
1793
1794                         qup_uart4_default: qup-uart4-default {
1795                                 pinmux {
1796                                         pins = "gpio115", "gpio116";
1797                                         function = "qup04_uart";
1798                                 };
1799                         };
1800
1801                         qup_uart5_default: qup-uart5-default {
1802                                 pinmux {
1803                                         pins = "gpio25", "gpio26",
1804                                                "gpio27", "gpio28";
1805                                         function = "qup05";
1806                                 };
1807                         };
1808
1809                         qup_uart6_default: qup-uart6-default {
1810                                 pinmux {
1811                                         pins = "gpio59", "gpio60",
1812                                                "gpio61", "gpio62";
1813                                         function = "qup10";
1814                                 };
1815                         };
1816
1817                         qup_uart7_default: qup-uart7-default {
1818                                 pinmux {
1819                                         pins = "gpio6", "gpio7";
1820                                         function = "qup11_uart";
1821                                 };
1822                         };
1823
1824                         qup_uart8_default: qup-uart8-default {
1825                                 pinmux {
1826                                         pins = "gpio44", "gpio45";
1827                                         function = "qup12";
1828                                 };
1829                         };
1830
1831                         qup_uart9_default: qup-uart9-default {
1832                                 pinmux {
1833                                         pins = "gpio46", "gpio47";
1834                                         function = "qup13_uart";
1835                                 };
1836                         };
1837
1838                         qup_uart10_default: qup-uart10-default {
1839                                 pinmux {
1840                                         pins = "gpio86", "gpio87",
1841                                                "gpio88", "gpio89";
1842                                         function = "qup14";
1843                                 };
1844                         };
1845
1846                         qup_uart11_default: qup-uart11-default {
1847                                 pinmux {
1848                                         pins = "gpio53", "gpio54",
1849                                                "gpio55", "gpio56";
1850                                         function = "qup15";
1851                                 };
1852                         };
1853
1854                         sec_mi2s_active: sec-mi2s-active {
1855                                 pinmux {
1856                                         pins = "gpio49", "gpio50", "gpio51";
1857                                         function = "mi2s_1";
1858                                 };
1859
1860                                 pinconf {
1861                                         pins = "gpio49", "gpio50", "gpio51";
1862                                         drive-strength = <8>;
1863                                         bias-pull-up;
1864                                 };
1865                         };
1866
1867                         pri_mi2s_active: pri-mi2s-active {
1868                                 pinmux {
1869                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1870                                         function = "mi2s_0";
1871                                 };
1872
1873                                 pinconf {
1874                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1875                                         drive-strength = <8>;
1876                                         bias-pull-up;
1877                                 };
1878                         };
1879
1880                         pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1881                                 pinmux {
1882                                         pins = "gpio57";
1883                                         function = "lpass_ext";
1884                                 };
1885
1886                                 pinconf {
1887                                         pins = "gpio57";
1888                                         drive-strength = <8>;
1889                                         bias-pull-up;
1890                                 };
1891                         };
1892
1893                         sdc1_on: sdc1-on {
1894                                 pinconf-clk {
1895                                         pins = "sdc1_clk";
1896                                         bias-disable;
1897                                         drive-strength = <16>;
1898                                 };
1899
1900                                 pinconf-cmd {
1901                                         pins = "sdc1_cmd";
1902                                         bias-pull-up;
1903                                         drive-strength = <10>;
1904                                 };
1905
1906                                 pinconf-data {
1907                                         pins = "sdc1_data";
1908                                         bias-pull-up;
1909                                         drive-strength = <10>;
1910                                 };
1911
1912                                 pinconf-rclk {
1913                                         pins = "sdc1_rclk";
1914                                         bias-pull-down;
1915                                 };
1916                         };
1917
1918                         sdc1_off: sdc1-off {
1919                                 pinconf-clk {
1920                                         pins = "sdc1_clk";
1921                                         bias-disable;
1922                                         drive-strength = <2>;
1923                                 };
1924
1925                                 pinconf-cmd {
1926                                         pins = "sdc1_cmd";
1927                                         bias-pull-up;
1928                                         drive-strength = <2>;
1929                                 };
1930
1931                                 pinconf-data {
1932                                         pins = "sdc1_data";
1933                                         bias-pull-up;
1934                                         drive-strength = <2>;
1935                                 };
1936
1937                                 pinconf-rclk {
1938                                         pins = "sdc1_rclk";
1939                                         bias-pull-down;
1940                                 };
1941                         };
1942
1943                         sdc2_on: sdc2-on {
1944                                 pinconf-clk {
1945                                         pins = "sdc2_clk";
1946                                         bias-disable;
1947                                         drive-strength = <16>;
1948                                 };
1949
1950                                 pinconf-cmd {
1951                                         pins = "sdc2_cmd";
1952                                         bias-pull-up;
1953                                         drive-strength = <10>;
1954                                 };
1955
1956                                 pinconf-data {
1957                                         pins = "sdc2_data";
1958                                         bias-pull-up;
1959                                         drive-strength = <10>;
1960                                 };
1961
1962                                 pinconf-sd-cd {
1963                                         pins = "gpio69";
1964                                         bias-pull-up;
1965                                         drive-strength = <2>;
1966                                 };
1967                         };
1968
1969                         sdc2_off: sdc2-off {
1970                                 pinconf-clk {
1971                                         pins = "sdc2_clk";
1972                                         bias-disable;
1973                                         drive-strength = <2>;
1974                                 };
1975
1976                                 pinconf-cmd {
1977                                         pins = "sdc2_cmd";
1978                                         bias-pull-up;
1979                                         drive-strength = <2>;
1980                                 };
1981
1982                                 pinconf-data {
1983                                         pins = "sdc2_data";
1984                                         bias-pull-up;
1985                                         drive-strength = <2>;
1986                                 };
1987
1988                                 pinconf-sd-cd {
1989                                         pins = "gpio69";
1990                                         bias-disable;
1991                                         drive-strength = <2>;
1992                                 };
1993                         };
1994                 };
1995
1996                 remoteproc_mpss: remoteproc@4080000 {
1997                         compatible = "qcom,sc7180-mpss-pas";
1998                         reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
1999                         reg-names = "qdsp6", "rmb";
2000
2001                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2002                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2003                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2004                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2005                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2006                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2007                         interrupt-names = "wdog", "fatal", "ready", "handover",
2008                                           "stop-ack", "shutdown-ack";
2009
2010                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2011                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2012                                  <&gcc GCC_MSS_NAV_AXI_CLK>,
2013                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2014                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2015                                  <&rpmhcc RPMH_CXO_CLK>;
2016                         clock-names = "iface", "bus", "nav", "snoc_axi",
2017                                       "mnoc_axi", "xo";
2018
2019                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2020                                         <&rpmhpd SC7180_CX>,
2021                                         <&rpmhpd SC7180_MX>,
2022                                         <&rpmhpd SC7180_MSS>;
2023                         power-domain-names = "load_state", "cx", "mx", "mss";
2024
2025                         memory-region = <&mpss_mem>;
2026
2027                         qcom,smem-states = <&modem_smp2p_out 0>;
2028                         qcom,smem-state-names = "stop";
2029
2030                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2031                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2032                         reset-names = "mss_restart", "pdc_reset";
2033
2034                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2035                         qcom,spare-regs = <&tcsr_regs 0xb3e4>;
2036
2037                         status = "disabled";
2038
2039                         glink-edge {
2040                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2041                                 label = "modem";
2042                                 qcom,remote-pid = <1>;
2043                                 mboxes = <&apss_shared 12>;
2044                         };
2045                 };
2046
2047                 gpu: gpu@5000000 {
2048                         compatible = "qcom,adreno-618.0", "qcom,adreno";
2049                         #stream-id-cells = <16>;
2050                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2051                                 <0 0x05061000 0 0x800>;
2052                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2053                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2054                         iommus = <&adreno_smmu 0>;
2055                         operating-points-v2 = <&gpu_opp_table>;
2056                         qcom,gmu = <&gmu>;
2057
2058                         #cooling-cells = <2>;
2059
2060                         nvmem-cells = <&gpu_speed_bin>;
2061                         nvmem-cell-names = "speed_bin";
2062
2063                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2064                         interconnect-names = "gfx-mem";
2065
2066                         gpu_opp_table: opp-table {
2067                                 compatible = "operating-points-v2";
2068
2069                                 opp-825000000 {
2070                                         opp-hz = /bits/ 64 <825000000>;
2071                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
2072                                         opp-peak-kBps = <8532000>;
2073                                         opp-supported-hw = <0x04>;
2074                                 };
2075
2076                                 opp-800000000 {
2077                                         opp-hz = /bits/ 64 <800000000>;
2078                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2079                                         opp-peak-kBps = <8532000>;
2080                                         opp-supported-hw = <0x07>;
2081                                 };
2082
2083                                 opp-650000000 {
2084                                         opp-hz = /bits/ 64 <650000000>;
2085                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2086                                         opp-peak-kBps = <7216000>;
2087                                         opp-supported-hw = <0x07>;
2088                                 };
2089
2090                                 opp-565000000 {
2091                                         opp-hz = /bits/ 64 <565000000>;
2092                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2093                                         opp-peak-kBps = <5412000>;
2094                                         opp-supported-hw = <0x07>;
2095                                 };
2096
2097                                 opp-430000000 {
2098                                         opp-hz = /bits/ 64 <430000000>;
2099                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2100                                         opp-peak-kBps = <5412000>;
2101                                         opp-supported-hw = <0x07>;
2102                                 };
2103
2104                                 opp-355000000 {
2105                                         opp-hz = /bits/ 64 <355000000>;
2106                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2107                                         opp-peak-kBps = <3072000>;
2108                                         opp-supported-hw = <0x07>;
2109                                 };
2110
2111                                 opp-267000000 {
2112                                         opp-hz = /bits/ 64 <267000000>;
2113                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2114                                         opp-peak-kBps = <3072000>;
2115                                         opp-supported-hw = <0x07>;
2116                                 };
2117
2118                                 opp-180000000 {
2119                                         opp-hz = /bits/ 64 <180000000>;
2120                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2121                                         opp-peak-kBps = <1804000>;
2122                                         opp-supported-hw = <0x07>;
2123                                 };
2124                         };
2125                 };
2126
2127                 adreno_smmu: iommu@5040000 {
2128                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2129                         reg = <0 0x05040000 0 0x10000>;
2130                         #iommu-cells = <1>;
2131                         #global-interrupts = <2>;
2132                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2133                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2134                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2135                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2136                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2137                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2138                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2139                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2140                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2141                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2142
2143                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2144                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2145                         clock-names = "bus", "iface";
2146
2147                         power-domains = <&gpucc CX_GDSC>;
2148                 };
2149
2150                 gmu: gmu@506a000 {
2151                         compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2152                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2153                                 <0 0x0b490000 0 0x10000>;
2154                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2155                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2156                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2157                         interrupt-names = "hfi", "gmu";
2158                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2159                                <&gpucc GPU_CC_CXO_CLK>,
2160                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2161                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2162                         clock-names = "gmu", "cxo", "axi", "memnoc";
2163                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2164                         power-domain-names = "cx", "gx";
2165                         iommus = <&adreno_smmu 5>;
2166                         operating-points-v2 = <&gmu_opp_table>;
2167
2168                         gmu_opp_table: opp-table {
2169                                 compatible = "operating-points-v2";
2170
2171                                 opp-200000000 {
2172                                         opp-hz = /bits/ 64 <200000000>;
2173                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2174                                 };
2175                         };
2176                 };
2177
2178                 gpucc: clock-controller@5090000 {
2179                         compatible = "qcom,sc7180-gpucc";
2180                         reg = <0 0x05090000 0 0x9000>;
2181                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2182                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2183                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2184                         clock-names = "bi_tcxo",
2185                                       "gcc_gpu_gpll0_clk_src",
2186                                       "gcc_gpu_gpll0_div_clk_src";
2187                         #clock-cells = <1>;
2188                         #reset-cells = <1>;
2189                         #power-domain-cells = <1>;
2190                 };
2191
2192                 stm@6002000 {
2193                         compatible = "arm,coresight-stm", "arm,primecell";
2194                         reg = <0 0x06002000 0 0x1000>,
2195                               <0 0x16280000 0 0x180000>;
2196                         reg-names = "stm-base", "stm-stimulus-base";
2197
2198                         clocks = <&aoss_qmp>;
2199                         clock-names = "apb_pclk";
2200
2201                         out-ports {
2202                                 port {
2203                                         stm_out: endpoint {
2204                                                 remote-endpoint = <&funnel0_in7>;
2205                                         };
2206                                 };
2207                         };
2208                 };
2209
2210                 funnel@6041000 {
2211                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2212                         reg = <0 0x06041000 0 0x1000>;
2213
2214                         clocks = <&aoss_qmp>;
2215                         clock-names = "apb_pclk";
2216
2217                         out-ports {
2218                                 port {
2219                                         funnel0_out: endpoint {
2220                                                 remote-endpoint = <&merge_funnel_in0>;
2221                                         };
2222                                 };
2223                         };
2224
2225                         in-ports {
2226                                 #address-cells = <1>;
2227                                 #size-cells = <0>;
2228
2229                                 port@7 {
2230                                         reg = <7>;
2231                                         funnel0_in7: endpoint {
2232                                                 remote-endpoint = <&stm_out>;
2233                                         };
2234                                 };
2235                         };
2236                 };
2237
2238                 funnel@6042000 {
2239                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2240                         reg = <0 0x06042000 0 0x1000>;
2241
2242                         clocks = <&aoss_qmp>;
2243                         clock-names = "apb_pclk";
2244
2245                         out-ports {
2246                                 port {
2247                                         funnel1_out: endpoint {
2248                                                 remote-endpoint = <&merge_funnel_in1>;
2249                                         };
2250                                 };
2251                         };
2252
2253                         in-ports {
2254                                 #address-cells = <1>;
2255                                 #size-cells = <0>;
2256
2257                                 port@4 {
2258                                         reg = <4>;
2259                                         funnel1_in4: endpoint {
2260                                                 remote-endpoint = <&apss_merge_funnel_out>;
2261                                         };
2262                                 };
2263                         };
2264                 };
2265
2266                 funnel@6045000 {
2267                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2268                         reg = <0 0x06045000 0 0x1000>;
2269
2270                         clocks = <&aoss_qmp>;
2271                         clock-names = "apb_pclk";
2272
2273                         out-ports {
2274                                 port {
2275                                         merge_funnel_out: endpoint {
2276                                                 remote-endpoint = <&swao_funnel_in>;
2277                                         };
2278                                 };
2279                         };
2280
2281                         in-ports {
2282                                 #address-cells = <1>;
2283                                 #size-cells = <0>;
2284
2285                                 port@0 {
2286                                         reg = <0>;
2287                                         merge_funnel_in0: endpoint {
2288                                                 remote-endpoint = <&funnel0_out>;
2289                                         };
2290                                 };
2291
2292                                 port@1 {
2293                                         reg = <1>;
2294                                         merge_funnel_in1: endpoint {
2295                                                 remote-endpoint = <&funnel1_out>;
2296                                         };
2297                                 };
2298                         };
2299                 };
2300
2301                 replicator@6046000 {
2302                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2303                         reg = <0 0x06046000 0 0x1000>;
2304
2305                         clocks = <&aoss_qmp>;
2306                         clock-names = "apb_pclk";
2307
2308                         out-ports {
2309                                 port {
2310                                         replicator_out: endpoint {
2311                                                 remote-endpoint = <&etr_in>;
2312                                         };
2313                                 };
2314                         };
2315
2316                         in-ports {
2317                                 port {
2318                                         replicator_in: endpoint {
2319                                                 remote-endpoint = <&swao_replicator_out>;
2320                                         };
2321                                 };
2322                         };
2323                 };
2324
2325                 etr@6048000 {
2326                         compatible = "arm,coresight-tmc", "arm,primecell";
2327                         reg = <0 0x06048000 0 0x1000>;
2328                         iommus = <&apps_smmu 0x04a0 0x20>;
2329
2330                         clocks = <&aoss_qmp>;
2331                         clock-names = "apb_pclk";
2332                         arm,scatter-gather;
2333
2334                         in-ports {
2335                                 port {
2336                                         etr_in: endpoint {
2337                                                 remote-endpoint = <&replicator_out>;
2338                                         };
2339                                 };
2340                         };
2341                 };
2342
2343                 funnel@6b04000 {
2344                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2345                         reg = <0 0x06b04000 0 0x1000>;
2346
2347                         clocks = <&aoss_qmp>;
2348                         clock-names = "apb_pclk";
2349
2350                         out-ports {
2351                                 port {
2352                                         swao_funnel_out: endpoint {
2353                                                 remote-endpoint = <&etf_in>;
2354                                         };
2355                                 };
2356                         };
2357
2358                         in-ports {
2359                                 #address-cells = <1>;
2360                                 #size-cells = <0>;
2361
2362                                 port@7 {
2363                                         reg = <7>;
2364                                         swao_funnel_in: endpoint {
2365                                                 remote-endpoint = <&merge_funnel_out>;
2366                                         };
2367                                 };
2368                         };
2369                 };
2370
2371                 etf@6b05000 {
2372                         compatible = "arm,coresight-tmc", "arm,primecell";
2373                         reg = <0 0x06b05000 0 0x1000>;
2374
2375                         clocks = <&aoss_qmp>;
2376                         clock-names = "apb_pclk";
2377
2378                         out-ports {
2379                                 port {
2380                                         etf_out: endpoint {
2381                                                 remote-endpoint = <&swao_replicator_in>;
2382                                         };
2383                                 };
2384                         };
2385
2386                         in-ports {
2387                                 port {
2388                                         etf_in: endpoint {
2389                                                 remote-endpoint = <&swao_funnel_out>;
2390                                         };
2391                                 };
2392                         };
2393                 };
2394
2395                 replicator@6b06000 {
2396                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2397                         reg = <0 0x06b06000 0 0x1000>;
2398
2399                         clocks = <&aoss_qmp>;
2400                         clock-names = "apb_pclk";
2401                         qcom,replicator-loses-context;
2402
2403                         out-ports {
2404                                 port {
2405                                         swao_replicator_out: endpoint {
2406                                                 remote-endpoint = <&replicator_in>;
2407                                         };
2408                                 };
2409                         };
2410
2411                         in-ports {
2412                                 port {
2413                                         swao_replicator_in: endpoint {
2414                                                 remote-endpoint = <&etf_out>;
2415                                         };
2416                                 };
2417                         };
2418                 };
2419
2420                 etm@7040000 {
2421                         compatible = "arm,coresight-etm4x", "arm,primecell";
2422                         reg = <0 0x07040000 0 0x1000>;
2423
2424                         cpu = <&CPU0>;
2425
2426                         clocks = <&aoss_qmp>;
2427                         clock-names = "apb_pclk";
2428                         arm,coresight-loses-context-with-cpu;
2429                         qcom,skip-power-up;
2430
2431                         out-ports {
2432                                 port {
2433                                         etm0_out: endpoint {
2434                                                 remote-endpoint = <&apss_funnel_in0>;
2435                                         };
2436                                 };
2437                         };
2438                 };
2439
2440                 etm@7140000 {
2441                         compatible = "arm,coresight-etm4x", "arm,primecell";
2442                         reg = <0 0x07140000 0 0x1000>;
2443
2444                         cpu = <&CPU1>;
2445
2446                         clocks = <&aoss_qmp>;
2447                         clock-names = "apb_pclk";
2448                         arm,coresight-loses-context-with-cpu;
2449                         qcom,skip-power-up;
2450
2451                         out-ports {
2452                                 port {
2453                                         etm1_out: endpoint {
2454                                                 remote-endpoint = <&apss_funnel_in1>;
2455                                         };
2456                                 };
2457                         };
2458                 };
2459
2460                 etm@7240000 {
2461                         compatible = "arm,coresight-etm4x", "arm,primecell";
2462                         reg = <0 0x07240000 0 0x1000>;
2463
2464                         cpu = <&CPU2>;
2465
2466                         clocks = <&aoss_qmp>;
2467                         clock-names = "apb_pclk";
2468                         arm,coresight-loses-context-with-cpu;
2469                         qcom,skip-power-up;
2470
2471                         out-ports {
2472                                 port {
2473                                         etm2_out: endpoint {
2474                                                 remote-endpoint = <&apss_funnel_in2>;
2475                                         };
2476                                 };
2477                         };
2478                 };
2479
2480                 etm@7340000 {
2481                         compatible = "arm,coresight-etm4x", "arm,primecell";
2482                         reg = <0 0x07340000 0 0x1000>;
2483
2484                         cpu = <&CPU3>;
2485
2486                         clocks = <&aoss_qmp>;
2487                         clock-names = "apb_pclk";
2488                         arm,coresight-loses-context-with-cpu;
2489                         qcom,skip-power-up;
2490
2491                         out-ports {
2492                                 port {
2493                                         etm3_out: endpoint {
2494                                                 remote-endpoint = <&apss_funnel_in3>;
2495                                         };
2496                                 };
2497                         };
2498                 };
2499
2500                 etm@7440000 {
2501                         compatible = "arm,coresight-etm4x", "arm,primecell";
2502                         reg = <0 0x07440000 0 0x1000>;
2503
2504                         cpu = <&CPU4>;
2505
2506                         clocks = <&aoss_qmp>;
2507                         clock-names = "apb_pclk";
2508                         arm,coresight-loses-context-with-cpu;
2509                         qcom,skip-power-up;
2510
2511                         out-ports {
2512                                 port {
2513                                         etm4_out: endpoint {
2514                                                 remote-endpoint = <&apss_funnel_in4>;
2515                                         };
2516                                 };
2517                         };
2518                 };
2519
2520                 etm@7540000 {
2521                         compatible = "arm,coresight-etm4x", "arm,primecell";
2522                         reg = <0 0x07540000 0 0x1000>;
2523
2524                         cpu = <&CPU5>;
2525
2526                         clocks = <&aoss_qmp>;
2527                         clock-names = "apb_pclk";
2528                         arm,coresight-loses-context-with-cpu;
2529                         qcom,skip-power-up;
2530
2531                         out-ports {
2532                                 port {
2533                                         etm5_out: endpoint {
2534                                                 remote-endpoint = <&apss_funnel_in5>;
2535                                         };
2536                                 };
2537                         };
2538                 };
2539
2540                 etm@7640000 {
2541                         compatible = "arm,coresight-etm4x", "arm,primecell";
2542                         reg = <0 0x07640000 0 0x1000>;
2543
2544                         cpu = <&CPU6>;
2545
2546                         clocks = <&aoss_qmp>;
2547                         clock-names = "apb_pclk";
2548                         arm,coresight-loses-context-with-cpu;
2549                         qcom,skip-power-up;
2550
2551                         out-ports {
2552                                 port {
2553                                         etm6_out: endpoint {
2554                                                 remote-endpoint = <&apss_funnel_in6>;
2555                                         };
2556                                 };
2557                         };
2558                 };
2559
2560                 etm@7740000 {
2561                         compatible = "arm,coresight-etm4x", "arm,primecell";
2562                         reg = <0 0x07740000 0 0x1000>;
2563
2564                         cpu = <&CPU7>;
2565
2566                         clocks = <&aoss_qmp>;
2567                         clock-names = "apb_pclk";
2568                         arm,coresight-loses-context-with-cpu;
2569                         qcom,skip-power-up;
2570
2571                         out-ports {
2572                                 port {
2573                                         etm7_out: endpoint {
2574                                                 remote-endpoint = <&apss_funnel_in7>;
2575                                         };
2576                                 };
2577                         };
2578                 };
2579
2580                 funnel@7800000 { /* APSS Funnel */
2581                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2582                         reg = <0 0x07800000 0 0x1000>;
2583
2584                         clocks = <&aoss_qmp>;
2585                         clock-names = "apb_pclk";
2586
2587                         out-ports {
2588                                 port {
2589                                         apss_funnel_out: endpoint {
2590                                                 remote-endpoint = <&apss_merge_funnel_in>;
2591                                         };
2592                                 };
2593                         };
2594
2595                         in-ports {
2596                                 #address-cells = <1>;
2597                                 #size-cells = <0>;
2598
2599                                 port@0 {
2600                                         reg = <0>;
2601                                         apss_funnel_in0: endpoint {
2602                                                 remote-endpoint = <&etm0_out>;
2603                                         };
2604                                 };
2605
2606                                 port@1 {
2607                                         reg = <1>;
2608                                         apss_funnel_in1: endpoint {
2609                                                 remote-endpoint = <&etm1_out>;
2610                                         };
2611                                 };
2612
2613                                 port@2 {
2614                                         reg = <2>;
2615                                         apss_funnel_in2: endpoint {
2616                                                 remote-endpoint = <&etm2_out>;
2617                                         };
2618                                 };
2619
2620                                 port@3 {
2621                                         reg = <3>;
2622                                         apss_funnel_in3: endpoint {
2623                                                 remote-endpoint = <&etm3_out>;
2624                                         };
2625                                 };
2626
2627                                 port@4 {
2628                                         reg = <4>;
2629                                         apss_funnel_in4: endpoint {
2630                                                 remote-endpoint = <&etm4_out>;
2631                                         };
2632                                 };
2633
2634                                 port@5 {
2635                                         reg = <5>;
2636                                         apss_funnel_in5: endpoint {
2637                                                 remote-endpoint = <&etm5_out>;
2638                                         };
2639                                 };
2640
2641                                 port@6 {
2642                                         reg = <6>;
2643                                         apss_funnel_in6: endpoint {
2644                                                 remote-endpoint = <&etm6_out>;
2645                                         };
2646                                 };
2647
2648                                 port@7 {
2649                                         reg = <7>;
2650                                         apss_funnel_in7: endpoint {
2651                                                 remote-endpoint = <&etm7_out>;
2652                                         };
2653                                 };
2654                         };
2655                 };
2656
2657                 funnel@7810000 {
2658                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2659                         reg = <0 0x07810000 0 0x1000>;
2660
2661                         clocks = <&aoss_qmp>;
2662                         clock-names = "apb_pclk";
2663
2664                         out-ports {
2665                                 port {
2666                                         apss_merge_funnel_out: endpoint {
2667                                                 remote-endpoint = <&funnel1_in4>;
2668                                         };
2669                                 };
2670                         };
2671
2672                         in-ports {
2673                                 port {
2674                                         apss_merge_funnel_in: endpoint {
2675                                                 remote-endpoint = <&apss_funnel_out>;
2676                                         };
2677                                 };
2678                         };
2679                 };
2680
2681                 sdhc_2: sdhci@8804000 {
2682                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2683                         reg = <0 0x08804000 0 0x1000>;
2684
2685                         iommus = <&apps_smmu 0x80 0>;
2686                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2687                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2688                         interrupt-names = "hc_irq", "pwr_irq";
2689
2690                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2691                                         <&gcc GCC_SDCC2_AHB_CLK>;
2692                         clock-names = "core", "iface";
2693
2694                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2695                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2696                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2697                         power-domains = <&rpmhpd SC7180_CX>;
2698                         operating-points-v2 = <&sdhc2_opp_table>;
2699
2700                         bus-width = <4>;
2701
2702                         status = "disabled";
2703
2704                         sdhc2_opp_table: sdhc2-opp-table {
2705                                 compatible = "operating-points-v2";
2706
2707                                 opp-100000000 {
2708                                         opp-hz = /bits/ 64 <100000000>;
2709                                         required-opps = <&rpmhpd_opp_low_svs>;
2710                                         opp-peak-kBps = <160000 100000>;
2711                                         opp-avg-kBps = <80000 50000>;
2712                                 };
2713
2714                                 opp-202000000 {
2715                                         opp-hz = /bits/ 64 <202000000>;
2716                                         required-opps = <&rpmhpd_opp_svs_l1>;
2717                                         opp-peak-kBps = <200000 120000>;
2718                                         opp-avg-kBps = <100000 60000>;
2719                                 };
2720                         };
2721                 };
2722
2723                 qspi_opp_table: qspi-opp-table {
2724                         compatible = "operating-points-v2";
2725
2726                         opp-75000000 {
2727                                 opp-hz = /bits/ 64 <75000000>;
2728                                 required-opps = <&rpmhpd_opp_low_svs>;
2729                         };
2730
2731                         opp-150000000 {
2732                                 opp-hz = /bits/ 64 <150000000>;
2733                                 required-opps = <&rpmhpd_opp_svs>;
2734                         };
2735
2736                         opp-300000000 {
2737                                 opp-hz = /bits/ 64 <300000000>;
2738                                 required-opps = <&rpmhpd_opp_nom>;
2739                         };
2740                 };
2741
2742                 qspi: spi@88dc000 {
2743                         compatible = "qcom,qspi-v1";
2744                         reg = <0 0x088dc000 0 0x600>;
2745                         #address-cells = <1>;
2746                         #size-cells = <0>;
2747                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2748                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2749                                  <&gcc GCC_QSPI_CORE_CLK>;
2750                         clock-names = "iface", "core";
2751                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2752                                         &config_noc SLAVE_QSPI_0 0>;
2753                         interconnect-names = "qspi-config";
2754                         power-domains = <&rpmhpd SC7180_CX>;
2755                         operating-points-v2 = <&qspi_opp_table>;
2756                         status = "disabled";
2757                 };
2758
2759                 usb_1_hsphy: phy@88e3000 {
2760                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2761                         reg = <0 0x088e3000 0 0x400>;
2762                         status = "disabled";
2763                         #phy-cells = <0>;
2764                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2765                                  <&rpmhcc RPMH_CXO_CLK>;
2766                         clock-names = "cfg_ahb", "ref";
2767                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2768
2769                         nvmem-cells = <&qusb2p_hstx_trim>;
2770                 };
2771
2772                 usb_1_qmpphy: phy-wrapper@88e9000 {
2773                         compatible = "qcom,sc7180-qmp-usb3-phy";
2774                         reg = <0 0x088e9000 0 0x18c>,
2775                               <0 0x088e8000 0 0x38>;
2776                         reg-names = "reg-base", "dp_com";
2777                         status = "disabled";
2778                         #clock-cells = <1>;
2779                         #address-cells = <2>;
2780                         #size-cells = <2>;
2781                         ranges;
2782
2783                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2784                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2785                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2786                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2787                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2788
2789                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2790                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2791                         reset-names = "phy", "common";
2792
2793                         usb_1_ssphy: phy@88e9200 {
2794                                 reg = <0 0x088e9200 0 0x128>,
2795                                       <0 0x088e9400 0 0x200>,
2796                                       <0 0x088e9c00 0 0x218>,
2797                                       <0 0x088e9600 0 0x128>,
2798                                       <0 0x088e9800 0 0x200>,
2799                                       <0 0x088e9a00 0 0x18>;
2800                                 #clock-cells = <0>;
2801                                 #phy-cells = <0>;
2802                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2803                                 clock-names = "pipe0";
2804                                 clock-output-names = "usb3_phy_pipe_clk_src";
2805                         };
2806                 };
2807
2808                 dc_noc: interconnect@9160000 {
2809                         compatible = "qcom,sc7180-dc-noc";
2810                         reg = <0 0x09160000 0 0x03200>;
2811                         #interconnect-cells = <2>;
2812                         qcom,bcm-voters = <&apps_bcm_voter>;
2813                 };
2814
2815                 system-cache-controller@9200000 {
2816                         compatible = "qcom,sc7180-llcc";
2817                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2818                         reg-names = "llcc_base", "llcc_broadcast_base";
2819                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2820                 };
2821
2822                 gem_noc: interconnect@9680000 {
2823                         compatible = "qcom,sc7180-gem-noc";
2824                         reg = <0 0x09680000 0 0x3e200>;
2825                         #interconnect-cells = <2>;
2826                         qcom,bcm-voters = <&apps_bcm_voter>;
2827                 };
2828
2829                 npu_noc: interconnect@9990000 {
2830                         compatible = "qcom,sc7180-npu-noc";
2831                         reg = <0 0x09990000 0 0x1600>;
2832                         #interconnect-cells = <2>;
2833                         qcom,bcm-voters = <&apps_bcm_voter>;
2834                 };
2835
2836                 usb_1: usb@a6f8800 {
2837                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2838                         reg = <0 0x0a6f8800 0 0x400>;
2839                         status = "disabled";
2840                         #address-cells = <2>;
2841                         #size-cells = <2>;
2842                         ranges;
2843                         dma-ranges;
2844
2845                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2846                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2847                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2848                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2849                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2850                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2851                                       "sleep";
2852
2853                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2854                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2855                         assigned-clock-rates = <19200000>, <150000000>;
2856
2857                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2858                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2859                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2860                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2861                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2862                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2863
2864                         power-domains = <&gcc USB30_PRIM_GDSC>;
2865
2866                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2867
2868                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2869                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2870                         interconnect-names = "usb-ddr", "apps-usb";
2871
2872                         usb_1_dwc3: dwc3@a600000 {
2873                                 compatible = "snps,dwc3";
2874                                 reg = <0 0x0a600000 0 0xe000>;
2875                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2876                                 iommus = <&apps_smmu 0x540 0>;
2877                                 snps,dis_u2_susphy_quirk;
2878                                 snps,dis_enblslpm_quirk;
2879                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2880                                 phy-names = "usb2-phy", "usb3-phy";
2881                                 maximum-speed = "super-speed";
2882                         };
2883                 };
2884
2885                 venus: video-codec@aa00000 {
2886                         compatible = "qcom,sc7180-venus";
2887                         reg = <0 0x0aa00000 0 0xff000>;
2888                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2889                         power-domains = <&videocc VENUS_GDSC>,
2890                                         <&videocc VCODEC0_GDSC>,
2891                                         <&rpmhpd SC7180_CX>;
2892                         power-domain-names = "venus", "vcodec0", "cx";
2893                         operating-points-v2 = <&venus_opp_table>;
2894                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2895                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2896                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2897                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2898                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2899                         clock-names = "core", "iface", "bus",
2900                                       "vcodec0_core", "vcodec0_bus";
2901                         iommus = <&apps_smmu 0x0c00 0x60>;
2902                         memory-region = <&venus_mem>;
2903                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2904                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2905                         interconnect-names = "video-mem", "cpu-cfg";
2906
2907                         video-decoder {
2908                                 compatible = "venus-decoder";
2909                         };
2910
2911                         video-encoder {
2912                                 compatible = "venus-encoder";
2913                         };
2914
2915                         venus_opp_table: venus-opp-table {
2916                                 compatible = "operating-points-v2";
2917
2918                                 opp-150000000 {
2919                                         opp-hz = /bits/ 64 <150000000>;
2920                                         required-opps = <&rpmhpd_opp_low_svs>;
2921                                 };
2922
2923                                 opp-270000000 {
2924                                         opp-hz = /bits/ 64 <270000000>;
2925                                         required-opps = <&rpmhpd_opp_svs>;
2926                                 };
2927
2928                                 opp-340000000 {
2929                                         opp-hz = /bits/ 64 <340000000>;
2930                                         required-opps = <&rpmhpd_opp_svs_l1>;
2931                                 };
2932
2933                                 opp-434000000 {
2934                                         opp-hz = /bits/ 64 <434000000>;
2935                                         required-opps = <&rpmhpd_opp_nom>;
2936                                 };
2937
2938                                 opp-500000097 {
2939                                         opp-hz = /bits/ 64 <500000097>;
2940                                         required-opps = <&rpmhpd_opp_turbo>;
2941                                 };
2942                         };
2943                 };
2944
2945                 videocc: clock-controller@ab00000 {
2946                         compatible = "qcom,sc7180-videocc";
2947                         reg = <0 0x0ab00000 0 0x10000>;
2948                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2949                         clock-names = "bi_tcxo";
2950                         #clock-cells = <1>;
2951                         #reset-cells = <1>;
2952                         #power-domain-cells = <1>;
2953                 };
2954
2955                 camnoc_virt: interconnect@ac00000 {
2956                         compatible = "qcom,sc7180-camnoc-virt";
2957                         reg = <0 0x0ac00000 0 0x1000>;
2958                         #interconnect-cells = <2>;
2959                         qcom,bcm-voters = <&apps_bcm_voter>;
2960                 };
2961
2962                 camcc: clock-controller@ad00000 {
2963                         compatible = "qcom,sc7180-camcc";
2964                         reg = <0 0x0ad00000 0 0x10000>;
2965                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2966                                <&gcc GCC_CAMERA_AHB_CLK>,
2967                                <&gcc GCC_CAMERA_XO_CLK>;
2968                         clock-names = "bi_tcxo", "iface", "xo";
2969                         #clock-cells = <1>;
2970                         #reset-cells = <1>;
2971                         #power-domain-cells = <1>;
2972                 };
2973
2974                 mdss: mdss@ae00000 {
2975                         compatible = "qcom,sc7180-mdss";
2976                         reg = <0 0x0ae00000 0 0x1000>;
2977                         reg-names = "mdss";
2978
2979                         power-domains = <&dispcc MDSS_GDSC>;
2980
2981                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2982                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
2983                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2984                         clock-names = "iface", "ahb", "core";
2985
2986                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2987                         assigned-clock-rates = <300000000>;
2988
2989                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2990                         interrupt-controller;
2991                         #interrupt-cells = <1>;
2992
2993                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2994                         interconnect-names = "mdp0-mem";
2995
2996                         iommus = <&apps_smmu 0x800 0x2>;
2997
2998                         #address-cells = <2>;
2999                         #size-cells = <2>;
3000                         ranges;
3001
3002                         status = "disabled";
3003
3004                         mdp: mdp@ae01000 {
3005                                 compatible = "qcom,sc7180-dpu";
3006                                 reg = <0 0x0ae01000 0 0x8f000>,
3007                                       <0 0x0aeb0000 0 0x2008>;
3008                                 reg-names = "mdp", "vbif";
3009
3010                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
3011                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3012                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
3013                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
3014                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
3015                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3016                                 clock-names = "bus", "iface", "rot", "lut", "core",
3017                                               "vsync";
3018                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3019                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3020                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
3021                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
3022                                 assigned-clock-rates = <300000000>,
3023                                                        <19200000>,
3024                                                        <19200000>,
3025                                                        <19200000>;
3026                                 operating-points-v2 = <&mdp_opp_table>;
3027                                 power-domains = <&rpmhpd SC7180_CX>;
3028
3029                                 interrupt-parent = <&mdss>;
3030                                 interrupts = <0>;
3031
3032                                 status = "disabled";
3033
3034                                 ports {
3035                                         #address-cells = <1>;
3036                                         #size-cells = <0>;
3037
3038                                         port@0 {
3039                                                 reg = <0>;
3040                                                 dpu_intf1_out: endpoint {
3041                                                         remote-endpoint = <&dsi0_in>;
3042                                                 };
3043                                         };
3044                                 };
3045
3046                                 mdp_opp_table: mdp-opp-table {
3047                                         compatible = "operating-points-v2";
3048
3049                                         opp-200000000 {
3050                                                 opp-hz = /bits/ 64 <200000000>;
3051                                                 required-opps = <&rpmhpd_opp_low_svs>;
3052                                         };
3053
3054                                         opp-300000000 {
3055                                                 opp-hz = /bits/ 64 <300000000>;
3056                                                 required-opps = <&rpmhpd_opp_svs>;
3057                                         };
3058
3059                                         opp-345000000 {
3060                                                 opp-hz = /bits/ 64 <345000000>;
3061                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3062                                         };
3063
3064                                         opp-460000000 {
3065                                                 opp-hz = /bits/ 64 <460000000>;
3066                                                 required-opps = <&rpmhpd_opp_nom>;
3067                                         };
3068                                 };
3069
3070                         };
3071
3072                         dsi0: dsi@ae94000 {
3073                                 compatible = "qcom,mdss-dsi-ctrl";
3074                                 reg = <0 0x0ae94000 0 0x400>;
3075                                 reg-names = "dsi_ctrl";
3076
3077                                 interrupt-parent = <&mdss>;
3078                                 interrupts = <4>;
3079
3080                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3081                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3082                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3083                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3084                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3085                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3086                                 clock-names = "byte",
3087                                               "byte_intf",
3088                                               "pixel",
3089                                               "core",
3090                                               "iface",
3091                                               "bus";
3092
3093                                 operating-points-v2 = <&dsi_opp_table>;
3094                                 power-domains = <&rpmhpd SC7180_CX>;
3095
3096                                 phys = <&dsi_phy>;
3097                                 phy-names = "dsi";
3098
3099                                 #address-cells = <1>;
3100                                 #size-cells = <0>;
3101
3102                                 status = "disabled";
3103
3104                                 ports {
3105                                         #address-cells = <1>;
3106                                         #size-cells = <0>;
3107
3108                                         port@0 {
3109                                                 reg = <0>;
3110                                                 dsi0_in: endpoint {
3111                                                         remote-endpoint = <&dpu_intf1_out>;
3112                                                 };
3113                                         };
3114
3115                                         port@1 {
3116                                                 reg = <1>;
3117                                                 dsi0_out: endpoint {
3118                                                 };
3119                                         };
3120                                 };
3121
3122                                 dsi_opp_table: dsi-opp-table {
3123                                         compatible = "operating-points-v2";
3124
3125                                         opp-187500000 {
3126                                                 opp-hz = /bits/ 64 <187500000>;
3127                                                 required-opps = <&rpmhpd_opp_low_svs>;
3128                                         };
3129
3130                                         opp-300000000 {
3131                                                 opp-hz = /bits/ 64 <300000000>;
3132                                                 required-opps = <&rpmhpd_opp_svs>;
3133                                         };
3134
3135                                         opp-358000000 {
3136                                                 opp-hz = /bits/ 64 <358000000>;
3137                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3138                                         };
3139                                 };
3140                         };
3141
3142                         dsi_phy: dsi-phy@ae94400 {
3143                                 compatible = "qcom,dsi-phy-10nm";
3144                                 reg = <0 0x0ae94400 0 0x200>,
3145                                       <0 0x0ae94600 0 0x280>,
3146                                       <0 0x0ae94a00 0 0x1e0>;
3147                                 reg-names = "dsi_phy",
3148                                             "dsi_phy_lane",
3149                                             "dsi_pll";
3150
3151                                 #clock-cells = <1>;
3152                                 #phy-cells = <0>;
3153
3154                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3155                                          <&rpmhcc RPMH_CXO_CLK>;
3156                                 clock-names = "iface", "ref";
3157
3158                                 status = "disabled";
3159                         };
3160                 };
3161
3162                 dispcc: clock-controller@af00000 {
3163                         compatible = "qcom,sc7180-dispcc";
3164                         reg = <0 0x0af00000 0 0x200000>;
3165                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3166                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3167                                  <&dsi_phy 0>,
3168                                  <&dsi_phy 1>,
3169                                  <0>,
3170                                  <0>;
3171                         clock-names = "bi_tcxo",
3172                                       "gcc_disp_gpll0_clk_src",
3173                                       "dsi0_phy_pll_out_byteclk",
3174                                       "dsi0_phy_pll_out_dsiclk",
3175                                       "dp_phy_pll_link_clk",
3176                                       "dp_phy_pll_vco_div_clk";
3177                         #clock-cells = <1>;
3178                         #reset-cells = <1>;
3179                         #power-domain-cells = <1>;
3180                 };
3181
3182                 pdc: interrupt-controller@b220000 {
3183                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3184                         reg = <0 0x0b220000 0 0x30000>;
3185                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3186                         #interrupt-cells = <2>;
3187                         interrupt-parent = <&intc>;
3188                         interrupt-controller;
3189                 };
3190
3191                 pdc_reset: reset-controller@b2e0000 {
3192                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3193                         reg = <0 0x0b2e0000 0 0x20000>;
3194                         #reset-cells = <1>;
3195                 };
3196
3197                 tsens0: thermal-sensor@c263000 {
3198                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3199                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3200                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3201                         #qcom,sensors = <15>;
3202                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3203                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3204                         interrupt-names = "uplow","critical";
3205                         #thermal-sensor-cells = <1>;
3206                 };
3207
3208                 tsens1: thermal-sensor@c265000 {
3209                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3210                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3211                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3212                         #qcom,sensors = <10>;
3213                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3214                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3215                         interrupt-names = "uplow","critical";
3216                         #thermal-sensor-cells = <1>;
3217                 };
3218
3219                 aoss_reset: reset-controller@c2a0000 {
3220                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3221                         reg = <0 0x0c2a0000 0 0x31000>;
3222                         #reset-cells = <1>;
3223                 };
3224
3225                 aoss_qmp: qmp@c300000 {
3226                         compatible = "qcom,sc7180-aoss-qmp";
3227                         reg = <0 0x0c300000 0 0x100000>;
3228                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3229                         mboxes = <&apss_shared 0>;
3230
3231                         #clock-cells = <0>;
3232                         #power-domain-cells = <1>;
3233                 };
3234
3235                 spmi_bus: spmi@c440000 {
3236                         compatible = "qcom,spmi-pmic-arb";
3237                         reg = <0 0x0c440000 0 0x1100>,
3238                               <0 0x0c600000 0 0x2000000>,
3239                               <0 0x0e600000 0 0x100000>,
3240                               <0 0x0e700000 0 0xa0000>,
3241                               <0 0x0c40a000 0 0x26000>;
3242                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3243                         interrupt-names = "periph_irq";
3244                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3245                         qcom,ee = <0>;
3246                         qcom,channel = <0>;
3247                         #address-cells = <1>;
3248                         #size-cells = <1>;
3249                         interrupt-controller;
3250                         #interrupt-cells = <4>;
3251                         cell-index = <0>;
3252                 };
3253
3254                 apps_smmu: iommu@15000000 {
3255                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3256                         reg = <0 0x15000000 0 0x100000>;
3257                         #iommu-cells = <2>;
3258                         #global-interrupts = <1>;
3259                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3260                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3261                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3262                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3263                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3264                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3265                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3266                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3267                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3268                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3269                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3270                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3271                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3272                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3278                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3279                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3280                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3281                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3282                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3283                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3284                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3285                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3286                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3287                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3288                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3289                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3290                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3291                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3292                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3293                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3294                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3295                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3296                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3297                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3298                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3299                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3300                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3301                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3302                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3303                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3304                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3305                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3306                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3307                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3308                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3309                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3310                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3311                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3312                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3313                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3314                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3315                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3316                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3317                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3318                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3319                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3320                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3321                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3322                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3323                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3324                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3325                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3326                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3327                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3328                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3329                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3330                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3331                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3332                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3333                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3334                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3335                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3336                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3337                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3338                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3339                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3340                 };
3341
3342                 intc: interrupt-controller@17a00000 {
3343                         compatible = "arm,gic-v3";
3344                         #address-cells = <2>;
3345                         #size-cells = <2>;
3346                         ranges;
3347                         #interrupt-cells = <3>;
3348                         interrupt-controller;
3349                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3350                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3351                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3352
3353                         msi-controller@17a40000 {
3354                                 compatible = "arm,gic-v3-its";
3355                                 msi-controller;
3356                                 #msi-cells = <1>;
3357                                 reg = <0 0x17a40000 0 0x20000>;
3358                                 status = "disabled";
3359                         };
3360                 };
3361
3362                 apss_shared: mailbox@17c00000 {
3363                         compatible = "qcom,sc7180-apss-shared";
3364                         reg = <0 0x17c00000 0 0x10000>;
3365                         #mbox-cells = <1>;
3366                 };
3367
3368                 watchdog@17c10000 {
3369                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3370                         reg = <0 0x17c10000 0 0x1000>;
3371                         clocks = <&sleep_clk>;
3372                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
3373                 };
3374
3375                 timer@17c20000{
3376                         #address-cells = <2>;
3377                         #size-cells = <2>;
3378                         ranges;
3379                         compatible = "arm,armv7-timer-mem";
3380                         reg = <0 0x17c20000 0 0x1000>;
3381
3382                         frame@17c21000 {
3383                                 frame-number = <0>;
3384                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3385                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3386                                 reg = <0 0x17c21000 0 0x1000>,
3387                                       <0 0x17c22000 0 0x1000>;
3388                         };
3389
3390                         frame@17c23000 {
3391                                 frame-number = <1>;
3392                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3393                                 reg = <0 0x17c23000 0 0x1000>;
3394                                 status = "disabled";
3395                         };
3396
3397                         frame@17c25000 {
3398                                 frame-number = <2>;
3399                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3400                                 reg = <0 0x17c25000 0 0x1000>;
3401                                 status = "disabled";
3402                         };
3403
3404                         frame@17c27000 {
3405                                 frame-number = <3>;
3406                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3407                                 reg = <0 0x17c27000 0 0x1000>;
3408                                 status = "disabled";
3409                         };
3410
3411                         frame@17c29000 {
3412                                 frame-number = <4>;
3413                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3414                                 reg = <0 0x17c29000 0 0x1000>;
3415                                 status = "disabled";
3416                         };
3417
3418                         frame@17c2b000 {
3419                                 frame-number = <5>;
3420                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3421                                 reg = <0 0x17c2b000 0 0x1000>;
3422                                 status = "disabled";
3423                         };
3424
3425                         frame@17c2d000 {
3426                                 frame-number = <6>;
3427                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3428                                 reg = <0 0x17c2d000 0 0x1000>;
3429                                 status = "disabled";
3430                         };
3431                 };
3432
3433                 apps_rsc: rsc@18200000 {
3434                         compatible = "qcom,rpmh-rsc";
3435                         reg = <0 0x18200000 0 0x10000>,
3436                               <0 0x18210000 0 0x10000>,
3437                               <0 0x18220000 0 0x10000>;
3438                         reg-names = "drv-0", "drv-1", "drv-2";
3439                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3440                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3441                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3442                         qcom,tcs-offset = <0xd00>;
3443                         qcom,drv-id = <2>;
3444                         qcom,tcs-config = <ACTIVE_TCS  2>,
3445                                           <SLEEP_TCS   3>,
3446                                           <WAKE_TCS    3>,
3447                                           <CONTROL_TCS 1>;
3448
3449                         rpmhcc: clock-controller {
3450                                 compatible = "qcom,sc7180-rpmh-clk";
3451                                 clocks = <&xo_board>;
3452                                 clock-names = "xo";
3453                                 #clock-cells = <1>;
3454                         };
3455
3456                         rpmhpd: power-controller {
3457                                 compatible = "qcom,sc7180-rpmhpd";
3458                                 #power-domain-cells = <1>;
3459                                 operating-points-v2 = <&rpmhpd_opp_table>;
3460
3461                                 rpmhpd_opp_table: opp-table {
3462                                         compatible = "operating-points-v2";
3463
3464                                         rpmhpd_opp_ret: opp1 {
3465                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3466                                         };
3467
3468                                         rpmhpd_opp_min_svs: opp2 {
3469                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3470                                         };
3471
3472                                         rpmhpd_opp_low_svs: opp3 {
3473                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3474                                         };
3475
3476                                         rpmhpd_opp_svs: opp4 {
3477                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3478                                         };
3479
3480                                         rpmhpd_opp_svs_l1: opp5 {
3481                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3482                                         };
3483
3484                                         rpmhpd_opp_svs_l2: opp6 {
3485                                                 opp-level = <224>;
3486                                         };
3487
3488                                         rpmhpd_opp_nom: opp7 {
3489                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3490                                         };
3491
3492                                         rpmhpd_opp_nom_l1: opp8 {
3493                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3494                                         };
3495
3496                                         rpmhpd_opp_nom_l2: opp9 {
3497                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3498                                         };
3499
3500                                         rpmhpd_opp_turbo: opp10 {
3501                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3502                                         };
3503
3504                                         rpmhpd_opp_turbo_l1: opp11 {
3505                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3506                                         };
3507                                 };
3508                         };
3509
3510                         apps_bcm_voter: bcm_voter {
3511                                 compatible = "qcom,bcm-voter";
3512                         };
3513                 };
3514
3515                 osm_l3: interconnect@18321000 {
3516                         compatible = "qcom,sc7180-osm-l3";
3517                         reg = <0 0x18321000 0 0x1400>;
3518
3519                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3520                         clock-names = "xo", "alternate";
3521
3522                         #interconnect-cells = <1>;
3523                 };
3524
3525                 cpufreq_hw: cpufreq@18323000 {
3526                         compatible = "qcom,cpufreq-hw";
3527                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3528                         reg-names = "freq-domain0", "freq-domain1";
3529
3530                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3531                         clock-names = "xo", "alternate";
3532
3533                         #freq-domain-cells = <1>;
3534                 };
3535
3536                 wifi: wifi@18800000 {
3537                         compatible = "qcom,wcn3990-wifi";
3538                         reg = <0 0x18800000 0 0x800000>;
3539                         reg-names = "membase";
3540                         iommus = <&apps_smmu 0xc0 0x1>;
3541                         interrupts =
3542                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3543                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3544                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3545                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3546                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3547                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3548                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3549                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3550                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3551                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3552                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3553                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3554                         memory-region = <&wlan_mem>;
3555                         qcom,msa-fixed-perm;
3556                         status = "disabled";
3557                 };
3558
3559                 lpasscc: clock-controller@62d00000 {
3560                         compatible = "qcom,sc7180-lpasscorecc";
3561                         reg = <0 0x62d00000 0 0x50000>,
3562                               <0 0x62780000 0 0x30000>;
3563                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3564                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3565                                  <&rpmhcc RPMH_CXO_CLK>;
3566                         clock-names = "iface", "bi_tcxo";
3567                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3568                         #clock-cells = <1>;
3569                         #power-domain-cells = <1>;
3570                 };
3571
3572                 lpass_cpu: lpass@62f00000 {
3573                         compatible = "qcom,sc7180-lpass-cpu";
3574
3575                         reg = <0 0x62f00000 0 0x29000>;
3576                         reg-names = "lpass-lpaif";
3577
3578                         iommus = <&apps_smmu 0x1020 0>;
3579
3580                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3581
3582                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3583                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3584                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3585                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3586                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3587                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3588
3589                         clock-names = "pcnoc-sway-clk", "audio-core",
3590                                         "mclk0", "pcnoc-mport-clk",
3591                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
3592
3593
3594                         #sound-dai-cells = <1>;
3595                         #address-cells = <1>;
3596                         #size-cells = <0>;
3597
3598                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3599                         interrupt-names = "lpass-irq-lpaif";
3600                 };
3601
3602                 lpass_hm: clock-controller@63000000 {
3603                         compatible = "qcom,sc7180-lpasshm";
3604                         reg = <0 0x63000000 0 0x28>;
3605                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3606                                  <&rpmhcc RPMH_CXO_CLK>;
3607                         clock-names = "iface", "bi_tcxo";
3608                         #clock-cells = <1>;
3609                         #power-domain-cells = <1>;
3610                 };
3611         };
3612
3613         thermal-zones {
3614                 cpu0_thermal: cpu0-thermal {
3615                         polling-delay-passive = <250>;
3616                         polling-delay = <0>;
3617
3618                         thermal-sensors = <&tsens0 1>;
3619                         sustainable-power = <768>;
3620
3621                         trips {
3622                                 cpu0_alert0: trip-point0 {
3623                                         temperature = <90000>;
3624                                         hysteresis = <2000>;
3625                                         type = "passive";
3626                                 };
3627
3628                                 cpu0_alert1: trip-point1 {
3629                                         temperature = <95000>;
3630                                         hysteresis = <2000>;
3631                                         type = "passive";
3632                                 };
3633
3634                                 cpu0_crit: cpu_crit {
3635                                         temperature = <110000>;
3636                                         hysteresis = <1000>;
3637                                         type = "critical";
3638                                 };
3639                         };
3640
3641                         cooling-maps {
3642                                 map0 {
3643                                         trip = <&cpu0_alert0>;
3644                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3645                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3646                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3647                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3648                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3649                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3650                                 };
3651                                 map1 {
3652                                         trip = <&cpu0_alert1>;
3653                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3654                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3655                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3656                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3657                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3658                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3659                                 };
3660                         };
3661                 };
3662
3663                 cpu1_thermal: cpu1-thermal {
3664                         polling-delay-passive = <250>;
3665                         polling-delay = <0>;
3666
3667                         thermal-sensors = <&tsens0 2>;
3668                         sustainable-power = <768>;
3669
3670                         trips {
3671                                 cpu1_alert0: trip-point0 {
3672                                         temperature = <90000>;
3673                                         hysteresis = <2000>;
3674                                         type = "passive";
3675                                 };
3676
3677                                 cpu1_alert1: trip-point1 {
3678                                         temperature = <95000>;
3679                                         hysteresis = <2000>;
3680                                         type = "passive";
3681                                 };
3682
3683                                 cpu1_crit: cpu_crit {
3684                                         temperature = <110000>;
3685                                         hysteresis = <1000>;
3686                                         type = "critical";
3687                                 };
3688                         };
3689
3690                         cooling-maps {
3691                                 map0 {
3692                                         trip = <&cpu1_alert0>;
3693                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3694                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3695                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3696                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3697                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3698                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3699                                 };
3700                                 map1 {
3701                                         trip = <&cpu1_alert1>;
3702                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3703                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3704                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3705                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3706                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3707                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3708                                 };
3709                         };
3710                 };
3711
3712                 cpu2_thermal: cpu2-thermal {
3713                         polling-delay-passive = <250>;
3714                         polling-delay = <0>;
3715
3716                         thermal-sensors = <&tsens0 3>;
3717                         sustainable-power = <768>;
3718
3719                         trips {
3720                                 cpu2_alert0: trip-point0 {
3721                                         temperature = <90000>;
3722                                         hysteresis = <2000>;
3723                                         type = "passive";
3724                                 };
3725
3726                                 cpu2_alert1: trip-point1 {
3727                                         temperature = <95000>;
3728                                         hysteresis = <2000>;
3729                                         type = "passive";
3730                                 };
3731
3732                                 cpu2_crit: cpu_crit {
3733                                         temperature = <110000>;
3734                                         hysteresis = <1000>;
3735                                         type = "critical";
3736                                 };
3737                         };
3738
3739                         cooling-maps {
3740                                 map0 {
3741                                         trip = <&cpu2_alert0>;
3742                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3743                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3744                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3745                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3746                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3747                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3748                                 };
3749                                 map1 {
3750                                         trip = <&cpu2_alert1>;
3751                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3752                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3753                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3754                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3755                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3756                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3757                                 };
3758                         };
3759                 };
3760
3761                 cpu3_thermal: cpu3-thermal {
3762                         polling-delay-passive = <250>;
3763                         polling-delay = <0>;
3764
3765                         thermal-sensors = <&tsens0 4>;
3766                         sustainable-power = <768>;
3767
3768                         trips {
3769                                 cpu3_alert0: trip-point0 {
3770                                         temperature = <90000>;
3771                                         hysteresis = <2000>;
3772                                         type = "passive";
3773                                 };
3774
3775                                 cpu3_alert1: trip-point1 {
3776                                         temperature = <95000>;
3777                                         hysteresis = <2000>;
3778                                         type = "passive";
3779                                 };
3780
3781                                 cpu3_crit: cpu_crit {
3782                                         temperature = <110000>;
3783                                         hysteresis = <1000>;
3784                                         type = "critical";
3785                                 };
3786                         };
3787
3788                         cooling-maps {
3789                                 map0 {
3790                                         trip = <&cpu3_alert0>;
3791                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3792                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3793                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3794                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3795                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3796                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3797                                 };
3798                                 map1 {
3799                                         trip = <&cpu3_alert1>;
3800                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3801                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3802                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3803                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3804                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3805                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3806                                 };
3807                         };
3808                 };
3809
3810                 cpu4_thermal: cpu4-thermal {
3811                         polling-delay-passive = <250>;
3812                         polling-delay = <0>;
3813
3814                         thermal-sensors = <&tsens0 5>;
3815                         sustainable-power = <768>;
3816
3817                         trips {
3818                                 cpu4_alert0: trip-point0 {
3819                                         temperature = <90000>;
3820                                         hysteresis = <2000>;
3821                                         type = "passive";
3822                                 };
3823
3824                                 cpu4_alert1: trip-point1 {
3825                                         temperature = <95000>;
3826                                         hysteresis = <2000>;
3827                                         type = "passive";
3828                                 };
3829
3830                                 cpu4_crit: cpu_crit {
3831                                         temperature = <110000>;
3832                                         hysteresis = <1000>;
3833                                         type = "critical";
3834                                 };
3835                         };
3836
3837                         cooling-maps {
3838                                 map0 {
3839                                         trip = <&cpu4_alert0>;
3840                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3841                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3842                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3843                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3844                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3845                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3846                                 };
3847                                 map1 {
3848                                         trip = <&cpu4_alert1>;
3849                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3850                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3851                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3852                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3853                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3854                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3855                                 };
3856                         };
3857                 };
3858
3859                 cpu5_thermal: cpu5-thermal {
3860                         polling-delay-passive = <250>;
3861                         polling-delay = <0>;
3862
3863                         thermal-sensors = <&tsens0 6>;
3864                         sustainable-power = <768>;
3865
3866                         trips {
3867                                 cpu5_alert0: trip-point0 {
3868                                         temperature = <90000>;
3869                                         hysteresis = <2000>;
3870                                         type = "passive";
3871                                 };
3872
3873                                 cpu5_alert1: trip-point1 {
3874                                         temperature = <95000>;
3875                                         hysteresis = <2000>;
3876                                         type = "passive";
3877                                 };
3878
3879                                 cpu5_crit: cpu_crit {
3880                                         temperature = <110000>;
3881                                         hysteresis = <1000>;
3882                                         type = "critical";
3883                                 };
3884                         };
3885
3886                         cooling-maps {
3887                                 map0 {
3888                                         trip = <&cpu5_alert0>;
3889                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3890                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3891                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3892                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3893                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3894                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3895                                 };
3896                                 map1 {
3897                                         trip = <&cpu5_alert1>;
3898                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3899                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3900                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3901                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3902                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3903                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3904                                 };
3905                         };
3906                 };
3907
3908                 cpu6_thermal: cpu6-thermal {
3909                         polling-delay-passive = <250>;
3910                         polling-delay = <0>;
3911
3912                         thermal-sensors = <&tsens0 9>;
3913                         sustainable-power = <1202>;
3914
3915                         trips {
3916                                 cpu6_alert0: trip-point0 {
3917                                         temperature = <90000>;
3918                                         hysteresis = <2000>;
3919                                         type = "passive";
3920                                 };
3921
3922                                 cpu6_alert1: trip-point1 {
3923                                         temperature = <95000>;
3924                                         hysteresis = <2000>;
3925                                         type = "passive";
3926                                 };
3927
3928                                 cpu6_crit: cpu_crit {
3929                                         temperature = <110000>;
3930                                         hysteresis = <1000>;
3931                                         type = "critical";
3932                                 };
3933                         };
3934
3935                         cooling-maps {
3936                                 map0 {
3937                                         trip = <&cpu6_alert0>;
3938                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3939                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3940                                 };
3941                                 map1 {
3942                                         trip = <&cpu6_alert1>;
3943                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3944                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3945                                 };
3946                         };
3947                 };
3948
3949                 cpu7_thermal: cpu7-thermal {
3950                         polling-delay-passive = <250>;
3951                         polling-delay = <0>;
3952
3953                         thermal-sensors = <&tsens0 10>;
3954                         sustainable-power = <1202>;
3955
3956                         trips {
3957                                 cpu7_alert0: trip-point0 {
3958                                         temperature = <90000>;
3959                                         hysteresis = <2000>;
3960                                         type = "passive";
3961                                 };
3962
3963                                 cpu7_alert1: trip-point1 {
3964                                         temperature = <95000>;
3965                                         hysteresis = <2000>;
3966                                         type = "passive";
3967                                 };
3968
3969                                 cpu7_crit: cpu_crit {
3970                                         temperature = <110000>;
3971                                         hysteresis = <1000>;
3972                                         type = "critical";
3973                                 };
3974                         };
3975
3976                         cooling-maps {
3977                                 map0 {
3978                                         trip = <&cpu7_alert0>;
3979                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3980                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3981                                 };
3982                                 map1 {
3983                                         trip = <&cpu7_alert1>;
3984                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3985                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3986                                 };
3987                         };
3988                 };
3989
3990                 cpu8_thermal: cpu8-thermal {
3991                         polling-delay-passive = <250>;
3992                         polling-delay = <0>;
3993
3994                         thermal-sensors = <&tsens0 11>;
3995                         sustainable-power = <1202>;
3996
3997                         trips {
3998                                 cpu8_alert0: trip-point0 {
3999                                         temperature = <90000>;
4000                                         hysteresis = <2000>;
4001                                         type = "passive";
4002                                 };
4003
4004                                 cpu8_alert1: trip-point1 {
4005                                         temperature = <95000>;
4006                                         hysteresis = <2000>;
4007                                         type = "passive";
4008                                 };
4009
4010                                 cpu8_crit: cpu_crit {
4011                                         temperature = <110000>;
4012                                         hysteresis = <1000>;
4013                                         type = "critical";
4014                                 };
4015                         };
4016
4017                         cooling-maps {
4018                                 map0 {
4019                                         trip = <&cpu8_alert0>;
4020                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4021                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4022                                 };
4023                                 map1 {
4024                                         trip = <&cpu8_alert1>;
4025                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4026                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4027                                 };
4028                         };
4029                 };
4030
4031                 cpu9_thermal: cpu9-thermal {
4032                         polling-delay-passive = <250>;
4033                         polling-delay = <0>;
4034
4035                         thermal-sensors = <&tsens0 12>;
4036                         sustainable-power = <1202>;
4037
4038                         trips {
4039                                 cpu9_alert0: trip-point0 {
4040                                         temperature = <90000>;
4041                                         hysteresis = <2000>;
4042                                         type = "passive";
4043                                 };
4044
4045                                 cpu9_alert1: trip-point1 {
4046                                         temperature = <95000>;
4047                                         hysteresis = <2000>;
4048                                         type = "passive";
4049                                 };
4050
4051                                 cpu9_crit: cpu_crit {
4052                                         temperature = <110000>;
4053                                         hysteresis = <1000>;
4054                                         type = "critical";
4055                                 };
4056                         };
4057
4058                         cooling-maps {
4059                                 map0 {
4060                                         trip = <&cpu9_alert0>;
4061                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4062                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4063                                 };
4064                                 map1 {
4065                                         trip = <&cpu9_alert1>;
4066                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4067                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4068                                 };
4069                         };
4070                 };
4071
4072                 aoss0-thermal {
4073                         polling-delay-passive = <250>;
4074                         polling-delay = <0>;
4075
4076                         thermal-sensors = <&tsens0 0>;
4077
4078                         trips {
4079                                 aoss0_alert0: trip-point0 {
4080                                         temperature = <90000>;
4081                                         hysteresis = <2000>;
4082                                         type = "hot";
4083                                 };
4084
4085                                 aoss0_crit: aoss0_crit {
4086                                         temperature = <110000>;
4087                                         hysteresis = <2000>;
4088                                         type = "critical";
4089                                 };
4090                         };
4091                 };
4092
4093                 cpuss0-thermal {
4094                         polling-delay-passive = <250>;
4095                         polling-delay = <0>;
4096
4097                         thermal-sensors = <&tsens0 7>;
4098
4099                         trips {
4100                                 cpuss0_alert0: trip-point0 {
4101                                         temperature = <90000>;
4102                                         hysteresis = <2000>;
4103                                         type = "hot";
4104                                 };
4105                                 cpuss0_crit: cluster0_crit {
4106                                         temperature = <110000>;
4107                                         hysteresis = <2000>;
4108                                         type = "critical";
4109                                 };
4110                         };
4111                 };
4112
4113                 cpuss1-thermal {
4114                         polling-delay-passive = <250>;
4115                         polling-delay = <0>;
4116
4117                         thermal-sensors = <&tsens0 8>;
4118
4119                         trips {
4120                                 cpuss1_alert0: trip-point0 {
4121                                         temperature = <90000>;
4122                                         hysteresis = <2000>;
4123                                         type = "hot";
4124                                 };
4125                                 cpuss1_crit: cluster0_crit {
4126                                         temperature = <110000>;
4127                                         hysteresis = <2000>;
4128                                         type = "critical";
4129                                 };
4130                         };
4131                 };
4132
4133                 gpuss0-thermal {
4134                         polling-delay-passive = <250>;
4135                         polling-delay = <0>;
4136
4137                         thermal-sensors = <&tsens0 13>;
4138
4139                         trips {
4140                                 gpuss0_alert0: trip-point0 {
4141                                         temperature = <95000>;
4142                                         hysteresis = <2000>;
4143                                         type = "passive";
4144                                 };
4145
4146                                 gpuss0_crit: gpuss0_crit {
4147                                         temperature = <110000>;
4148                                         hysteresis = <2000>;
4149                                         type = "critical";
4150                                 };
4151                         };
4152
4153                         cooling-maps {
4154                                 map0 {
4155                                         trip = <&gpuss0_alert0>;
4156                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4157                                 };
4158                         };
4159                 };
4160
4161                 gpuss1-thermal {
4162                         polling-delay-passive = <250>;
4163                         polling-delay = <0>;
4164
4165                         thermal-sensors = <&tsens0 14>;
4166
4167                         trips {
4168                                 gpuss1_alert0: trip-point0 {
4169                                         temperature = <95000>;
4170                                         hysteresis = <2000>;
4171                                         type = "passive";
4172                                 };
4173
4174                                 gpuss1_crit: gpuss1_crit {
4175                                         temperature = <110000>;
4176                                         hysteresis = <2000>;
4177                                         type = "critical";
4178                                 };
4179                         };
4180
4181                         cooling-maps {
4182                                 map0 {
4183                                         trip = <&gpuss1_alert0>;
4184                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4185                                 };
4186                         };
4187                 };
4188
4189                 aoss1-thermal {
4190                         polling-delay-passive = <250>;
4191                         polling-delay = <0>;
4192
4193                         thermal-sensors = <&tsens1 0>;
4194
4195                         trips {
4196                                 aoss1_alert0: trip-point0 {
4197                                         temperature = <90000>;
4198                                         hysteresis = <2000>;
4199                                         type = "hot";
4200                                 };
4201
4202                                 aoss1_crit: aoss1_crit {
4203                                         temperature = <110000>;
4204                                         hysteresis = <2000>;
4205                                         type = "critical";
4206                                 };
4207                         };
4208                 };
4209
4210                 cwlan-thermal {
4211                         polling-delay-passive = <250>;
4212                         polling-delay = <0>;
4213
4214                         thermal-sensors = <&tsens1 1>;
4215
4216                         trips {
4217                                 cwlan_alert0: trip-point0 {
4218                                         temperature = <90000>;
4219                                         hysteresis = <2000>;
4220                                         type = "hot";
4221                                 };
4222
4223                                 cwlan_crit: cwlan_crit {
4224                                         temperature = <110000>;
4225                                         hysteresis = <2000>;
4226                                         type = "critical";
4227                                 };
4228                         };
4229                 };
4230
4231                 audio-thermal {
4232                         polling-delay-passive = <250>;
4233                         polling-delay = <0>;
4234
4235                         thermal-sensors = <&tsens1 2>;
4236
4237                         trips {
4238                                 audio_alert0: trip-point0 {
4239                                         temperature = <90000>;
4240                                         hysteresis = <2000>;
4241                                         type = "hot";
4242                                 };
4243
4244                                 audio_crit: audio_crit {
4245                                         temperature = <110000>;
4246                                         hysteresis = <2000>;
4247                                         type = "critical";
4248                                 };
4249                         };
4250                 };
4251
4252                 ddr-thermal {
4253                         polling-delay-passive = <250>;
4254                         polling-delay = <0>;
4255
4256                         thermal-sensors = <&tsens1 3>;
4257
4258                         trips {
4259                                 ddr_alert0: trip-point0 {
4260                                         temperature = <90000>;
4261                                         hysteresis = <2000>;
4262                                         type = "hot";
4263                                 };
4264
4265                                 ddr_crit: ddr_crit {
4266                                         temperature = <110000>;
4267                                         hysteresis = <2000>;
4268                                         type = "critical";
4269                                 };
4270                         };
4271                 };
4272
4273                 q6-hvx-thermal {
4274                         polling-delay-passive = <250>;
4275                         polling-delay = <0>;
4276
4277                         thermal-sensors = <&tsens1 4>;
4278
4279                         trips {
4280                                 q6_hvx_alert0: trip-point0 {
4281                                         temperature = <90000>;
4282                                         hysteresis = <2000>;
4283                                         type = "hot";
4284                                 };
4285
4286                                 q6_hvx_crit: q6_hvx_crit {
4287                                         temperature = <110000>;
4288                                         hysteresis = <2000>;
4289                                         type = "critical";
4290                                 };
4291                         };
4292                 };
4293
4294                 camera-thermal {
4295                         polling-delay-passive = <250>;
4296                         polling-delay = <0>;
4297
4298                         thermal-sensors = <&tsens1 5>;
4299
4300                         trips {
4301                                 camera_alert0: trip-point0 {
4302                                         temperature = <90000>;
4303                                         hysteresis = <2000>;
4304                                         type = "hot";
4305                                 };
4306
4307                                 camera_crit: camera_crit {
4308                                         temperature = <110000>;
4309                                         hysteresis = <2000>;
4310                                         type = "critical";
4311                                 };
4312                         };
4313                 };
4314
4315                 mdm-core-thermal {
4316                         polling-delay-passive = <250>;
4317                         polling-delay = <0>;
4318
4319                         thermal-sensors = <&tsens1 6>;
4320
4321                         trips {
4322                                 mdm_alert0: trip-point0 {
4323                                         temperature = <90000>;
4324                                         hysteresis = <2000>;
4325                                         type = "hot";
4326                                 };
4327
4328                                 mdm_crit: mdm_crit {
4329                                         temperature = <110000>;
4330                                         hysteresis = <2000>;
4331                                         type = "critical";
4332                                 };
4333                         };
4334                 };
4335
4336                 mdm-dsp-thermal {
4337                         polling-delay-passive = <250>;
4338                         polling-delay = <0>;
4339
4340                         thermal-sensors = <&tsens1 7>;
4341
4342                         trips {
4343                                 mdm_dsp_alert0: trip-point0 {
4344                                         temperature = <90000>;
4345                                         hysteresis = <2000>;
4346                                         type = "hot";
4347                                 };
4348
4349                                 mdm_dsp_crit: mdm_dsp_crit {
4350                                         temperature = <110000>;
4351                                         hysteresis = <2000>;
4352                                         type = "critical";
4353                                 };
4354                         };
4355                 };
4356
4357                 npu-thermal {
4358                         polling-delay-passive = <250>;
4359                         polling-delay = <0>;
4360
4361                         thermal-sensors = <&tsens1 8>;
4362
4363                         trips {
4364                                 npu_alert0: trip-point0 {
4365                                         temperature = <90000>;
4366                                         hysteresis = <2000>;
4367                                         type = "hot";
4368                                 };
4369
4370                                 npu_crit: npu_crit {
4371                                         temperature = <110000>;
4372                                         hysteresis = <2000>;
4373                                         type = "critical";
4374                                 };
4375                         };
4376                 };
4377
4378                 video-thermal {
4379                         polling-delay-passive = <250>;
4380                         polling-delay = <0>;
4381
4382                         thermal-sensors = <&tsens1 9>;
4383
4384                         trips {
4385                                 video_alert0: trip-point0 {
4386                                         temperature = <90000>;
4387                                         hysteresis = <2000>;
4388                                         type = "hot";
4389                                 };
4390
4391                                 video_crit: video_crit {
4392                                         temperature = <110000>;
4393                                         hysteresis = <2000>;
4394                                         type = "critical";
4395                                 };
4396                         };
4397                 };
4398         };
4399
4400         timer {
4401                 compatible = "arm,armv8-timer";
4402                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4403                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4404                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4405                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4406         };
4407 };