arch/arm64/boot/dts/qcom/sc7180.dtsi

   1 // SPDX-License-Identifier: BSD-3-Clause
   2 /*
   3  * SC7180 SoC device tree source
   4  *
   5  * Copyright (c) 2019-2020, The Linux Foundation. All rights reserved.
   6  */
   7
   8 #include <dt-bindings/clock/qcom,dispcc-sc7180.h>
   9 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
  10 #include <dt-bindings/clock/qcom,gpucc-sc7180.h>
  11 #include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
  12 #include <dt-bindings/clock/qcom,rpmh.h>
  13 #include <dt-bindings/clock/qcom,videocc-sc7180.h>
  14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
  15 #include <dt-bindings/interconnect/qcom,sc7180.h>
  16 #include <dt-bindings/interrupt-controller/arm-gic.h>
  17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
  18 #include <dt-bindings/power/qcom-aoss-qmp.h>
  19 #include <dt-bindings/power/qcom-rpmpd.h>
  20 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
  21 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
  22 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
  23 #include <dt-bindings/thermal/thermal.h>
  24
  25 / {
  26         interrupt-parent = <&intc>;
  27
  28         #address-cells = <2>;
  29         #size-cells = <2>;
  30
  31         chosen { };
  32
  33         aliases {
  34                 mmc1 = &sdhc_1;
  35                 mmc2 = &sdhc_2;
  36                 i2c0 = &i2c0;
  37                 i2c1 = &i2c1;
  38                 i2c2 = &i2c2;
  39                 i2c3 = &i2c3;
  40                 i2c4 = &i2c4;
  41                 i2c5 = &i2c5;
  42                 i2c6 = &i2c6;
  43                 i2c7 = &i2c7;
  44                 i2c8 = &i2c8;
  45                 i2c9 = &i2c9;
  46                 i2c10 = &i2c10;
  47                 i2c11 = &i2c11;
  48                 spi0 = &spi0;
  49                 spi1 = &spi1;
  50                 spi3 = &spi3;
  51                 spi5 = &spi5;
  52                 spi6 = &spi6;
  53                 spi8 = &spi8;
  54                 spi10 = &spi10;
  55                 spi11 = &spi11;
  56         };
  57
  58         clocks {
  59                 xo_board: xo-board {
  60                         compatible = "fixed-clock";
  61                         clock-frequency = <38400000>;
  62                         #clock-cells = <0>;
  63                 };
  64
  65                 sleep_clk: sleep-clk {
  66                         compatible = "fixed-clock";
  67                         clock-frequency = <32764>;
  68                         #clock-cells = <0>;
  69                 };
  70         };
  71
  72         reserved_memory: reserved-memory {
  73                 #address-cells = <2>;
  74                 #size-cells = <2>;
  75                 ranges;
  76
  77                 hyp_mem: memory@80000000 {
  78                         reg = <0x0 0x80000000 0x0 0x600000>;
  79                         no-map;
  80                 };
  81
  82                 xbl_mem: memory@80600000 {
  83                         reg = <0x0 0x80600000 0x0 0x200000>;
  84                         no-map;
  85                 };
  86
  87                 aop_mem: memory@80800000 {
  88                         reg = <0x0 0x80800000 0x0 0x20000>;
  89                         no-map;
  90                 };
  91
  92                 aop_cmd_db_mem: memory@80820000 {
  93                         reg = <0x0 0x80820000 0x0 0x20000>;
  94                         compatible = "qcom,cmd-db";
  95                         no-map;
  96                 };
  97
  98                 sec_apps_mem: memory@808ff000 {
  99                         reg = <0x0 0x808ff000 0x0 0x1000>;
 100                         no-map;
 101                 };
 102
 103                 smem_mem: memory@80900000 {
 104                         reg = <0x0 0x80900000 0x0 0x200000>;
 105                         no-map;
 106                 };
 107
 108                 tz_mem: memory@80b00000 {
 109                         reg = <0x0 0x80b00000 0x0 0x3900000>;
 110                         no-map;
 111                 };
 112
 113                 rmtfs_mem: memory@84400000 {
 114                         compatible = "qcom,rmtfs-mem";
 115                         reg = <0x0 0x84400000 0x0 0x200000>;
 116                         no-map;
 117
 118                         qcom,client-id = <1>;
 119                         qcom,vmid = <15>;
 120                 };
 121         };
 122
 123         cpus {
 124                 #address-cells = <2>;
 125                 #size-cells = <0>;
 126
 127                 CPU0: cpu@0 {
 128                         device_type = "cpu";
 129                         compatible = "qcom,kryo468";
 130                         reg = <0x0 0x0>;
 131                         enable-method = "psci";
 132                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 133                                            &LITTLE_CPU_SLEEP_1
 134                                            &CLUSTER_SLEEP_0>;
 135                         capacity-dmips-mhz = <1024>;
 136                         dynamic-power-coefficient = <100>;
 137                         operating-points-v2 = <&cpu0_opp_table>;
 138                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 139                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 140                         next-level-cache = <&L2_0>;
 141                         #cooling-cells = <2>;
 142                         qcom,freq-domain = <&cpufreq_hw 0>;
 143                         L2_0: l2-cache {
 144                                 compatible = "cache";
 145                                 next-level-cache = <&L3_0>;
 146                                 L3_0: l3-cache {
 147                                         compatible = "cache";
 148                                 };
 149                         };
 150                 };
 151
 152                 CPU1: cpu@100 {
 153                         device_type = "cpu";
 154                         compatible = "qcom,kryo468";
 155                         reg = <0x0 0x100>;
 156                         enable-method = "psci";
 157                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 158                                            &LITTLE_CPU_SLEEP_1
 159                                            &CLUSTER_SLEEP_0>;
 160                         capacity-dmips-mhz = <1024>;
 161                         dynamic-power-coefficient = <100>;
 162                         next-level-cache = <&L2_100>;
 163                         operating-points-v2 = <&cpu0_opp_table>;
 164                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 165                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 166                         #cooling-cells = <2>;
 167                         qcom,freq-domain = <&cpufreq_hw 0>;
 168                         L2_100: l2-cache {
 169                                 compatible = "cache";
 170                                 next-level-cache = <&L3_0>;
 171                         };
 172                 };
 173
 174                 CPU2: cpu@200 {
 175                         device_type = "cpu";
 176                         compatible = "qcom,kryo468";
 177                         reg = <0x0 0x200>;
 178                         enable-method = "psci";
 179                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 180                                            &LITTLE_CPU_SLEEP_1
 181                                            &CLUSTER_SLEEP_0>;
 182                         capacity-dmips-mhz = <1024>;
 183                         dynamic-power-coefficient = <100>;
 184                         next-level-cache = <&L2_200>;
 185                         operating-points-v2 = <&cpu0_opp_table>;
 186                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 187                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 188                         #cooling-cells = <2>;
 189                         qcom,freq-domain = <&cpufreq_hw 0>;
 190                         L2_200: l2-cache {
 191                                 compatible = "cache";
 192                                 next-level-cache = <&L3_0>;
 193                         };
 194                 };
 195
 196                 CPU3: cpu@300 {
 197                         device_type = "cpu";
 198                         compatible = "qcom,kryo468";
 199                         reg = <0x0 0x300>;
 200                         enable-method = "psci";
 201                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 202                                            &LITTLE_CPU_SLEEP_1
 203                                            &CLUSTER_SLEEP_0>;
 204                         capacity-dmips-mhz = <1024>;
 205                         dynamic-power-coefficient = <100>;
 206                         next-level-cache = <&L2_300>;
 207                         operating-points-v2 = <&cpu0_opp_table>;
 208                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 209                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 210                         #cooling-cells = <2>;
 211                         qcom,freq-domain = <&cpufreq_hw 0>;
 212                         L2_300: l2-cache {
 213                                 compatible = "cache";
 214                                 next-level-cache = <&L3_0>;
 215                         };
 216                 };
 217
 218                 CPU4: cpu@400 {
 219                         device_type = "cpu";
 220                         compatible = "qcom,kryo468";
 221                         reg = <0x0 0x400>;
 222                         enable-method = "psci";
 223                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 224                                            &LITTLE_CPU_SLEEP_1
 225                                            &CLUSTER_SLEEP_0>;
 226                         capacity-dmips-mhz = <1024>;
 227                         dynamic-power-coefficient = <100>;
 228                         next-level-cache = <&L2_400>;
 229                         operating-points-v2 = <&cpu0_opp_table>;
 230                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 231                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 232                         #cooling-cells = <2>;
 233                         qcom,freq-domain = <&cpufreq_hw 0>;
 234                         L2_400: l2-cache {
 235                                 compatible = "cache";
 236                                 next-level-cache = <&L3_0>;
 237                         };
 238                 };
 239
 240                 CPU5: cpu@500 {
 241                         device_type = "cpu";
 242                         compatible = "qcom,kryo468";
 243                         reg = <0x0 0x500>;
 244                         enable-method = "psci";
 245                         cpu-idle-states = <&LITTLE_CPU_SLEEP_0
 246                                            &LITTLE_CPU_SLEEP_1
 247                                            &CLUSTER_SLEEP_0>;
 248                         capacity-dmips-mhz = <1024>;
 249                         dynamic-power-coefficient = <100>;
 250                         next-level-cache = <&L2_500>;
 251                         operating-points-v2 = <&cpu0_opp_table>;
 252                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 253                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 254                         #cooling-cells = <2>;
 255                         qcom,freq-domain = <&cpufreq_hw 0>;
 256                         L2_500: l2-cache {
 257                                 compatible = "cache";
 258                                 next-level-cache = <&L3_0>;
 259                         };
 260                 };
 261
 262                 CPU6: cpu@600 {
 263                         device_type = "cpu";
 264                         compatible = "qcom,kryo468";
 265                         reg = <0x0 0x600>;
 266                         enable-method = "psci";
 267                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 268                                            &BIG_CPU_SLEEP_1
 269                                            &CLUSTER_SLEEP_0>;
 270                         capacity-dmips-mhz = <1740>;
 271                         dynamic-power-coefficient = <405>;
 272                         next-level-cache = <&L2_600>;
 273                         operating-points-v2 = <&cpu6_opp_table>;
 274                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 275                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 276                         #cooling-cells = <2>;
 277                         qcom,freq-domain = <&cpufreq_hw 1>;
 278                         L2_600: l2-cache {
 279                                 compatible = "cache";
 280                                 next-level-cache = <&L3_0>;
 281                         };
 282                 };
 283
 284                 CPU7: cpu@700 {
 285                         device_type = "cpu";
 286                         compatible = "qcom,kryo468";
 287                         reg = <0x0 0x700>;
 288                         enable-method = "psci";
 289                         cpu-idle-states = <&BIG_CPU_SLEEP_0
 290                                            &BIG_CPU_SLEEP_1
 291                                            &CLUSTER_SLEEP_0>;
 292                         capacity-dmips-mhz = <1740>;
 293                         dynamic-power-coefficient = <405>;
 294                         next-level-cache = <&L2_700>;
 295                         operating-points-v2 = <&cpu6_opp_table>;
 296                         interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>,
 297                                         <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
 298                         #cooling-cells = <2>;
 299                         qcom,freq-domain = <&cpufreq_hw 1>;
 300                         L2_700: l2-cache {
 301                                 compatible = "cache";
 302                                 next-level-cache = <&L3_0>;
 303                         };
 304                 };
 305
 306                 cpu-map {
 307                         cluster0 {
 308                                 core0 {
 309                                         cpu = <&CPU0>;
 310                                 };
 311
 312                                 core1 {
 313                                         cpu = <&CPU1>;
 314                                 };
 315
 316                                 core2 {
 317                                         cpu = <&CPU2>;
 318                                 };
 319
 320                                 core3 {
 321                                         cpu = <&CPU3>;
 322                                 };
 323
 324                                 core4 {
 325                                         cpu = <&CPU4>;
 326                                 };
 327
 328                                 core5 {
 329                                         cpu = <&CPU5>;
 330                                 };
 331
 332                                 core6 {
 333                                         cpu = <&CPU6>;
 334                                 };
 335
 336                                 core7 {
 337                                         cpu = <&CPU7>;
 338                                 };
 339                         };
 340                 };
 341
 342                 idle-states {
 343                         entry-method = "psci";
 344
 345                         LITTLE_CPU_SLEEP_0: cpu-sleep-0-0 {
 346                                 compatible = "arm,idle-state";
 347                                 idle-state-name = "little-power-down";
 348                                 arm,psci-suspend-param = <0x40000003>;
 349                                 entry-latency-us = <549>;
 350                                 exit-latency-us = <901>;
 351                                 min-residency-us = <1774>;
 352                                 local-timer-stop;
 353                         };
 354
 355                         LITTLE_CPU_SLEEP_1: cpu-sleep-0-1 {
 356                                 compatible = "arm,idle-state";
 357                                 idle-state-name = "little-rail-power-down";
 358                                 arm,psci-suspend-param = <0x40000004>;
 359                                 entry-latency-us = <702>;
 360                                 exit-latency-us = <915>;
 361                                 min-residency-us = <4001>;
 362                                 local-timer-stop;
 363                         };
 364
 365                         BIG_CPU_SLEEP_0: cpu-sleep-1-0 {
 366                                 compatible = "arm,idle-state";
 367                                 idle-state-name = "big-power-down";
 368                                 arm,psci-suspend-param = <0x40000003>;
 369                                 entry-latency-us = <523>;
 370                                 exit-latency-us = <1244>;
 371                                 min-residency-us = <2207>;
 372                                 local-timer-stop;
 373                         };
 374
 375                         BIG_CPU_SLEEP_1: cpu-sleep-1-1 {
 376                                 compatible = "arm,idle-state";
 377                                 idle-state-name = "big-rail-power-down";
 378                                 arm,psci-suspend-param = <0x40000004>;
 379                                 entry-latency-us = <526>;
 380                                 exit-latency-us = <1854>;
 381                                 min-residency-us = <5555>;
 382                                 local-timer-stop;
 383                         };
 384
 385                         CLUSTER_SLEEP_0: cluster-sleep-0 {
 386                                 compatible = "arm,idle-state";
 387                                 idle-state-name = "cluster-power-down";
 388                                 arm,psci-suspend-param = <0x40003444>;
 389                                 entry-latency-us = <3263>;
 390                                 exit-latency-us = <6562>;
 391                                 min-residency-us = <9926>;
 392                                 local-timer-stop;
 393                         };
 394                 };
 395         };
 396
 397         cpu0_opp_table: cpu0_opp_table {
 398                 compatible = "operating-points-v2";
 399                 opp-shared;
 400
 401                 cpu0_opp1: opp-300000000 {
 402                         opp-hz = /bits/ 64 <300000000>;
 403                         opp-peak-kBps = <1200000 4800000>;
 404                 };
 405
 406                 cpu0_opp2: opp-576000000 {
 407                         opp-hz = /bits/ 64 <576000000>;
 408                         opp-peak-kBps = <1200000 4800000>;
 409                 };
 410
 411                 cpu0_opp3: opp-768000000 {
 412                         opp-hz = /bits/ 64 <768000000>;
 413                         opp-peak-kBps = <1200000 4800000>;
 414                 };
 415
 416                 cpu0_opp4: opp-1017600000 {
 417                         opp-hz = /bits/ 64 <1017600000>;
 418                         opp-peak-kBps = <1804000 8908800>;
 419                 };
 420
 421                 cpu0_opp5: opp-1248000000 {
 422                         opp-hz = /bits/ 64 <1248000000>;
 423                         opp-peak-kBps = <2188000 12902400>;
 424                 };
 425
 426                 cpu0_opp6: opp-1324800000 {
 427                         opp-hz = /bits/ 64 <1324800000>;
 428                         opp-peak-kBps = <2188000 12902400>;
 429                 };
 430
 431                 cpu0_opp7: opp-1516800000 {
 432                         opp-hz = /bits/ 64 <1516800000>;
 433                         opp-peak-kBps = <3072000 15052800>;
 434                 };
 435
 436                 cpu0_opp8: opp-1612800000 {
 437                         opp-hz = /bits/ 64 <1612800000>;
 438                         opp-peak-kBps = <3072000 15052800>;
 439                 };
 440
 441                 cpu0_opp9: opp-1708800000 {
 442                         opp-hz = /bits/ 64 <1708800000>;
 443                         opp-peak-kBps = <3072000 15052800>;
 444                 };
 445
 446                 cpu0_opp10: opp-1804800000 {
 447                         opp-hz = /bits/ 64 <1804800000>;
 448                         opp-peak-kBps = <4068000 22425600>;
 449                 };
 450         };
 451
 452         cpu6_opp_table: cpu6_opp_table {
 453                 compatible = "operating-points-v2";
 454                 opp-shared;
 455
 456                 cpu6_opp1: opp-300000000 {
 457                         opp-hz = /bits/ 64 <300000000>;
 458                         opp-peak-kBps = <2188000 8908800>;
 459                 };
 460
 461                 cpu6_opp2: opp-652800000 {
 462                         opp-hz = /bits/ 64 <652800000>;
 463                         opp-peak-kBps = <2188000 8908800>;
 464                 };
 465
 466                 cpu6_opp3: opp-825600000 {
 467                         opp-hz = /bits/ 64 <825600000>;
 468                         opp-peak-kBps = <2188000 8908800>;
 469                 };
 470
 471                 cpu6_opp4: opp-979200000 {
 472                         opp-hz = /bits/ 64 <979200000>;
 473                         opp-peak-kBps = <2188000 8908800>;
 474                 };
 475
 476                 cpu6_opp5: opp-1113600000 {
 477                         opp-hz = /bits/ 64 <1113600000>;
 478                         opp-peak-kBps = <2188000 8908800>;
 479                 };
 480
 481                 cpu6_opp6: opp-1267200000 {
 482                         opp-hz = /bits/ 64 <1267200000>;
 483                         opp-peak-kBps = <4068000 12902400>;
 484                 };
 485
 486                 cpu6_opp7: opp-1555200000 {
 487                         opp-hz = /bits/ 64 <1555200000>;
 488                         opp-peak-kBps = <4068000 15052800>;
 489                 };
 490
 491                 cpu6_opp8: opp-1708800000 {
 492                         opp-hz = /bits/ 64 <1708800000>;
 493                         opp-peak-kBps = <6220000 19353600>;
 494                 };
 495
 496                 cpu6_opp9: opp-1843200000 {
 497                         opp-hz = /bits/ 64 <1843200000>;
 498                         opp-peak-kBps = <6220000 19353600>;
 499                 };
 500
 501                 cpu6_opp10: opp-1900800000 {
 502                         opp-hz = /bits/ 64 <1900800000>;
 503                         opp-peak-kBps = <6220000 22425600>;
 504                 };
 505
 506                 cpu6_opp11: opp-1996800000 {
 507                         opp-hz = /bits/ 64 <1996800000>;
 508                         opp-peak-kBps = <6220000 22425600>;
 509                 };
 510
 511                 cpu6_opp12: opp-2112000000 {
 512                         opp-hz = /bits/ 64 <2112000000>;
 513                         opp-peak-kBps = <6220000 22425600>;
 514                 };
 515
 516                 cpu6_opp13: opp-2208000000 {
 517                         opp-hz = /bits/ 64 <2208000000>;
 518                         opp-peak-kBps = <7216000 22425600>;
 519                 };
 520
 521                 cpu6_opp14: opp-2323200000 {
 522                         opp-hz = /bits/ 64 <2323200000>;
 523                         opp-peak-kBps = <7216000 22425600>;
 524                 };
 525
 526                 cpu6_opp15: opp-2400000000 {
 527                         opp-hz = /bits/ 64 <2400000000>;
 528                         opp-peak-kBps = <8532000 23347200>;
 529                 };
 530
 531                 cpu6_opp16: opp-2553600000 {
 532                         opp-hz = /bits/ 64 <2553600000>;
 533                         opp-peak-kBps = <8532000 23347200>;
 534                 };
 535         };
 536
 537         memory@80000000 {
 538                 device_type = "memory";
 539                 /* We expect the bootloader to fill in the size */
 540                 reg = <0 0x80000000 0 0>;
 541         };
 542
 543         pmu {
 544                 compatible = "arm,armv8-pmuv3";
 545                 interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
 546         };
 547
 548         firmware {
 549                 scm {
 550                         compatible = "qcom,scm-sc7180", "qcom,scm";
 551                 };
 552         };
 553
 554         tcsr_mutex: hwlock {
 555                 compatible = "qcom,tcsr-mutex";
 556                 syscon = <&tcsr_mutex_regs 0 0x1000>;
 557                 #hwlock-cells = <1>;
 558         };
 559
 560         smem {
 561                 compatible = "qcom,smem";
 562                 memory-region = <&smem_mem>;
 563                 hwlocks = <&tcsr_mutex 3>;
 564         };
 565
 566         smp2p-cdsp {
 567                 compatible = "qcom,smp2p";
 568                 qcom,smem = <94>, <432>;
 569
 570                 interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
 571
 572                 mboxes = <&apss_shared 6>;
 573
 574                 qcom,local-pid = <0>;
 575                 qcom,remote-pid = <5>;
 576
 577                 cdsp_smp2p_out: master-kernel {
 578                         qcom,entry-name = "master-kernel";
 579                         #qcom,smem-state-cells = <1>;
 580                 };
 581
 582                 cdsp_smp2p_in: slave-kernel {
 583                         qcom,entry-name = "slave-kernel";
 584
 585                         interrupt-controller;
 586                         #interrupt-cells = <2>;
 587                 };
 588         };
 589
 590         smp2p-lpass {
 591                 compatible = "qcom,smp2p";
 592                 qcom,smem = <443>, <429>;
 593
 594                 interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
 595
 596                 mboxes = <&apss_shared 10>;
 597
 598                 qcom,local-pid = <0>;
 599                 qcom,remote-pid = <2>;
 600
 601                 adsp_smp2p_out: master-kernel {
 602                         qcom,entry-name = "master-kernel";
 603                         #qcom,smem-state-cells = <1>;
 604                 };
 605
 606                 adsp_smp2p_in: slave-kernel {
 607                         qcom,entry-name = "slave-kernel";
 608
 609                         interrupt-controller;
 610                         #interrupt-cells = <2>;
 611                 };
 612         };
 613
 614         smp2p-mpss {
 615                 compatible = "qcom,smp2p";
 616                 qcom,smem = <435>, <428>;
 617                 interrupts = <GIC_SPI 451 IRQ_TYPE_EDGE_RISING>;
 618                 mboxes = <&apss_shared 14>;
 619                 qcom,local-pid = <0>;
 620                 qcom,remote-pid = <1>;
 621
 622                 modem_smp2p_out: master-kernel {
 623                         qcom,entry-name = "master-kernel";
 624                         #qcom,smem-state-cells = <1>;
 625                 };
 626
 627                 modem_smp2p_in: slave-kernel {
 628                         qcom,entry-name = "slave-kernel";
 629                         interrupt-controller;
 630                         #interrupt-cells = <2>;
 631                 };
 632
 633                 ipa_smp2p_out: ipa-ap-to-modem {
 634                         qcom,entry-name = "ipa";
 635                         #qcom,smem-state-cells = <1>;
 636                 };
 637
 638                 ipa_smp2p_in: ipa-modem-to-ap {
 639                         qcom,entry-name = "ipa";
 640                         interrupt-controller;
 641                         #interrupt-cells = <2>;
 642                 };
 643         };
 644
 645         psci {
 646                 compatible = "arm,psci-1.0";
 647                 method = "smc";
 648         };
 649
 650         soc: soc@0 {
 651                 #address-cells = <2>;
 652                 #size-cells = <2>;
 653                 ranges = <0 0 0 0 0x10 0>;
 654                 dma-ranges = <0 0 0 0 0x10 0>;
 655                 compatible = "simple-bus";
 656
 657                 gcc: clock-controller@100000 {
 658                         compatible = "qcom,gcc-sc7180";
 659                         reg = <0 0x00100000 0 0x1f0000>;
 660                         clocks = <&rpmhcc RPMH_CXO_CLK>,
 661                                  <&rpmhcc RPMH_CXO_CLK_A>,
 662                                  <&sleep_clk>;
 663                         clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
 664                         #clock-cells = <1>;
 665                         #reset-cells = <1>;
 666                         #power-domain-cells = <1>;
 667                 };
 668
 669                 qfprom: efuse@784000 {
 670                         compatible = "qcom,sc7180-qfprom", "qcom,qfprom";
 671                         reg = <0 0x00784000 0 0x8ff>,
 672                               <0 0x00780000 0 0x7a0>,
 673                               <0 0x00782000 0 0x100>,
 674                               <0 0x00786000 0 0x1fff>;
 675
 676                         clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>;
 677                         clock-names = "core";
 678                         #address-cells = <1>;
 679                         #size-cells = <1>;
 680
 681                         qusb2p_hstx_trim: hstx-trim-primary@25b {
 682                                 reg = <0x25b 0x1>;
 683                                 bits = <1 3>;
 684                         };
 685                 };
 686
 687                 sdhc_1: sdhci@7c4000 {
 688                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
 689                         reg = <0 0x7c4000 0 0x1000>,
 690                                 <0 0x07c5000 0 0x1000>;
 691                         reg-names = "hc", "cqhci";
 692
 693                         iommus = <&apps_smmu 0x60 0x0>;
 694                         interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>,
 695                                         <GIC_SPI 644 IRQ_TYPE_LEVEL_HIGH>;
 696                         interrupt-names = "hc_irq", "pwr_irq";
 697
 698                         clocks = <&gcc GCC_SDCC1_APPS_CLK>,
 699                                         <&gcc GCC_SDCC1_AHB_CLK>;
 700                         clock-names = "core", "iface";
 701                         interconnects = <&aggre1_noc MASTER_EMMC 0 &mc_virt SLAVE_EBI1 0>,
 702                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_EMMC_CFG 0>;
 703                         interconnect-names = "sdhc-ddr","cpu-sdhc";
 704                         power-domains = <&rpmhpd SC7180_CX>;
 705                         operating-points-v2 = <&sdhc1_opp_table>;
 706
 707                         bus-width = <8>;
 708                         non-removable;
 709                         supports-cqe;
 710
 711                         mmc-ddr-1_8v;
 712                         mmc-hs200-1_8v;
 713                         mmc-hs400-1_8v;
 714                         mmc-hs400-enhanced-strobe;
 715
 716                         status = "disabled";
 717
 718                         sdhc1_opp_table: sdhc1-opp-table {
 719                                 compatible = "operating-points-v2";
 720
 721                                 opp-100000000 {
 722                                         opp-hz = /bits/ 64 <100000000>;
 723                                         required-opps = <&rpmhpd_opp_low_svs>;
 724                                         opp-peak-kBps = <100000 100000>;
 725                                         opp-avg-kBps = <100000 50000>;
 726                                 };
 727
 728                                 opp-384000000 {
 729                                         opp-hz = /bits/ 64 <384000000>;
 730                                         required-opps = <&rpmhpd_opp_svs_l1>;
 731                                         opp-peak-kBps = <600000 900000>;
 732                                         opp-avg-kBps = <261438 300000>;
 733                                 };
 734                         };
 735                 };
 736
 737                 qup_opp_table: qup-opp-table {
 738                         compatible = "operating-points-v2";
 739
 740                         opp-75000000 {
 741                                 opp-hz = /bits/ 64 <75000000>;
 742                                 required-opps = <&rpmhpd_opp_low_svs>;
 743                         };
 744
 745                         opp-100000000 {
 746                                 opp-hz = /bits/ 64 <100000000>;
 747                                 required-opps = <&rpmhpd_opp_svs>;
 748                         };
 749
 750                         opp-128000000 {
 751                                 opp-hz = /bits/ 64 <128000000>;
 752                                 required-opps = <&rpmhpd_opp_nom>;
 753                         };
 754                 };
 755
 756                 qupv3_id_0: geniqup@8c0000 {
 757                         compatible = "qcom,geni-se-qup";
 758                         reg = <0 0x008c0000 0 0x6000>;
 759                         clock-names = "m-ahb", "s-ahb";
 760                         clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 761                                  <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 762                         #address-cells = <2>;
 763                         #size-cells = <2>;
 764                         ranges;
 765                         iommus = <&apps_smmu 0x43 0x0>;
 766                         interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>;
 767                         interconnect-names = "qup-core";
 768                         status = "disabled";
 769
 770                         i2c0: i2c@880000 {
 771                                 compatible = "qcom,geni-i2c";
 772                                 reg = <0 0x00880000 0 0x4000>;
 773                                 clock-names = "se";
 774                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 775                                 pinctrl-names = "default";
 776                                 pinctrl-0 = <&qup_i2c0_default>;
 777                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 778                                 #address-cells = <1>;
 779                                 #size-cells = <0>;
 780                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 781                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 782                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 783                                 interconnect-names = "qup-core", "qup-config",
 784                                                         "qup-memory";
 785                                 status = "disabled";
 786                         };
 787
 788                         spi0: spi@880000 {
 789                                 compatible = "qcom,geni-spi";
 790                                 reg = <0 0x00880000 0 0x4000>;
 791                                 clock-names = "se";
 792                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 793                                 pinctrl-names = "default";
 794                                 pinctrl-0 = <&qup_spi0_default>;
 795                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 796                                 #address-cells = <1>;
 797                                 #size-cells = <0>;
 798                                 power-domains = <&rpmhpd SC7180_CX>;
 799                                 operating-points-v2 = <&qup_opp_table>;
 800                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 801                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 802                                 interconnect-names = "qup-core", "qup-config";
 803                                 status = "disabled";
 804                         };
 805
 806                         uart0: serial@880000 {
 807                                 compatible = "qcom,geni-uart";
 808                                 reg = <0 0x00880000 0 0x4000>;
 809                                 clock-names = "se";
 810                                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 811                                 pinctrl-names = "default";
 812                                 pinctrl-0 = <&qup_uart0_default>;
 813                                 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>;
 814                                 power-domains = <&rpmhpd SC7180_CX>;
 815                                 operating-points-v2 = <&qup_opp_table>;
 816                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 817                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 818                                 interconnect-names = "qup-core", "qup-config";
 819                                 status = "disabled";
 820                         };
 821
 822                         i2c1: i2c@884000 {
 823                                 compatible = "qcom,geni-i2c";
 824                                 reg = <0 0x00884000 0 0x4000>;
 825                                 clock-names = "se";
 826                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 827                                 pinctrl-names = "default";
 828                                 pinctrl-0 = <&qup_i2c1_default>;
 829                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 830                                 #address-cells = <1>;
 831                                 #size-cells = <0>;
 832                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 833                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 834                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 835                                 interconnect-names = "qup-core", "qup-config",
 836                                                         "qup-memory";
 837                                 status = "disabled";
 838                         };
 839
 840                         spi1: spi@884000 {
 841                                 compatible = "qcom,geni-spi";
 842                                 reg = <0 0x00884000 0 0x4000>;
 843                                 clock-names = "se";
 844                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 845                                 pinctrl-names = "default";
 846                                 pinctrl-0 = <&qup_spi1_default>;
 847                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 848                                 #address-cells = <1>;
 849                                 #size-cells = <0>;
 850                                 power-domains = <&rpmhpd SC7180_CX>;
 851                                 operating-points-v2 = <&qup_opp_table>;
 852                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 853                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 854                                 interconnect-names = "qup-core", "qup-config";
 855                                 status = "disabled";
 856                         };
 857
 858                         uart1: serial@884000 {
 859                                 compatible = "qcom,geni-uart";
 860                                 reg = <0 0x00884000 0 0x4000>;
 861                                 clock-names = "se";
 862                                 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
 863                                 pinctrl-names = "default";
 864                                 pinctrl-0 = <&qup_uart1_default>;
 865                                 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>;
 866                                 power-domains = <&rpmhpd SC7180_CX>;
 867                                 operating-points-v2 = <&qup_opp_table>;
 868                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 869                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 870                                 interconnect-names = "qup-core", "qup-config";
 871                                 status = "disabled";
 872                         };
 873
 874                         i2c2: i2c@888000 {
 875                                 compatible = "qcom,geni-i2c";
 876                                 reg = <0 0x00888000 0 0x4000>;
 877                                 clock-names = "se";
 878                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 879                                 pinctrl-names = "default";
 880                                 pinctrl-0 = <&qup_i2c2_default>;
 881                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 882                                 #address-cells = <1>;
 883                                 #size-cells = <0>;
 884                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 885                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 886                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 887                                 interconnect-names = "qup-core", "qup-config",
 888                                                         "qup-memory";
 889                                 status = "disabled";
 890                         };
 891
 892                         uart2: serial@888000 {
 893                                 compatible = "qcom,geni-uart";
 894                                 reg = <0 0x00888000 0 0x4000>;
 895                                 clock-names = "se";
 896                                 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
 897                                 pinctrl-names = "default";
 898                                 pinctrl-0 = <&qup_uart2_default>;
 899                                 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
 900                                 power-domains = <&rpmhpd SC7180_CX>;
 901                                 operating-points-v2 = <&qup_opp_table>;
 902                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 903                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 904                                 interconnect-names = "qup-core", "qup-config";
 905                                 status = "disabled";
 906                         };
 907
 908                         i2c3: i2c@88c000 {
 909                                 compatible = "qcom,geni-i2c";
 910                                 reg = <0 0x0088c000 0 0x4000>;
 911                                 clock-names = "se";
 912                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 913                                 pinctrl-names = "default";
 914                                 pinctrl-0 = <&qup_i2c3_default>;
 915                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 916                                 #address-cells = <1>;
 917                                 #size-cells = <0>;
 918                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 919                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 920                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 921                                 interconnect-names = "qup-core", "qup-config",
 922                                                         "qup-memory";
 923                                 status = "disabled";
 924                         };
 925
 926                         spi3: spi@88c000 {
 927                                 compatible = "qcom,geni-spi";
 928                                 reg = <0 0x0088c000 0 0x4000>;
 929                                 clock-names = "se";
 930                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 931                                 pinctrl-names = "default";
 932                                 pinctrl-0 = <&qup_spi3_default>;
 933                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 934                                 #address-cells = <1>;
 935                                 #size-cells = <0>;
 936                                 power-domains = <&rpmhpd SC7180_CX>;
 937                                 operating-points-v2 = <&qup_opp_table>;
 938                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 939                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 940                                 interconnect-names = "qup-core", "qup-config";
 941                                 status = "disabled";
 942                         };
 943
 944                         uart3: serial@88c000 {
 945                                 compatible = "qcom,geni-uart";
 946                                 reg = <0 0x0088c000 0 0x4000>;
 947                                 clock-names = "se";
 948                                 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
 949                                 pinctrl-names = "default";
 950                                 pinctrl-0 = <&qup_uart3_default>;
 951                                 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>;
 952                                 power-domains = <&rpmhpd SC7180_CX>;
 953                                 operating-points-v2 = <&qup_opp_table>;
 954                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 955                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 956                                 interconnect-names = "qup-core", "qup-config";
 957                                 status = "disabled";
 958                         };
 959
 960                         i2c4: i2c@890000 {
 961                                 compatible = "qcom,geni-i2c";
 962                                 reg = <0 0x00890000 0 0x4000>;
 963                                 clock-names = "se";
 964                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 965                                 pinctrl-names = "default";
 966                                 pinctrl-0 = <&qup_i2c4_default>;
 967                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 968                                 #address-cells = <1>;
 969                                 #size-cells = <0>;
 970                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 971                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
 972                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
 973                                 interconnect-names = "qup-core", "qup-config",
 974                                                         "qup-memory";
 975                                 status = "disabled";
 976                         };
 977
 978                         uart4: serial@890000 {
 979                                 compatible = "qcom,geni-uart";
 980                                 reg = <0 0x00890000 0 0x4000>;
 981                                 clock-names = "se";
 982                                 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
 983                                 pinctrl-names = "default";
 984                                 pinctrl-0 = <&qup_uart4_default>;
 985                                 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>;
 986                                 power-domains = <&rpmhpd SC7180_CX>;
 987                                 operating-points-v2 = <&qup_opp_table>;
 988                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
 989                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
 990                                 interconnect-names = "qup-core", "qup-config";
 991                                 status = "disabled";
 992                         };
 993
 994                         i2c5: i2c@894000 {
 995                                 compatible = "qcom,geni-i2c";
 996                                 reg = <0 0x00894000 0 0x4000>;
 997                                 clock-names = "se";
 998                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 999                                 pinctrl-names = "default";
1000                                 pinctrl-0 = <&qup_i2c5_default>;
1001                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1002                                 #address-cells = <1>;
1003                                 #size-cells = <0>;
1004                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1005                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>,
1006                                                 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>;
1007                                 interconnect-names = "qup-core", "qup-config",
1008                                                         "qup-memory";
1009                                 status = "disabled";
1010                         };
1011
1012                         spi5: spi@894000 {
1013                                 compatible = "qcom,geni-spi";
1014                                 reg = <0 0x00894000 0 0x4000>;
1015                                 clock-names = "se";
1016                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1017                                 pinctrl-names = "default";
1018                                 pinctrl-0 = <&qup_spi5_default>;
1019                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1020                                 #address-cells = <1>;
1021                                 #size-cells = <0>;
1022                                 power-domains = <&rpmhpd SC7180_CX>;
1023                                 operating-points-v2 = <&qup_opp_table>;
1024                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1025                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1026                                 interconnect-names = "qup-core", "qup-config";
1027                                 status = "disabled";
1028                         };
1029
1030                         uart5: serial@894000 {
1031                                 compatible = "qcom,geni-uart";
1032                                 reg = <0 0x00894000 0 0x4000>;
1033                                 clock-names = "se";
1034                                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
1035                                 pinctrl-names = "default";
1036                                 pinctrl-0 = <&qup_uart5_default>;
1037                                 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>;
1038                                 power-domains = <&rpmhpd SC7180_CX>;
1039                                 operating-points-v2 = <&qup_opp_table>;
1040                                 interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
1041                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_0 0>;
1042                                 interconnect-names = "qup-core", "qup-config";
1043                                 status = "disabled";
1044                         };
1045                 };
1046
1047                 qupv3_id_1: geniqup@ac0000 {
1048                         compatible = "qcom,geni-se-qup";
1049                         reg = <0 0x00ac0000 0 0x6000>;
1050                         clock-names = "m-ahb", "s-ahb";
1051                         clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
1052                                  <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
1053                         #address-cells = <2>;
1054                         #size-cells = <2>;
1055                         ranges;
1056                         iommus = <&apps_smmu 0x4c3 0x0>;
1057                         interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>;
1058                         interconnect-names = "qup-core";
1059                         status = "disabled";
1060
1061                         i2c6: i2c@a80000 {
1062                                 compatible = "qcom,geni-i2c";
1063                                 reg = <0 0x00a80000 0 0x4000>;
1064                                 clock-names = "se";
1065                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1066                                 pinctrl-names = "default";
1067                                 pinctrl-0 = <&qup_i2c6_default>;
1068                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1069                                 #address-cells = <1>;
1070                                 #size-cells = <0>;
1071                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1072                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1073                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1074                                 interconnect-names = "qup-core", "qup-config",
1075                                                         "qup-memory";
1076                                 status = "disabled";
1077                         };
1078
1079                         spi6: spi@a80000 {
1080                                 compatible = "qcom,geni-spi";
1081                                 reg = <0 0x00a80000 0 0x4000>;
1082                                 clock-names = "se";
1083                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1084                                 pinctrl-names = "default";
1085                                 pinctrl-0 = <&qup_spi6_default>;
1086                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1087                                 #address-cells = <1>;
1088                                 #size-cells = <0>;
1089                                 power-domains = <&rpmhpd SC7180_CX>;
1090                                 operating-points-v2 = <&qup_opp_table>;
1091                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1092                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1093                                 interconnect-names = "qup-core", "qup-config";
1094                                 status = "disabled";
1095                         };
1096
1097                         uart6: serial@a80000 {
1098                                 compatible = "qcom,geni-uart";
1099                                 reg = <0 0x00a80000 0 0x4000>;
1100                                 clock-names = "se";
1101                                 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>;
1102                                 pinctrl-names = "default";
1103                                 pinctrl-0 = <&qup_uart6_default>;
1104                                 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>;
1105                                 power-domains = <&rpmhpd SC7180_CX>;
1106                                 operating-points-v2 = <&qup_opp_table>;
1107                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1108                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1109                                 interconnect-names = "qup-core", "qup-config";
1110                                 status = "disabled";
1111                         };
1112
1113                         i2c7: i2c@a84000 {
1114                                 compatible = "qcom,geni-i2c";
1115                                 reg = <0 0x00a84000 0 0x4000>;
1116                                 clock-names = "se";
1117                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1118                                 pinctrl-names = "default";
1119                                 pinctrl-0 = <&qup_i2c7_default>;
1120                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1121                                 #address-cells = <1>;
1122                                 #size-cells = <0>;
1123                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1124                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1125                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1126                                 interconnect-names = "qup-core", "qup-config",
1127                                                         "qup-memory";
1128                                 status = "disabled";
1129                         };
1130
1131                         uart7: serial@a84000 {
1132                                 compatible = "qcom,geni-uart";
1133                                 reg = <0 0x00a84000 0 0x4000>;
1134                                 clock-names = "se";
1135                                 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
1136                                 pinctrl-names = "default";
1137                                 pinctrl-0 = <&qup_uart7_default>;
1138                                 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
1139                                 power-domains = <&rpmhpd SC7180_CX>;
1140                                 operating-points-v2 = <&qup_opp_table>;
1141                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1142                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1143                                 interconnect-names = "qup-core", "qup-config";
1144                                 status = "disabled";
1145                         };
1146
1147                         i2c8: i2c@a88000 {
1148                                 compatible = "qcom,geni-i2c";
1149                                 reg = <0 0x00a88000 0 0x4000>;
1150                                 clock-names = "se";
1151                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1152                                 pinctrl-names = "default";
1153                                 pinctrl-0 = <&qup_i2c8_default>;
1154                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1155                                 #address-cells = <1>;
1156                                 #size-cells = <0>;
1157                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1158                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1159                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1160                                 interconnect-names = "qup-core", "qup-config",
1161                                                         "qup-memory";
1162                                 status = "disabled";
1163                         };
1164
1165                         spi8: spi@a88000 {
1166                                 compatible = "qcom,geni-spi";
1167                                 reg = <0 0x00a88000 0 0x4000>;
1168                                 clock-names = "se";
1169                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1170                                 pinctrl-names = "default";
1171                                 pinctrl-0 = <&qup_spi8_default>;
1172                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1173                                 #address-cells = <1>;
1174                                 #size-cells = <0>;
1175                                 power-domains = <&rpmhpd SC7180_CX>;
1176                                 operating-points-v2 = <&qup_opp_table>;
1177                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1178                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1179                                 interconnect-names = "qup-core", "qup-config";
1180                                 status = "disabled";
1181                         };
1182
1183                         uart8: serial@a88000 {
1184                                 compatible = "qcom,geni-debug-uart";
1185                                 reg = <0 0x00a88000 0 0x4000>;
1186                                 clock-names = "se";
1187                                 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>;
1188                                 pinctrl-names = "default";
1189                                 pinctrl-0 = <&qup_uart8_default>;
1190                                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
1191                                 power-domains = <&rpmhpd SC7180_CX>;
1192                                 operating-points-v2 = <&qup_opp_table>;
1193                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1194                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1195                                 interconnect-names = "qup-core", "qup-config";
1196                                 status = "disabled";
1197                         };
1198
1199                         i2c9: i2c@a8c000 {
1200                                 compatible = "qcom,geni-i2c";
1201                                 reg = <0 0x00a8c000 0 0x4000>;
1202                                 clock-names = "se";
1203                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1204                                 pinctrl-names = "default";
1205                                 pinctrl-0 = <&qup_i2c9_default>;
1206                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1207                                 #address-cells = <1>;
1208                                 #size-cells = <0>;
1209                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1210                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1211                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1212                                 interconnect-names = "qup-core", "qup-config",
1213                                                         "qup-memory";
1214                                 status = "disabled";
1215                         };
1216
1217                         uart9: serial@a8c000 {
1218                                 compatible = "qcom,geni-uart";
1219                                 reg = <0 0x00a8c000 0 0x4000>;
1220                                 clock-names = "se";
1221                                 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>;
1222                                 pinctrl-names = "default";
1223                                 pinctrl-0 = <&qup_uart9_default>;
1224                                 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>;
1225                                 power-domains = <&rpmhpd SC7180_CX>;
1226                                 operating-points-v2 = <&qup_opp_table>;
1227                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1228                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1229                                 interconnect-names = "qup-core", "qup-config";
1230                                 status = "disabled";
1231                         };
1232
1233                         i2c10: i2c@a90000 {
1234                                 compatible = "qcom,geni-i2c";
1235                                 reg = <0 0x00a90000 0 0x4000>;
1236                                 clock-names = "se";
1237                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1238                                 pinctrl-names = "default";
1239                                 pinctrl-0 = <&qup_i2c10_default>;
1240                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1241                                 #address-cells = <1>;
1242                                 #size-cells = <0>;
1243                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1244                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1245                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1246                                 interconnect-names = "qup-core", "qup-config",
1247                                                         "qup-memory";
1248                                 status = "disabled";
1249                         };
1250
1251                         spi10: spi@a90000 {
1252                                 compatible = "qcom,geni-spi";
1253                                 reg = <0 0x00a90000 0 0x4000>;
1254                                 clock-names = "se";
1255                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1256                                 pinctrl-names = "default";
1257                                 pinctrl-0 = <&qup_spi10_default>;
1258                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1259                                 #address-cells = <1>;
1260                                 #size-cells = <0>;
1261                                 power-domains = <&rpmhpd SC7180_CX>;
1262                                 operating-points-v2 = <&qup_opp_table>;
1263                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1264                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1265                                 interconnect-names = "qup-core", "qup-config";
1266                                 status = "disabled";
1267                         };
1268
1269                         uart10: serial@a90000 {
1270                                 compatible = "qcom,geni-uart";
1271                                 reg = <0 0x00a90000 0 0x4000>;
1272                                 clock-names = "se";
1273                                 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>;
1274                                 pinctrl-names = "default";
1275                                 pinctrl-0 = <&qup_uart10_default>;
1276                                 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
1277                                 power-domains = <&rpmhpd SC7180_CX>;
1278                                 operating-points-v2 = <&qup_opp_table>;
1279                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1280                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1281                                 interconnect-names = "qup-core", "qup-config";
1282                                 status = "disabled";
1283                         };
1284
1285                         i2c11: i2c@a94000 {
1286                                 compatible = "qcom,geni-i2c";
1287                                 reg = <0 0x00a94000 0 0x4000>;
1288                                 clock-names = "se";
1289                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1290                                 pinctrl-names = "default";
1291                                 pinctrl-0 = <&qup_i2c11_default>;
1292                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1293                                 #address-cells = <1>;
1294                                 #size-cells = <0>;
1295                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1296                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>,
1297                                                 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>;
1298                                 interconnect-names = "qup-core", "qup-config",
1299                                                         "qup-memory";
1300                                 status = "disabled";
1301                         };
1302
1303                         spi11: spi@a94000 {
1304                                 compatible = "qcom,geni-spi";
1305                                 reg = <0 0x00a94000 0 0x4000>;
1306                                 clock-names = "se";
1307                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1308                                 pinctrl-names = "default";
1309                                 pinctrl-0 = <&qup_spi11_default>;
1310                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1311                                 #address-cells = <1>;
1312                                 #size-cells = <0>;
1313                                 power-domains = <&rpmhpd SC7180_CX>;
1314                                 operating-points-v2 = <&qup_opp_table>;
1315                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1316                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1317                                 interconnect-names = "qup-core", "qup-config";
1318                                 status = "disabled";
1319                         };
1320
1321                         uart11: serial@a94000 {
1322                                 compatible = "qcom,geni-uart";
1323                                 reg = <0 0x00a94000 0 0x4000>;
1324                                 clock-names = "se";
1325                                 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
1326                                 pinctrl-names = "default";
1327                                 pinctrl-0 = <&qup_uart11_default>;
1328                                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
1329                                 power-domains = <&rpmhpd SC7180_CX>;
1330                                 operating-points-v2 = <&qup_opp_table>;
1331                                 interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
1332                                                 <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_QUP_1 0>;
1333                                 interconnect-names = "qup-core", "qup-config";
1334                                 status = "disabled";
1335                         };
1336                 };
1337
1338                 config_noc: interconnect@1500000 {
1339                         compatible = "qcom,sc7180-config-noc";
1340                         reg = <0 0x01500000 0 0x28000>;
1341                         #interconnect-cells = <2>;
1342                         qcom,bcm-voters = <&apps_bcm_voter>;
1343                 };
1344
1345                 system_noc: interconnect@1620000 {
1346                         compatible = "qcom,sc7180-system-noc";
1347                         reg = <0 0x01620000 0 0x17080>;
1348                         #interconnect-cells = <2>;
1349                         qcom,bcm-voters = <&apps_bcm_voter>;
1350                 };
1351
1352                 mc_virt: interconnect@1638000 {
1353                         compatible = "qcom,sc7180-mc-virt";
1354                         reg = <0 0x01638000 0 0x1000>;
1355                         #interconnect-cells = <2>;
1356                         qcom,bcm-voters = <&apps_bcm_voter>;
1357                 };
1358
1359                 qup_virt: interconnect@1650000 {
1360                         compatible = "qcom,sc7180-qup-virt";
1361                         reg = <0 0x01650000 0 0x1000>;
1362                         #interconnect-cells = <2>;
1363                         qcom,bcm-voters = <&apps_bcm_voter>;
1364                 };
1365
1366                 aggre1_noc: interconnect@16e0000 {
1367                         compatible = "qcom,sc7180-aggre1-noc";
1368                         reg = <0 0x016e0000 0 0x15080>;
1369                         #interconnect-cells = <2>;
1370                         qcom,bcm-voters = <&apps_bcm_voter>;
1371                 };
1372
1373                 aggre2_noc: interconnect@1705000 {
1374                         compatible = "qcom,sc7180-aggre2-noc";
1375                         reg = <0 0x01705000 0 0x9000>;
1376                         #interconnect-cells = <2>;
1377                         qcom,bcm-voters = <&apps_bcm_voter>;
1378                 };
1379
1380                 compute_noc: interconnect@170e000 {
1381                         compatible = "qcom,sc7180-compute-noc";
1382                         reg = <0 0x0170e000 0 0x6000>;
1383                         #interconnect-cells = <2>;
1384                         qcom,bcm-voters = <&apps_bcm_voter>;
1385                 };
1386
1387                 mmss_noc: interconnect@1740000 {
1388                         compatible = "qcom,sc7180-mmss-noc";
1389                         reg = <0 0x01740000 0 0x1c100>;
1390                         #interconnect-cells = <2>;
1391                         qcom,bcm-voters = <&apps_bcm_voter>;
1392                 };
1393
1394                 ipa_virt: interconnect@1e00000 {
1395                         compatible = "qcom,sc7180-ipa-virt";
1396                         reg = <0 0x01e00000 0 0x1000>;
1397                         #interconnect-cells = <2>;
1398                         qcom,bcm-voters = <&apps_bcm_voter>;
1399                 };
1400
1401                 ipa: ipa@1e40000 {
1402                         compatible = "qcom,sc7180-ipa";
1403
1404                         iommus = <&apps_smmu 0x440 0x0>,
1405                                  <&apps_smmu 0x442 0x0>;
1406                         reg = <0 0x1e40000 0 0x7000>,
1407                               <0 0x1e47000 0 0x2000>,
1408                               <0 0x1e04000 0 0x2c000>;
1409                         reg-names = "ipa-reg",
1410                                     "ipa-shared",
1411                                     "gsi";
1412
1413                         interrupts-extended = <&intc GIC_SPI 311 IRQ_TYPE_EDGE_RISING>,
1414                                               <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>,
1415                                               <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
1416                                               <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>;
1417                         interrupt-names = "ipa",
1418                                           "gsi",
1419                                           "ipa-clock-query",
1420                                           "ipa-setup-ready";
1421
1422                         clocks = <&rpmhcc RPMH_IPA_CLK>;
1423                         clock-names = "core";
1424
1425                         interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>,
1426                                         <&aggre2_noc MASTER_IPA 0 &system_noc SLAVE_IMEM 0>,
1427                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_IPA_CFG 0>;
1428                         interconnect-names = "memory",
1429                                              "imem",
1430                                              "config";
1431
1432                         qcom,smem-states = <&ipa_smp2p_out 0>,
1433                                            <&ipa_smp2p_out 1>;
1434                         qcom,smem-state-names = "ipa-clock-enabled-valid",
1435                                                 "ipa-clock-enabled";
1436
1437                         status = "disabled";
1438                 };
1439
1440                 tcsr_mutex_regs: syscon@1f40000 {
1441                         compatible = "syscon";
1442                         reg = <0 0x01f40000 0 0x40000>;
1443                 };
1444
1445                 tcsr_regs: syscon@1fc0000 {
1446                         compatible = "syscon";
1447                         reg = <0 0x01fc0000 0 0x40000>;
1448                 };
1449
1450                 tlmm: pinctrl@3500000 {
1451                         compatible = "qcom,sc7180-pinctrl";
1452                         reg = <0 0x03500000 0 0x300000>,
1453                               <0 0x03900000 0 0x300000>,
1454                               <0 0x03d00000 0 0x300000>;
1455                         reg-names = "west", "north", "south";
1456                         interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
1457                         gpio-controller;
1458                         #gpio-cells = <2>;
1459                         interrupt-controller;
1460                         #interrupt-cells = <2>;
1461                         gpio-ranges = <&tlmm 0 0 120>;
1462                         wakeup-parent = <&pdc>;
1463
1464                         dp_hot_plug_det: dp-hot-plug-det {
1465                                 pinmux {
1466                                         pins = "gpio117";
1467                                         function = "dp_hot";
1468                                 };
1469
1470                                 pinconf {
1471                                         pins = "gpio117";
1472                                         bias-disable;
1473                                         input-enable;
1474                                 };
1475                         };
1476
1477                         qspi_clk: qspi-clk {
1478                                 pinmux {
1479                                         pins = "gpio63";
1480                                         function = "qspi_clk";
1481                                 };
1482                         };
1483
1484                         qspi_cs0: qspi-cs0 {
1485                                 pinmux {
1486                                         pins = "gpio68";
1487                                         function = "qspi_cs";
1488                                 };
1489                         };
1490
1491                         qspi_cs1: qspi-cs1 {
1492                                 pinmux {
1493                                         pins = "gpio72";
1494                                         function = "qspi_cs";
1495                                 };
1496                         };
1497
1498                         qspi_data01: qspi-data01 {
1499                                 pinmux-data {
1500                                         pins = "gpio64", "gpio65";
1501                                         function = "qspi_data";
1502                                 };
1503                         };
1504
1505                         qspi_data12: qspi-data12 {
1506                                 pinmux-data {
1507                                         pins = "gpio66", "gpio67";
1508                                         function = "qspi_data";
1509                                 };
1510                         };
1511
1512                         qup_i2c0_default: qup-i2c0-default {
1513                                 pinmux {
1514                                         pins = "gpio34", "gpio35";
1515                                         function = "qup00";
1516                                 };
1517                         };
1518
1519                         qup_i2c1_default: qup-i2c1-default {
1520                                 pinmux {
1521                                         pins = "gpio0", "gpio1";
1522                                         function = "qup01";
1523                                 };
1524                         };
1525
1526                         qup_i2c2_default: qup-i2c2-default {
1527                                 pinmux {
1528                                         pins = "gpio15", "gpio16";
1529                                         function = "qup02_i2c";
1530                                 };
1531                         };
1532
1533                         qup_i2c3_default: qup-i2c3-default {
1534                                 pinmux {
1535                                         pins = "gpio38", "gpio39";
1536                                         function = "qup03";
1537                                 };
1538                         };
1539
1540                         qup_i2c4_default: qup-i2c4-default {
1541                                 pinmux {
1542                                         pins = "gpio115", "gpio116";
1543                                         function = "qup04_i2c";
1544                                 };
1545                         };
1546
1547                         qup_i2c5_default: qup-i2c5-default {
1548                                 pinmux {
1549                                         pins = "gpio25", "gpio26";
1550                                         function = "qup05";
1551                                 };
1552                         };
1553
1554                         qup_i2c6_default: qup-i2c6-default {
1555                                 pinmux {
1556                                         pins = "gpio59", "gpio60";
1557                                         function = "qup10";
1558                                 };
1559                         };
1560
1561                         qup_i2c7_default: qup-i2c7-default {
1562                                 pinmux {
1563                                         pins = "gpio6", "gpio7";
1564                                         function = "qup11_i2c";
1565                                 };
1566                         };
1567
1568                         qup_i2c8_default: qup-i2c8-default {
1569                                 pinmux {
1570                                         pins = "gpio42", "gpio43";
1571                                         function = "qup12";
1572                                 };
1573                         };
1574
1575                         qup_i2c9_default: qup-i2c9-default {
1576                                 pinmux {
1577                                         pins = "gpio46", "gpio47";
1578                                         function = "qup13_i2c";
1579                                 };
1580                         };
1581
1582                         qup_i2c10_default: qup-i2c10-default {
1583                                 pinmux {
1584                                         pins = "gpio86", "gpio87";
1585                                         function = "qup14";
1586                                 };
1587                         };
1588
1589                         qup_i2c11_default: qup-i2c11-default {
1590                                 pinmux {
1591                                         pins = "gpio53", "gpio54";
1592                                         function = "qup15";
1593                                 };
1594                         };
1595
1596                         qup_spi0_default: qup-spi0-default {
1597                                 pinmux {
1598                                         pins = "gpio34", "gpio35",
1599                                                "gpio36", "gpio37";
1600                                         function = "qup00";
1601                                 };
1602                         };
1603
1604                         qup_spi0_cs_gpio: qup-spi0-cs-gpio {
1605                                 pinmux {
1606                                         pins = "gpio34", "gpio35",
1607                                                "gpio36";
1608                                         function = "qup00";
1609                                 };
1610
1611                                 pinmux-cs {
1612                                         pins = "gpio37";
1613                                         function = "gpio";
1614                                 };
1615                         };
1616
1617                         qup_spi1_default: qup-spi1-default {
1618                                 pinmux {
1619                                         pins = "gpio0", "gpio1",
1620                                                "gpio2", "gpio3";
1621                                         function = "qup01";
1622                                 };
1623                         };
1624
1625                         qup_spi1_cs_gpio: qup-spi1-cs-gpio {
1626                                 pinmux {
1627                                         pins = "gpio0", "gpio1",
1628                                                "gpio2";
1629                                         function = "qup01";
1630                                 };
1631
1632                                 pinmux-cs {
1633                                         pins = "gpio3";
1634                                         function = "gpio";
1635                                 };
1636                         };
1637
1638                         qup_spi3_default: qup-spi3-default {
1639                                 pinmux {
1640                                         pins = "gpio38", "gpio39",
1641                                                "gpio40", "gpio41";
1642                                         function = "qup03";
1643                                 };
1644                         };
1645
1646                         qup_spi3_cs_gpio: qup-spi3-cs-gpio {
1647                                 pinmux {
1648                                         pins = "gpio38", "gpio39",
1649                                                "gpio40";
1650                                         function = "qup03";
1651                                 };
1652
1653                                 pinmux-cs {
1654                                         pins = "gpio41";
1655                                         function = "gpio";
1656                                 };
1657                         };
1658
1659                         qup_spi5_default: qup-spi5-default {
1660                                 pinmux {
1661                                         pins = "gpio25", "gpio26",
1662                                                "gpio27", "gpio28";
1663                                         function = "qup05";
1664                                 };
1665                         };
1666
1667                         qup_spi5_cs_gpio: qup-spi5-cs-gpio {
1668                                 pinmux {
1669                                         pins = "gpio25", "gpio26",
1670                                                "gpio27";
1671                                         function = "qup05";
1672                                 };
1673
1674                                 pinmux-cs {
1675                                         pins = "gpio28";
1676                                         function = "gpio";
1677                                 };
1678                         };
1679
1680                         qup_spi6_default: qup-spi6-default {
1681                                 pinmux {
1682                                         pins = "gpio59", "gpio60",
1683                                                "gpio61", "gpio62";
1684                                         function = "qup10";
1685                                 };
1686                         };
1687
1688                         qup_spi6_cs_gpio: qup-spi6-cs-gpio {
1689                                 pinmux {
1690                                         pins = "gpio59", "gpio60",
1691                                                "gpio61";
1692                                         function = "qup10";
1693                                 };
1694
1695                                 pinmux-cs {
1696                                         pins = "gpio62";
1697                                         function = "gpio";
1698                                 };
1699                         };
1700
1701                         qup_spi8_default: qup-spi8-default {
1702                                 pinmux {
1703                                         pins = "gpio42", "gpio43",
1704                                                "gpio44", "gpio45";
1705                                         function = "qup12";
1706                                 };
1707                         };
1708
1709                         qup_spi8_cs_gpio: qup-spi8-cs-gpio {
1710                                 pinmux {
1711                                         pins = "gpio42", "gpio43",
1712                                                "gpio44";
1713                                         function = "qup12";
1714                                 };
1715
1716                                 pinmux-cs {
1717                                         pins = "gpio45";
1718                                         function = "gpio";
1719                                 };
1720                         };
1721
1722                         qup_spi10_default: qup-spi10-default {
1723                                 pinmux {
1724                                         pins = "gpio86", "gpio87",
1725                                                "gpio88", "gpio89";
1726                                         function = "qup14";
1727                                 };
1728                         };
1729
1730                         qup_spi10_cs_gpio: qup-spi10-cs-gpio {
1731                                 pinmux {
1732                                         pins = "gpio86", "gpio87",
1733                                                "gpio88";
1734                                         function = "qup14";
1735                                 };
1736
1737                                 pinmux-cs {
1738                                         pins = "gpio89";
1739                                         function = "gpio";
1740                                 };
1741                         };
1742
1743                         qup_spi11_default: qup-spi11-default {
1744                                 pinmux {
1745                                         pins = "gpio53", "gpio54",
1746                                                "gpio55", "gpio56";
1747                                         function = "qup15";
1748                                 };
1749                         };
1750
1751                         qup_spi11_cs_gpio: qup-spi11-cs-gpio {
1752                                 pinmux {
1753                                         pins = "gpio53", "gpio54",
1754                                                "gpio55";
1755                                         function = "qup15";
1756                                 };
1757
1758                                 pinmux-cs {
1759                                         pins = "gpio56";
1760                                         function = "gpio";
1761                                 };
1762                         };
1763
1764                         qup_uart0_default: qup-uart0-default {
1765                                 pinmux {
1766                                         pins = "gpio34", "gpio35",
1767                                                "gpio36", "gpio37";
1768                                         function = "qup00";
1769                                 };
1770                         };
1771
1772                         qup_uart1_default: qup-uart1-default {
1773                                 pinmux {
1774                                         pins = "gpio0", "gpio1",
1775                                                "gpio2", "gpio3";
1776                                         function = "qup01";
1777                                 };
1778                         };
1779
1780                         qup_uart2_default: qup-uart2-default {
1781                                 pinmux {
1782                                         pins = "gpio15", "gpio16";
1783                                         function = "qup02_uart";
1784                                 };
1785                         };
1786
1787                         qup_uart3_default: qup-uart3-default {
1788                                 pinmux {
1789                                         pins = "gpio38", "gpio39",
1790                                                "gpio40", "gpio41";
1791                                         function = "qup03";
1792                                 };
1793                         };
1794
1795                         qup_uart4_default: qup-uart4-default {
1796                                 pinmux {
1797                                         pins = "gpio115", "gpio116";
1798                                         function = "qup04_uart";
1799                                 };
1800                         };
1801
1802                         qup_uart5_default: qup-uart5-default {
1803                                 pinmux {
1804                                         pins = "gpio25", "gpio26",
1805                                                "gpio27", "gpio28";
1806                                         function = "qup05";
1807                                 };
1808                         };
1809
1810                         qup_uart6_default: qup-uart6-default {
1811                                 pinmux {
1812                                         pins = "gpio59", "gpio60",
1813                                                "gpio61", "gpio62";
1814                                         function = "qup10";
1815                                 };
1816                         };
1817
1818                         qup_uart7_default: qup-uart7-default {
1819                                 pinmux {
1820                                         pins = "gpio6", "gpio7";
1821                                         function = "qup11_uart";
1822                                 };
1823                         };
1824
1825                         qup_uart8_default: qup-uart8-default {
1826                                 pinmux {
1827                                         pins = "gpio44", "gpio45";
1828                                         function = "qup12";
1829                                 };
1830                         };
1831
1832                         qup_uart9_default: qup-uart9-default {
1833                                 pinmux {
1834                                         pins = "gpio46", "gpio47";
1835                                         function = "qup13_uart";
1836                                 };
1837                         };
1838
1839                         qup_uart10_default: qup-uart10-default {
1840                                 pinmux {
1841                                         pins = "gpio86", "gpio87",
1842                                                "gpio88", "gpio89";
1843                                         function = "qup14";
1844                                 };
1845                         };
1846
1847                         qup_uart11_default: qup-uart11-default {
1848                                 pinmux {
1849                                         pins = "gpio53", "gpio54",
1850                                                "gpio55", "gpio56";
1851                                         function = "qup15";
1852                                 };
1853                         };
1854
1855                         sec_mi2s_active: sec-mi2s-active {
1856                                 pinmux {
1857                                         pins = "gpio49", "gpio50", "gpio51";
1858                                         function = "mi2s_1";
1859                                 };
1860
1861                                 pinconf {
1862                                         pins = "gpio49", "gpio50", "gpio51";
1863                                         drive-strength = <8>;
1864                                         bias-pull-up;
1865                                 };
1866                         };
1867
1868                         pri_mi2s_active: pri-mi2s-active {
1869                                 pinmux {
1870                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1871                                         function = "mi2s_0";
1872                                 };
1873
1874                                 pinconf {
1875                                         pins = "gpio53", "gpio54", "gpio55", "gpio56";
1876                                         drive-strength = <8>;
1877                                         bias-pull-up;
1878                                 };
1879                         };
1880
1881                         pri_mi2s_mclk_active: pri-mi2s-mclk-active {
1882                                 pinmux {
1883                                         pins = "gpio57";
1884                                         function = "lpass_ext";
1885                                 };
1886
1887                                 pinconf {
1888                                         pins = "gpio57";
1889                                         drive-strength = <8>;
1890                                         bias-pull-up;
1891                                 };
1892                         };
1893
1894                         sdc1_on: sdc1-on {
1895                                 pinconf-clk {
1896                                         pins = "sdc1_clk";
1897                                         bias-disable;
1898                                         drive-strength = <16>;
1899                                 };
1900
1901                                 pinconf-cmd {
1902                                         pins = "sdc1_cmd";
1903                                         bias-pull-up;
1904                                         drive-strength = <10>;
1905                                 };
1906
1907                                 pinconf-data {
1908                                         pins = "sdc1_data";
1909                                         bias-pull-up;
1910                                         drive-strength = <10>;
1911                                 };
1912
1913                                 pinconf-rclk {
1914                                         pins = "sdc1_rclk";
1915                                         bias-pull-down;
1916                                 };
1917                         };
1918
1919                         sdc1_off: sdc1-off {
1920                                 pinconf-clk {
1921                                         pins = "sdc1_clk";
1922                                         bias-disable;
1923                                         drive-strength = <2>;
1924                                 };
1925
1926                                 pinconf-cmd {
1927                                         pins = "sdc1_cmd";
1928                                         bias-pull-up;
1929                                         drive-strength = <2>;
1930                                 };
1931
1932                                 pinconf-data {
1933                                         pins = "sdc1_data";
1934                                         bias-pull-up;
1935                                         drive-strength = <2>;
1936                                 };
1937
1938                                 pinconf-rclk {
1939                                         pins = "sdc1_rclk";
1940                                         bias-pull-down;
1941                                 };
1942                         };
1943
1944                         sdc2_on: sdc2-on {
1945                                 pinconf-clk {
1946                                         pins = "sdc2_clk";
1947                                         bias-disable;
1948                                         drive-strength = <16>;
1949                                 };
1950
1951                                 pinconf-cmd {
1952                                         pins = "sdc2_cmd";
1953                                         bias-pull-up;
1954                                         drive-strength = <10>;
1955                                 };
1956
1957                                 pinconf-data {
1958                                         pins = "sdc2_data";
1959                                         bias-pull-up;
1960                                         drive-strength = <10>;
1961                                 };
1962
1963                                 pinconf-sd-cd {
1964                                         pins = "gpio69";
1965                                         bias-pull-up;
1966                                         drive-strength = <2>;
1967                                 };
1968                         };
1969
1970                         sdc2_off: sdc2-off {
1971                                 pinconf-clk {
1972                                         pins = "sdc2_clk";
1973                                         bias-disable;
1974                                         drive-strength = <2>;
1975                                 };
1976
1977                                 pinconf-cmd {
1978                                         pins = "sdc2_cmd";
1979                                         bias-pull-up;
1980                                         drive-strength = <2>;
1981                                 };
1982
1983                                 pinconf-data {
1984                                         pins = "sdc2_data";
1985                                         bias-pull-up;
1986                                         drive-strength = <2>;
1987                                 };
1988
1989                                 pinconf-sd-cd {
1990                                         pins = "gpio69";
1991                                         bias-disable;
1992                                         drive-strength = <2>;
1993                                 };
1994                         };
1995                 };
1996
1997                 remoteproc_mpss: remoteproc@4080000 {
1998                         compatible = "qcom,sc7180-mpss-pas";
1999                         reg = <0 0x04080000 0 0x4040>, <0 0x04180000 0 0x48>;
2000                         reg-names = "qdsp6", "rmb";
2001
2002                         interrupts-extended = <&intc GIC_SPI 266 IRQ_TYPE_EDGE_RISING>,
2003                                               <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
2004                                               <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
2005                                               <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
2006                                               <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
2007                                               <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
2008                         interrupt-names = "wdog", "fatal", "ready", "handover",
2009                                           "stop-ack", "shutdown-ack";
2010
2011                         clocks = <&gcc GCC_MSS_CFG_AHB_CLK>,
2012                                  <&gcc GCC_MSS_Q6_MEMNOC_AXI_CLK>,
2013                                  <&gcc GCC_MSS_NAV_AXI_CLK>,
2014                                  <&gcc GCC_MSS_SNOC_AXI_CLK>,
2015                                  <&gcc GCC_MSS_MFAB_AXIS_CLK>,
2016                                  <&rpmhcc RPMH_CXO_CLK>;
2017                         clock-names = "iface", "bus", "nav", "snoc_axi",
2018                                       "mnoc_axi", "xo";
2019
2020                         power-domains = <&aoss_qmp AOSS_QMP_LS_MODEM>,
2021                                         <&rpmhpd SC7180_CX>,
2022                                         <&rpmhpd SC7180_MX>,
2023                                         <&rpmhpd SC7180_MSS>;
2024                         power-domain-names = "load_state", "cx", "mx", "mss";
2025
2026                         memory-region = <&mpss_mem>;
2027
2028                         qcom,smem-states = <&modem_smp2p_out 0>;
2029                         qcom,smem-state-names = "stop";
2030
2031                         resets = <&aoss_reset AOSS_CC_MSS_RESTART>,
2032                                  <&pdc_reset PDC_MODEM_SYNC_RESET>;
2033                         reset-names = "mss_restart", "pdc_reset";
2034
2035                         qcom,halt-regs = <&tcsr_mutex_regs 0x23000 0x25000 0x24000>;
2036                         qcom,spare-regs = <&tcsr_regs 0xb3e4>;
2037
2038                         status = "disabled";
2039
2040                         glink-edge {
2041                                 interrupts = <GIC_SPI 449 IRQ_TYPE_EDGE_RISING>;
2042                                 label = "modem";
2043                                 qcom,remote-pid = <1>;
2044                                 mboxes = <&apss_shared 12>;
2045                         };
2046                 };
2047
2048                 gpu: gpu@5000000 {
2049                         compatible = "qcom,adreno-618.0", "qcom,adreno";
2050                         #stream-id-cells = <16>;
2051                         reg = <0 0x05000000 0 0x40000>, <0 0x0509e000 0 0x1000>,
2052                                 <0 0x05061000 0 0x800>;
2053                         reg-names = "kgsl_3d0_reg_memory", "cx_mem", "cx_dbgc";
2054                         interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>;
2055                         iommus = <&adreno_smmu 0>;
2056                         operating-points-v2 = <&gpu_opp_table>;
2057                         qcom,gmu = <&gmu>;
2058
2059                         #cooling-cells = <2>;
2060
2061                         interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
2062                         interconnect-names = "gfx-mem";
2063
2064                         gpu_opp_table: opp-table {
2065                                 compatible = "operating-points-v2";
2066
2067                                 opp-800000000 {
2068                                         opp-hz = /bits/ 64 <800000000>;
2069                                         opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
2070                                         opp-peak-kBps = <8532000>;
2071                                 };
2072
2073                                 opp-650000000 {
2074                                         opp-hz = /bits/ 64 <650000000>;
2075                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
2076                                         opp-peak-kBps = <7216000>;
2077                                 };
2078
2079                                 opp-565000000 {
2080                                         opp-hz = /bits/ 64 <565000000>;
2081                                         opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
2082                                         opp-peak-kBps = <5412000>;
2083                                 };
2084
2085                                 opp-430000000 {
2086                                         opp-hz = /bits/ 64 <430000000>;
2087                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
2088                                         opp-peak-kBps = <5412000>;
2089                                 };
2090
2091                                 opp-355000000 {
2092                                         opp-hz = /bits/ 64 <355000000>;
2093                                         opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
2094                                         opp-peak-kBps = <3072000>;
2095                                 };
2096
2097                                 opp-267000000 {
2098                                         opp-hz = /bits/ 64 <267000000>;
2099                                         opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
2100                                         opp-peak-kBps = <3072000>;
2101                                 };
2102
2103                                 opp-180000000 {
2104                                         opp-hz = /bits/ 64 <180000000>;
2105                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2106                                         opp-peak-kBps = <1804000>;
2107                                 };
2108                         };
2109                 };
2110
2111                 adreno_smmu: iommu@5040000 {
2112                         compatible = "qcom,sc7180-smmu-v2", "qcom,adreno-smmu", "qcom,smmu-v2";
2113                         reg = <0 0x05040000 0 0x10000>;
2114                         #iommu-cells = <1>;
2115                         #global-interrupts = <2>;
2116                         interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
2117                                         <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
2118                                         <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
2119                                         <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
2120                                         <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
2121                                         <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
2122                                         <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
2123                                         <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
2124                                         <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
2125                                         <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
2126
2127                         clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
2128                                 <&gcc GCC_GPU_CFG_AHB_CLK>;
2129                         clock-names = "bus", "iface";
2130
2131                         power-domains = <&gpucc CX_GDSC>;
2132                 };
2133
2134                 gmu: gmu@506a000 {
2135                         compatible="qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2136                         reg = <0 0x0506a000 0 0x31000>, <0 0x0b290000 0 0x10000>,
2137                                 <0 0x0b490000 0 0x10000>;
2138                         reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2139                         interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
2140                                    <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
2141                         interrupt-names = "hfi", "gmu";
2142                         clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
2143                                <&gpucc GPU_CC_CXO_CLK>,
2144                                <&gcc GCC_DDRSS_GPU_AXI_CLK>,
2145                                <&gcc GCC_GPU_MEMNOC_GFX_CLK>;
2146                         clock-names = "gmu", "cxo", "axi", "memnoc";
2147                         power-domains = <&gpucc CX_GDSC>, <&gpucc GX_GDSC>;
2148                         power-domain-names = "cx", "gx";
2149                         iommus = <&adreno_smmu 5>;
2150                         operating-points-v2 = <&gmu_opp_table>;
2151
2152                         gmu_opp_table: opp-table {
2153                                 compatible = "operating-points-v2";
2154
2155                                 opp-200000000 {
2156                                         opp-hz = /bits/ 64 <200000000>;
2157                                         opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
2158                                 };
2159                         };
2160                 };
2161
2162                 gpucc: clock-controller@5090000 {
2163                         compatible = "qcom,sc7180-gpucc";
2164                         reg = <0 0x05090000 0 0x9000>;
2165                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2166                                  <&gcc GCC_GPU_GPLL0_CLK_SRC>,
2167                                  <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
2168                         clock-names = "bi_tcxo",
2169                                       "gcc_gpu_gpll0_clk_src",
2170                                       "gcc_gpu_gpll0_div_clk_src";
2171                         #clock-cells = <1>;
2172                         #reset-cells = <1>;
2173                         #power-domain-cells = <1>;
2174                 };
2175
2176                 stm@6002000 {
2177                         compatible = "arm,coresight-stm", "arm,primecell";
2178                         reg = <0 0x06002000 0 0x1000>,
2179                               <0 0x16280000 0 0x180000>;
2180                         reg-names = "stm-base", "stm-stimulus-base";
2181
2182                         clocks = <&aoss_qmp>;
2183                         clock-names = "apb_pclk";
2184
2185                         out-ports {
2186                                 port {
2187                                         stm_out: endpoint {
2188                                                 remote-endpoint = <&funnel0_in7>;
2189                                         };
2190                                 };
2191                         };
2192                 };
2193
2194                 funnel@6041000 {
2195                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2196                         reg = <0 0x06041000 0 0x1000>;
2197
2198                         clocks = <&aoss_qmp>;
2199                         clock-names = "apb_pclk";
2200
2201                         out-ports {
2202                                 port {
2203                                         funnel0_out: endpoint {
2204                                                 remote-endpoint = <&merge_funnel_in0>;
2205                                         };
2206                                 };
2207                         };
2208
2209                         in-ports {
2210                                 #address-cells = <1>;
2211                                 #size-cells = <0>;
2212
2213                                 port@7 {
2214                                         reg = <7>;
2215                                         funnel0_in7: endpoint {
2216                                                 remote-endpoint = <&stm_out>;
2217                                         };
2218                                 };
2219                         };
2220                 };
2221
2222                 funnel@6042000 {
2223                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2224                         reg = <0 0x06042000 0 0x1000>;
2225
2226                         clocks = <&aoss_qmp>;
2227                         clock-names = "apb_pclk";
2228
2229                         out-ports {
2230                                 port {
2231                                         funnel1_out: endpoint {
2232                                                 remote-endpoint = <&merge_funnel_in1>;
2233                                         };
2234                                 };
2235                         };
2236
2237                         in-ports {
2238                                 #address-cells = <1>;
2239                                 #size-cells = <0>;
2240
2241                                 port@4 {
2242                                         reg = <4>;
2243                                         funnel1_in4: endpoint {
2244                                                 remote-endpoint = <&apss_merge_funnel_out>;
2245                                         };
2246                                 };
2247                         };
2248                 };
2249
2250                 funnel@6045000 {
2251                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2252                         reg = <0 0x06045000 0 0x1000>;
2253
2254                         clocks = <&aoss_qmp>;
2255                         clock-names = "apb_pclk";
2256
2257                         out-ports {
2258                                 port {
2259                                         merge_funnel_out: endpoint {
2260                                                 remote-endpoint = <&swao_funnel_in>;
2261                                         };
2262                                 };
2263                         };
2264
2265                         in-ports {
2266                                 #address-cells = <1>;
2267                                 #size-cells = <0>;
2268
2269                                 port@0 {
2270                                         reg = <0>;
2271                                         merge_funnel_in0: endpoint {
2272                                                 remote-endpoint = <&funnel0_out>;
2273                                         };
2274                                 };
2275
2276                                 port@1 {
2277                                         reg = <1>;
2278                                         merge_funnel_in1: endpoint {
2279                                                 remote-endpoint = <&funnel1_out>;
2280                                         };
2281                                 };
2282                         };
2283                 };
2284
2285                 replicator@6046000 {
2286                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2287                         reg = <0 0x06046000 0 0x1000>;
2288
2289                         clocks = <&aoss_qmp>;
2290                         clock-names = "apb_pclk";
2291
2292                         out-ports {
2293                                 port {
2294                                         replicator_out: endpoint {
2295                                                 remote-endpoint = <&etr_in>;
2296                                         };
2297                                 };
2298                         };
2299
2300                         in-ports {
2301                                 port {
2302                                         replicator_in: endpoint {
2303                                                 remote-endpoint = <&swao_replicator_out>;
2304                                         };
2305                                 };
2306                         };
2307                 };
2308
2309                 etr@6048000 {
2310                         compatible = "arm,coresight-tmc", "arm,primecell";
2311                         reg = <0 0x06048000 0 0x1000>;
2312                         iommus = <&apps_smmu 0x04a0 0x20>;
2313
2314                         clocks = <&aoss_qmp>;
2315                         clock-names = "apb_pclk";
2316                         arm,scatter-gather;
2317
2318                         in-ports {
2319                                 port {
2320                                         etr_in: endpoint {
2321                                                 remote-endpoint = <&replicator_out>;
2322                                         };
2323                                 };
2324                         };
2325                 };
2326
2327                 funnel@6b04000 {
2328                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2329                         reg = <0 0x06b04000 0 0x1000>;
2330
2331                         clocks = <&aoss_qmp>;
2332                         clock-names = "apb_pclk";
2333
2334                         out-ports {
2335                                 port {
2336                                         swao_funnel_out: endpoint {
2337                                                 remote-endpoint = <&etf_in>;
2338                                         };
2339                                 };
2340                         };
2341
2342                         in-ports {
2343                                 #address-cells = <1>;
2344                                 #size-cells = <0>;
2345
2346                                 port@7 {
2347                                         reg = <7>;
2348                                         swao_funnel_in: endpoint {
2349                                                 remote-endpoint = <&merge_funnel_out>;
2350                                         };
2351                                 };
2352                         };
2353                 };
2354
2355                 etf@6b05000 {
2356                         compatible = "arm,coresight-tmc", "arm,primecell";
2357                         reg = <0 0x06b05000 0 0x1000>;
2358
2359                         clocks = <&aoss_qmp>;
2360                         clock-names = "apb_pclk";
2361
2362                         out-ports {
2363                                 port {
2364                                         etf_out: endpoint {
2365                                                 remote-endpoint = <&swao_replicator_in>;
2366                                         };
2367                                 };
2368                         };
2369
2370                         in-ports {
2371                                 port {
2372                                         etf_in: endpoint {
2373                                                 remote-endpoint = <&swao_funnel_out>;
2374                                         };
2375                                 };
2376                         };
2377                 };
2378
2379                 replicator@6b06000 {
2380                         compatible = "arm,coresight-dynamic-replicator", "arm,primecell";
2381                         reg = <0 0x06b06000 0 0x1000>;
2382
2383                         clocks = <&aoss_qmp>;
2384                         clock-names = "apb_pclk";
2385                         qcom,replicator-loses-context;
2386
2387                         out-ports {
2388                                 port {
2389                                         swao_replicator_out: endpoint {
2390                                                 remote-endpoint = <&replicator_in>;
2391                                         };
2392                                 };
2393                         };
2394
2395                         in-ports {
2396                                 port {
2397                                         swao_replicator_in: endpoint {
2398                                                 remote-endpoint = <&etf_out>;
2399                                         };
2400                                 };
2401                         };
2402                 };
2403
2404                 etm@7040000 {
2405                         compatible = "arm,coresight-etm4x", "arm,primecell";
2406                         reg = <0 0x07040000 0 0x1000>;
2407
2408                         cpu = <&CPU0>;
2409
2410                         clocks = <&aoss_qmp>;
2411                         clock-names = "apb_pclk";
2412                         arm,coresight-loses-context-with-cpu;
2413                         qcom,skip-power-up;
2414
2415                         out-ports {
2416                                 port {
2417                                         etm0_out: endpoint {
2418                                                 remote-endpoint = <&apss_funnel_in0>;
2419                                         };
2420                                 };
2421                         };
2422                 };
2423
2424                 etm@7140000 {
2425                         compatible = "arm,coresight-etm4x", "arm,primecell";
2426                         reg = <0 0x07140000 0 0x1000>;
2427
2428                         cpu = <&CPU1>;
2429
2430                         clocks = <&aoss_qmp>;
2431                         clock-names = "apb_pclk";
2432                         arm,coresight-loses-context-with-cpu;
2433                         qcom,skip-power-up;
2434
2435                         out-ports {
2436                                 port {
2437                                         etm1_out: endpoint {
2438                                                 remote-endpoint = <&apss_funnel_in1>;
2439                                         };
2440                                 };
2441                         };
2442                 };
2443
2444                 etm@7240000 {
2445                         compatible = "arm,coresight-etm4x", "arm,primecell";
2446                         reg = <0 0x07240000 0 0x1000>;
2447
2448                         cpu = <&CPU2>;
2449
2450                         clocks = <&aoss_qmp>;
2451                         clock-names = "apb_pclk";
2452                         arm,coresight-loses-context-with-cpu;
2453                         qcom,skip-power-up;
2454
2455                         out-ports {
2456                                 port {
2457                                         etm2_out: endpoint {
2458                                                 remote-endpoint = <&apss_funnel_in2>;
2459                                         };
2460                                 };
2461                         };
2462                 };
2463
2464                 etm@7340000 {
2465                         compatible = "arm,coresight-etm4x", "arm,primecell";
2466                         reg = <0 0x07340000 0 0x1000>;
2467
2468                         cpu = <&CPU3>;
2469
2470                         clocks = <&aoss_qmp>;
2471                         clock-names = "apb_pclk";
2472                         arm,coresight-loses-context-with-cpu;
2473                         qcom,skip-power-up;
2474
2475                         out-ports {
2476                                 port {
2477                                         etm3_out: endpoint {
2478                                                 remote-endpoint = <&apss_funnel_in3>;
2479                                         };
2480                                 };
2481                         };
2482                 };
2483
2484                 etm@7440000 {
2485                         compatible = "arm,coresight-etm4x", "arm,primecell";
2486                         reg = <0 0x07440000 0 0x1000>;
2487
2488                         cpu = <&CPU4>;
2489
2490                         clocks = <&aoss_qmp>;
2491                         clock-names = "apb_pclk";
2492                         arm,coresight-loses-context-with-cpu;
2493                         qcom,skip-power-up;
2494
2495                         out-ports {
2496                                 port {
2497                                         etm4_out: endpoint {
2498                                                 remote-endpoint = <&apss_funnel_in4>;
2499                                         };
2500                                 };
2501                         };
2502                 };
2503
2504                 etm@7540000 {
2505                         compatible = "arm,coresight-etm4x", "arm,primecell";
2506                         reg = <0 0x07540000 0 0x1000>;
2507
2508                         cpu = <&CPU5>;
2509
2510                         clocks = <&aoss_qmp>;
2511                         clock-names = "apb_pclk";
2512                         arm,coresight-loses-context-with-cpu;
2513                         qcom,skip-power-up;
2514
2515                         out-ports {
2516                                 port {
2517                                         etm5_out: endpoint {
2518                                                 remote-endpoint = <&apss_funnel_in5>;
2519                                         };
2520                                 };
2521                         };
2522                 };
2523
2524                 etm@7640000 {
2525                         compatible = "arm,coresight-etm4x", "arm,primecell";
2526                         reg = <0 0x07640000 0 0x1000>;
2527
2528                         cpu = <&CPU6>;
2529
2530                         clocks = <&aoss_qmp>;
2531                         clock-names = "apb_pclk";
2532                         arm,coresight-loses-context-with-cpu;
2533                         qcom,skip-power-up;
2534
2535                         out-ports {
2536                                 port {
2537                                         etm6_out: endpoint {
2538                                                 remote-endpoint = <&apss_funnel_in6>;
2539                                         };
2540                                 };
2541                         };
2542                 };
2543
2544                 etm@7740000 {
2545                         compatible = "arm,coresight-etm4x", "arm,primecell";
2546                         reg = <0 0x07740000 0 0x1000>;
2547
2548                         cpu = <&CPU7>;
2549
2550                         clocks = <&aoss_qmp>;
2551                         clock-names = "apb_pclk";
2552                         arm,coresight-loses-context-with-cpu;
2553                         qcom,skip-power-up;
2554
2555                         out-ports {
2556                                 port {
2557                                         etm7_out: endpoint {
2558                                                 remote-endpoint = <&apss_funnel_in7>;
2559                                         };
2560                                 };
2561                         };
2562                 };
2563
2564                 funnel@7800000 { /* APSS Funnel */
2565                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2566                         reg = <0 0x07800000 0 0x1000>;
2567
2568                         clocks = <&aoss_qmp>;
2569                         clock-names = "apb_pclk";
2570
2571                         out-ports {
2572                                 port {
2573                                         apss_funnel_out: endpoint {
2574                                                 remote-endpoint = <&apss_merge_funnel_in>;
2575                                         };
2576                                 };
2577                         };
2578
2579                         in-ports {
2580                                 #address-cells = <1>;
2581                                 #size-cells = <0>;
2582
2583                                 port@0 {
2584                                         reg = <0>;
2585                                         apss_funnel_in0: endpoint {
2586                                                 remote-endpoint = <&etm0_out>;
2587                                         };
2588                                 };
2589
2590                                 port@1 {
2591                                         reg = <1>;
2592                                         apss_funnel_in1: endpoint {
2593                                                 remote-endpoint = <&etm1_out>;
2594                                         };
2595                                 };
2596
2597                                 port@2 {
2598                                         reg = <2>;
2599                                         apss_funnel_in2: endpoint {
2600                                                 remote-endpoint = <&etm2_out>;
2601                                         };
2602                                 };
2603
2604                                 port@3 {
2605                                         reg = <3>;
2606                                         apss_funnel_in3: endpoint {
2607                                                 remote-endpoint = <&etm3_out>;
2608                                         };
2609                                 };
2610
2611                                 port@4 {
2612                                         reg = <4>;
2613                                         apss_funnel_in4: endpoint {
2614                                                 remote-endpoint = <&etm4_out>;
2615                                         };
2616                                 };
2617
2618                                 port@5 {
2619                                         reg = <5>;
2620                                         apss_funnel_in5: endpoint {
2621                                                 remote-endpoint = <&etm5_out>;
2622                                         };
2623                                 };
2624
2625                                 port@6 {
2626                                         reg = <6>;
2627                                         apss_funnel_in6: endpoint {
2628                                                 remote-endpoint = <&etm6_out>;
2629                                         };
2630                                 };
2631
2632                                 port@7 {
2633                                         reg = <7>;
2634                                         apss_funnel_in7: endpoint {
2635                                                 remote-endpoint = <&etm7_out>;
2636                                         };
2637                                 };
2638                         };
2639                 };
2640
2641                 funnel@7810000 {
2642                         compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
2643                         reg = <0 0x07810000 0 0x1000>;
2644
2645                         clocks = <&aoss_qmp>;
2646                         clock-names = "apb_pclk";
2647
2648                         out-ports {
2649                                 port {
2650                                         apss_merge_funnel_out: endpoint {
2651                                                 remote-endpoint = <&funnel1_in4>;
2652                                         };
2653                                 };
2654                         };
2655
2656                         in-ports {
2657                                 port {
2658                                         apss_merge_funnel_in: endpoint {
2659                                                 remote-endpoint = <&apss_funnel_out>;
2660                                         };
2661                                 };
2662                         };
2663                 };
2664
2665                 sdhc_2: sdhci@8804000 {
2666                         compatible = "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
2667                         reg = <0 0x08804000 0 0x1000>;
2668
2669                         iommus = <&apps_smmu 0x80 0>;
2670                         interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
2671                                         <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
2672                         interrupt-names = "hc_irq", "pwr_irq";
2673
2674                         clocks = <&gcc GCC_SDCC2_APPS_CLK>,
2675                                         <&gcc GCC_SDCC2_AHB_CLK>;
2676                         clock-names = "core", "iface";
2677
2678                         interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>,
2679                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_SDCC_2 0>;
2680                         interconnect-names = "sdhc-ddr","cpu-sdhc";
2681                         power-domains = <&rpmhpd SC7180_CX>;
2682                         operating-points-v2 = <&sdhc2_opp_table>;
2683
2684                         bus-width = <4>;
2685
2686                         status = "disabled";
2687
2688                         sdhc2_opp_table: sdhc2-opp-table {
2689                                 compatible = "operating-points-v2";
2690
2691                                 opp-100000000 {
2692                                         opp-hz = /bits/ 64 <100000000>;
2693                                         required-opps = <&rpmhpd_opp_low_svs>;
2694                                         opp-peak-kBps = <160000 100000>;
2695                                         opp-avg-kBps = <80000 50000>;
2696                                 };
2697
2698                                 opp-202000000 {
2699                                         opp-hz = /bits/ 64 <202000000>;
2700                                         required-opps = <&rpmhpd_opp_svs_l1>;
2701                                         opp-peak-kBps = <200000 120000>;
2702                                         opp-avg-kBps = <100000 60000>;
2703                                 };
2704                         };
2705                 };
2706
2707                 qspi_opp_table: qspi-opp-table {
2708                         compatible = "operating-points-v2";
2709
2710                         opp-75000000 {
2711                                 opp-hz = /bits/ 64 <75000000>;
2712                                 required-opps = <&rpmhpd_opp_low_svs>;
2713                         };
2714
2715                         opp-150000000 {
2716                                 opp-hz = /bits/ 64 <150000000>;
2717                                 required-opps = <&rpmhpd_opp_svs>;
2718                         };
2719
2720                         opp-300000000 {
2721                                 opp-hz = /bits/ 64 <300000000>;
2722                                 required-opps = <&rpmhpd_opp_nom>;
2723                         };
2724                 };
2725
2726                 qspi: spi@88dc000 {
2727                         compatible = "qcom,qspi-v1";
2728                         reg = <0 0x088dc000 0 0x600>;
2729                         #address-cells = <1>;
2730                         #size-cells = <0>;
2731                         interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
2732                         clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>,
2733                                  <&gcc GCC_QSPI_CORE_CLK>;
2734                         clock-names = "iface", "core";
2735                         interconnects = <&gem_noc MASTER_APPSS_PROC 0
2736                                         &config_noc SLAVE_QSPI_0 0>;
2737                         interconnect-names = "qspi-config";
2738                         power-domains = <&rpmhpd SC7180_CX>;
2739                         operating-points-v2 = <&qspi_opp_table>;
2740                         status = "disabled";
2741                 };
2742
2743                 usb_1_hsphy: phy@88e3000 {
2744                         compatible = "qcom,sc7180-qusb2-phy", "qcom,qusb2-v2-phy";
2745                         reg = <0 0x088e3000 0 0x400>;
2746                         status = "disabled";
2747                         #phy-cells = <0>;
2748                         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2749                                  <&rpmhcc RPMH_CXO_CLK>;
2750                         clock-names = "cfg_ahb", "ref";
2751                         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
2752
2753                         nvmem-cells = <&qusb2p_hstx_trim>;
2754                 };
2755
2756                 usb_1_qmpphy: phy-wrapper@88e9000 {
2757                         compatible = "qcom,sc7180-qmp-usb3-phy";
2758                         reg = <0 0x088e9000 0 0x18c>,
2759                               <0 0x088e8000 0 0x38>;
2760                         reg-names = "reg-base", "dp_com";
2761                         status = "disabled";
2762                         #clock-cells = <1>;
2763                         #address-cells = <2>;
2764                         #size-cells = <2>;
2765                         ranges;
2766
2767                         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
2768                                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
2769                                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
2770                                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
2771                         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
2772
2773                         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
2774                                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
2775                         reset-names = "phy", "common";
2776
2777                         usb_1_ssphy: phy@88e9200 {
2778                                 reg = <0 0x088e9200 0 0x128>,
2779                                       <0 0x088e9400 0 0x200>,
2780                                       <0 0x088e9c00 0 0x218>,
2781                                       <0 0x088e9600 0 0x128>,
2782                                       <0 0x088e9800 0 0x200>,
2783                                       <0 0x088e9a00 0 0x18>;
2784                                 #clock-cells = <0>;
2785                                 #phy-cells = <0>;
2786                                 clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
2787                                 clock-names = "pipe0";
2788                                 clock-output-names = "usb3_phy_pipe_clk_src";
2789                         };
2790                 };
2791
2792                 dc_noc: interconnect@9160000 {
2793                         compatible = "qcom,sc7180-dc-noc";
2794                         reg = <0 0x09160000 0 0x03200>;
2795                         #interconnect-cells = <2>;
2796                         qcom,bcm-voters = <&apps_bcm_voter>;
2797                 };
2798
2799                 system-cache-controller@9200000 {
2800                         compatible = "qcom,sc7180-llcc";
2801                         reg = <0 0x09200000 0 0x50000>, <0 0x09600000 0 0x50000>;
2802                         reg-names = "llcc_base", "llcc_broadcast_base";
2803                         interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>;
2804                 };
2805
2806                 gem_noc: interconnect@9680000 {
2807                         compatible = "qcom,sc7180-gem-noc";
2808                         reg = <0 0x09680000 0 0x3e200>;
2809                         #interconnect-cells = <2>;
2810                         qcom,bcm-voters = <&apps_bcm_voter>;
2811                 };
2812
2813                 npu_noc: interconnect@9990000 {
2814                         compatible = "qcom,sc7180-npu-noc";
2815                         reg = <0 0x09990000 0 0x1600>;
2816                         #interconnect-cells = <2>;
2817                         qcom,bcm-voters = <&apps_bcm_voter>;
2818                 };
2819
2820                 usb_1: usb@a6f8800 {
2821                         compatible = "qcom,sc7180-dwc3", "qcom,dwc3";
2822                         reg = <0 0x0a6f8800 0 0x400>;
2823                         status = "disabled";
2824                         #address-cells = <2>;
2825                         #size-cells = <2>;
2826                         ranges;
2827                         dma-ranges;
2828
2829                         clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
2830                                  <&gcc GCC_USB30_PRIM_MASTER_CLK>,
2831                                  <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
2832                                  <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2833                                  <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
2834                         clock-names = "cfg_noc", "core", "iface", "mock_utmi",
2835                                       "sleep";
2836
2837                         assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
2838                                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
2839                         assigned-clock-rates = <19200000>, <150000000>;
2840
2841                         interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
2842                                      <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
2843                                      <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
2844                                      <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
2845                         interrupt-names = "hs_phy_irq", "ss_phy_irq",
2846                                           "dm_hs_phy_irq", "dp_hs_phy_irq";
2847
2848                         power-domains = <&gcc USB30_PRIM_GDSC>;
2849
2850                         resets = <&gcc GCC_USB30_PRIM_BCR>;
2851
2852                         interconnects = <&aggre2_noc MASTER_USB3 0 &mc_virt SLAVE_EBI1 0>,
2853                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3 0>;
2854                         interconnect-names = "usb-ddr", "apps-usb";
2855
2856                         usb_1_dwc3: dwc3@a600000 {
2857                                 compatible = "snps,dwc3";
2858                                 reg = <0 0x0a600000 0 0xe000>;
2859                                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
2860                                 iommus = <&apps_smmu 0x540 0>;
2861                                 snps,dis_u2_susphy_quirk;
2862                                 snps,dis_enblslpm_quirk;
2863                                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
2864                                 phy-names = "usb2-phy", "usb3-phy";
2865                                 maximum-speed = "super-speed";
2866                         };
2867                 };
2868
2869                 venus: video-codec@aa00000 {
2870                         compatible = "qcom,sc7180-venus";
2871                         reg = <0 0x0aa00000 0 0xff000>;
2872                         interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
2873                         power-domains = <&videocc VENUS_GDSC>,
2874                                         <&videocc VCODEC0_GDSC>,
2875                                         <&rpmhpd SC7180_CX>;
2876                         power-domain-names = "venus", "vcodec0", "cx";
2877                         operating-points-v2 = <&venus_opp_table>;
2878                         clocks = <&videocc VIDEO_CC_VENUS_CTL_CORE_CLK>,
2879                                  <&videocc VIDEO_CC_VENUS_AHB_CLK>,
2880                                  <&videocc VIDEO_CC_VENUS_CTL_AXI_CLK>,
2881                                  <&videocc VIDEO_CC_VCODEC0_CORE_CLK>,
2882                                  <&videocc VIDEO_CC_VCODEC0_AXI_CLK>;
2883                         clock-names = "core", "iface", "bus",
2884                                       "vcodec0_core", "vcodec0_bus";
2885                         iommus = <&apps_smmu 0x0c00 0x60>;
2886                         memory-region = <&venus_mem>;
2887                         interconnects = <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>,
2888                                         <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_VENUS_CFG 0>;
2889                         interconnect-names = "video-mem", "cpu-cfg";
2890
2891                         video-decoder {
2892                                 compatible = "venus-decoder";
2893                         };
2894
2895                         video-encoder {
2896                                 compatible = "venus-encoder";
2897                         };
2898
2899                         venus_opp_table: venus-opp-table {
2900                                 compatible = "operating-points-v2";
2901
2902                                 opp-150000000 {
2903                                         opp-hz = /bits/ 64 <150000000>;
2904                                         required-opps = <&rpmhpd_opp_low_svs>;
2905                                 };
2906
2907                                 opp-270000000 {
2908                                         opp-hz = /bits/ 64 <270000000>;
2909                                         required-opps = <&rpmhpd_opp_svs>;
2910                                 };
2911
2912                                 opp-340000000 {
2913                                         opp-hz = /bits/ 64 <340000000>;
2914                                         required-opps = <&rpmhpd_opp_svs_l1>;
2915                                 };
2916
2917                                 opp-434000000 {
2918                                         opp-hz = /bits/ 64 <434000000>;
2919                                         required-opps = <&rpmhpd_opp_nom>;
2920                                 };
2921
2922                                 opp-500000097 {
2923                                         opp-hz = /bits/ 64 <500000097>;
2924                                         required-opps = <&rpmhpd_opp_turbo>;
2925                                 };
2926                         };
2927                 };
2928
2929                 videocc: clock-controller@ab00000 {
2930                         compatible = "qcom,sc7180-videocc";
2931                         reg = <0 0x0ab00000 0 0x10000>;
2932                         clocks = <&rpmhcc RPMH_CXO_CLK>;
2933                         clock-names = "bi_tcxo";
2934                         #clock-cells = <1>;
2935                         #reset-cells = <1>;
2936                         #power-domain-cells = <1>;
2937                 };
2938
2939                 camnoc_virt: interconnect@ac00000 {
2940                         compatible = "qcom,sc7180-camnoc-virt";
2941                         reg = <0 0x0ac00000 0 0x1000>;
2942                         #interconnect-cells = <2>;
2943                         qcom,bcm-voters = <&apps_bcm_voter>;
2944                 };
2945
2946                 camcc: clock-controller@ad00000 {
2947                         compatible = "qcom,sc7180-camcc";
2948                         reg = <0 0x0ad00000 0 0x10000>;
2949                         clocks = <&rpmhcc RPMH_CXO_CLK>,
2950                                <&gcc GCC_CAMERA_AHB_CLK>,
2951                                <&gcc GCC_CAMERA_XO_CLK>;
2952                         clock-names = "bi_tcxo", "iface", "xo";
2953                         #clock-cells = <1>;
2954                         #reset-cells = <1>;
2955                         #power-domain-cells = <1>;
2956                 };
2957
2958                 mdss: mdss@ae00000 {
2959                         compatible = "qcom,sc7180-mdss";
2960                         reg = <0 0x0ae00000 0 0x1000>;
2961                         reg-names = "mdss";
2962
2963                         power-domains = <&dispcc MDSS_GDSC>;
2964
2965                         clocks = <&gcc GCC_DISP_AHB_CLK>,
2966                                  <&dispcc DISP_CC_MDSS_AHB_CLK>,
2967                                  <&dispcc DISP_CC_MDSS_MDP_CLK>;
2968                         clock-names = "iface", "ahb", "core";
2969
2970                         assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>;
2971                         assigned-clock-rates = <300000000>;
2972
2973                         interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
2974                         interrupt-controller;
2975                         #interrupt-cells = <1>;
2976
2977                         interconnects = <&mmss_noc MASTER_MDP0 0 &mc_virt SLAVE_EBI1 0>;
2978                         interconnect-names = "mdp0-mem";
2979
2980                         iommus = <&apps_smmu 0x800 0x2>;
2981
2982                         #address-cells = <2>;
2983                         #size-cells = <2>;
2984                         ranges;
2985
2986                         status = "disabled";
2987
2988                         mdp: mdp@ae01000 {
2989                                 compatible = "qcom,sc7180-dpu";
2990                                 reg = <0 0x0ae01000 0 0x8f000>,
2991                                       <0 0x0aeb0000 0 0x2008>;
2992                                 reg-names = "mdp", "vbif";
2993
2994                                 clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
2995                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
2996                                          <&dispcc DISP_CC_MDSS_ROT_CLK>,
2997                                          <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
2998                                          <&dispcc DISP_CC_MDSS_MDP_CLK>,
2999                                          <&dispcc DISP_CC_MDSS_VSYNC_CLK>;
3000                                 clock-names = "bus", "iface", "rot", "lut", "core",
3001                                               "vsync";
3002                                 assigned-clocks = <&dispcc DISP_CC_MDSS_MDP_CLK>,
3003                                                   <&dispcc DISP_CC_MDSS_VSYNC_CLK>,
3004                                                   <&dispcc DISP_CC_MDSS_ROT_CLK>,
3005                                                   <&dispcc DISP_CC_MDSS_AHB_CLK>;
3006                                 assigned-clock-rates = <300000000>,
3007                                                        <19200000>,
3008                                                        <19200000>,
3009                                                        <19200000>;
3010                                 operating-points-v2 = <&mdp_opp_table>;
3011                                 power-domains = <&rpmhpd SC7180_CX>;
3012
3013                                 interrupt-parent = <&mdss>;
3014                                 interrupts = <0>;
3015
3016                                 status = "disabled";
3017
3018                                 ports {
3019                                         #address-cells = <1>;
3020                                         #size-cells = <0>;
3021
3022                                         port@0 {
3023                                                 reg = <0>;
3024                                                 dpu_intf1_out: endpoint {
3025                                                         remote-endpoint = <&dsi0_in>;
3026                                                 };
3027                                         };
3028                                 };
3029
3030                                 mdp_opp_table: mdp-opp-table {
3031                                         compatible = "operating-points-v2";
3032
3033                                         opp-200000000 {
3034                                                 opp-hz = /bits/ 64 <200000000>;
3035                                                 required-opps = <&rpmhpd_opp_low_svs>;
3036                                         };
3037
3038                                         opp-300000000 {
3039                                                 opp-hz = /bits/ 64 <300000000>;
3040                                                 required-opps = <&rpmhpd_opp_svs>;
3041                                         };
3042
3043                                         opp-345000000 {
3044                                                 opp-hz = /bits/ 64 <345000000>;
3045                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3046                                         };
3047
3048                                         opp-460000000 {
3049                                                 opp-hz = /bits/ 64 <460000000>;
3050                                                 required-opps = <&rpmhpd_opp_nom>;
3051                                         };
3052                                 };
3053
3054                         };
3055
3056                         dsi0: dsi@ae94000 {
3057                                 compatible = "qcom,mdss-dsi-ctrl";
3058                                 reg = <0 0x0ae94000 0 0x400>;
3059                                 reg-names = "dsi_ctrl";
3060
3061                                 interrupt-parent = <&mdss>;
3062                                 interrupts = <4>;
3063
3064                                 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
3065                                          <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
3066                                          <&dispcc DISP_CC_MDSS_PCLK0_CLK>,
3067                                          <&dispcc DISP_CC_MDSS_ESC0_CLK>,
3068                                          <&dispcc DISP_CC_MDSS_AHB_CLK>,
3069                                          <&gcc GCC_DISP_HF_AXI_CLK>;
3070                                 clock-names = "byte",
3071                                               "byte_intf",
3072                                               "pixel",
3073                                               "core",
3074                                               "iface",
3075                                               "bus";
3076
3077                                 operating-points-v2 = <&dsi_opp_table>;
3078                                 power-domains = <&rpmhpd SC7180_CX>;
3079
3080                                 phys = <&dsi_phy>;
3081                                 phy-names = "dsi";
3082
3083                                 #address-cells = <1>;
3084                                 #size-cells = <0>;
3085
3086                                 status = "disabled";
3087
3088                                 ports {
3089                                         #address-cells = <1>;
3090                                         #size-cells = <0>;
3091
3092                                         port@0 {
3093                                                 reg = <0>;
3094                                                 dsi0_in: endpoint {
3095                                                         remote-endpoint = <&dpu_intf1_out>;
3096                                                 };
3097                                         };
3098
3099                                         port@1 {
3100                                                 reg = <1>;
3101                                                 dsi0_out: endpoint {
3102                                                 };
3103                                         };
3104                                 };
3105
3106                                 dsi_opp_table: dsi-opp-table {
3107                                         compatible = "operating-points-v2";
3108
3109                                         opp-187500000 {
3110                                                 opp-hz = /bits/ 64 <187500000>;
3111                                                 required-opps = <&rpmhpd_opp_low_svs>;
3112                                         };
3113
3114                                         opp-300000000 {
3115                                                 opp-hz = /bits/ 64 <300000000>;
3116                                                 required-opps = <&rpmhpd_opp_svs>;
3117                                         };
3118
3119                                         opp-358000000 {
3120                                                 opp-hz = /bits/ 64 <358000000>;
3121                                                 required-opps = <&rpmhpd_opp_svs_l1>;
3122                                         };
3123                                 };
3124                         };
3125
3126                         dsi_phy: dsi-phy@ae94400 {
3127                                 compatible = "qcom,dsi-phy-10nm";
3128                                 reg = <0 0x0ae94400 0 0x200>,
3129                                       <0 0x0ae94600 0 0x280>,
3130                                       <0 0x0ae94a00 0 0x1e0>;
3131                                 reg-names = "dsi_phy",
3132                                             "dsi_phy_lane",
3133                                             "dsi_pll";
3134
3135                                 #clock-cells = <1>;
3136                                 #phy-cells = <0>;
3137
3138                                 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
3139                                          <&rpmhcc RPMH_CXO_CLK>;
3140                                 clock-names = "iface", "ref";
3141
3142                                 status = "disabled";
3143                         };
3144                 };
3145
3146                 dispcc: clock-controller@af00000 {
3147                         compatible = "qcom,sc7180-dispcc";
3148                         reg = <0 0x0af00000 0 0x200000>;
3149                         clocks = <&rpmhcc RPMH_CXO_CLK>,
3150                                  <&gcc GCC_DISP_GPLL0_CLK_SRC>,
3151                                  <&dsi_phy 0>,
3152                                  <&dsi_phy 1>,
3153                                  <0>,
3154                                  <0>;
3155                         clock-names = "bi_tcxo",
3156                                       "gcc_disp_gpll0_clk_src",
3157                                       "dsi0_phy_pll_out_byteclk",
3158                                       "dsi0_phy_pll_out_dsiclk",
3159                                       "dp_phy_pll_link_clk",
3160                                       "dp_phy_pll_vco_div_clk";
3161                         #clock-cells = <1>;
3162                         #reset-cells = <1>;
3163                         #power-domain-cells = <1>;
3164                 };
3165
3166                 pdc: interrupt-controller@b220000 {
3167                         compatible = "qcom,sc7180-pdc", "qcom,pdc";
3168                         reg = <0 0x0b220000 0 0x30000>;
3169                         qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
3170                         #interrupt-cells = <2>;
3171                         interrupt-parent = <&intc>;
3172                         interrupt-controller;
3173                 };
3174
3175                 pdc_reset: reset-controller@b2e0000 {
3176                         compatible = "qcom,sc7180-pdc-global", "qcom,sdm845-pdc-global";
3177                         reg = <0 0x0b2e0000 0 0x20000>;
3178                         #reset-cells = <1>;
3179                 };
3180
3181                 tsens0: thermal-sensor@c263000 {
3182                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3183                         reg = <0 0x0c263000 0 0x1ff>, /* TM */
3184                                 <0 0x0c222000 0 0x1ff>; /* SROT */
3185                         #qcom,sensors = <15>;
3186                         interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>,
3187                                      <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>;
3188                         interrupt-names = "uplow","critical";
3189                         #thermal-sensor-cells = <1>;
3190                 };
3191
3192                 tsens1: thermal-sensor@c265000 {
3193                         compatible = "qcom,sc7180-tsens","qcom,tsens-v2";
3194                         reg = <0 0x0c265000 0 0x1ff>, /* TM */
3195                                 <0 0x0c223000 0 0x1ff>; /* SROT */
3196                         #qcom,sensors = <10>;
3197                         interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>,
3198                                      <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>;
3199                         interrupt-names = "uplow","critical";
3200                         #thermal-sensor-cells = <1>;
3201                 };
3202
3203                 aoss_reset: reset-controller@c2a0000 {
3204                         compatible = "qcom,sc7180-aoss-cc", "qcom,sdm845-aoss-cc";
3205                         reg = <0 0x0c2a0000 0 0x31000>;
3206                         #reset-cells = <1>;
3207                 };
3208
3209                 aoss_qmp: qmp@c300000 {
3210                         compatible = "qcom,sc7180-aoss-qmp";
3211                         reg = <0 0x0c300000 0 0x100000>;
3212                         interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
3213                         mboxes = <&apss_shared 0>;
3214
3215                         #clock-cells = <0>;
3216                         #power-domain-cells = <1>;
3217                 };
3218
3219                 spmi_bus: spmi@c440000 {
3220                         compatible = "qcom,spmi-pmic-arb";
3221                         reg = <0 0x0c440000 0 0x1100>,
3222                               <0 0x0c600000 0 0x2000000>,
3223                               <0 0x0e600000 0 0x100000>,
3224                               <0 0x0e700000 0 0xa0000>,
3225                               <0 0x0c40a000 0 0x26000>;
3226                         reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
3227                         interrupt-names = "periph_irq";
3228                         interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
3229                         qcom,ee = <0>;
3230                         qcom,channel = <0>;
3231                         #address-cells = <1>;
3232                         #size-cells = <1>;
3233                         interrupt-controller;
3234                         #interrupt-cells = <4>;
3235                         cell-index = <0>;
3236                 };
3237
3238                 apps_smmu: iommu@15000000 {
3239                         compatible = "qcom,sc7180-smmu-500", "arm,mmu-500";
3240                         reg = <0 0x15000000 0 0x100000>;
3241                         #iommu-cells = <2>;
3242                         #global-interrupts = <1>;
3243                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
3244                                      <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
3245                                      <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
3246                                      <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
3247                                      <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
3248                                      <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
3249                                      <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
3250                                      <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
3251                                      <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
3252                                      <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
3253                                      <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
3254                                      <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
3255                                      <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
3256                                      <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
3257                                      <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
3258                                      <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
3259                                      <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
3260                                      <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
3261                                      <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
3262                                      <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
3263                                      <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
3264                                      <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
3265                                      <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
3266                                      <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
3267                                      <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
3268                                      <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
3269                                      <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
3270                                      <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
3271                                      <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
3272                                      <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
3273                                      <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
3274                                      <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
3275                                      <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
3276                                      <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
3277                                      <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
3278                                      <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
3279                                      <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
3280                                      <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
3281                                      <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
3282                                      <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
3283                                      <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
3284                                      <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
3285                                      <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
3286                                      <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
3287                                      <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
3288                                      <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
3289                                      <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
3290                                      <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
3291                                      <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
3292                                      <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
3293                                      <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
3294                                      <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
3295                                      <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
3296                                      <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
3297                                      <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
3298                                      <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
3299                                      <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
3300                                      <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
3301                                      <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
3302                                      <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
3303                                      <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
3304                                      <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
3305                                      <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
3306                                      <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
3307                                      <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
3308                                      <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
3309                                      <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
3310                                      <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
3311                                      <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
3312                                      <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
3313                                      <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
3314                                      <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
3315                                      <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
3316                                      <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
3317                                      <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
3318                                      <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
3319                                      <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
3320                                      <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
3321                                      <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
3322                                      <GIC_SPI 411 IRQ_TYPE_LEVEL_HIGH>,
3323                                      <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>;
3324                 };
3325
3326                 intc: interrupt-controller@17a00000 {
3327                         compatible = "arm,gic-v3";
3328                         #address-cells = <2>;
3329                         #size-cells = <2>;
3330                         ranges;
3331                         #interrupt-cells = <3>;
3332                         interrupt-controller;
3333                         reg = <0 0x17a00000 0 0x10000>,     /* GICD */
3334                               <0 0x17a60000 0 0x100000>;    /* GICR * 8 */
3335                         interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
3336
3337                         msi-controller@17a40000 {
3338                                 compatible = "arm,gic-v3-its";
3339                                 msi-controller;
3340                                 #msi-cells = <1>;
3341                                 reg = <0 0x17a40000 0 0x20000>;
3342                                 status = "disabled";
3343                         };
3344                 };
3345
3346                 apss_shared: mailbox@17c00000 {
3347                         compatible = "qcom,sc7180-apss-shared";
3348                         reg = <0 0x17c00000 0 0x10000>;
3349                         #mbox-cells = <1>;
3350                 };
3351
3352                 watchdog@17c10000 {
3353                         compatible = "qcom,apss-wdt-sc7180", "qcom,kpss-wdt";
3354                         reg = <0 0x17c10000 0 0x1000>;
3355                         clocks = <&sleep_clk>;
3356                 };
3357
3358                 timer@17c20000{
3359                         #address-cells = <2>;
3360                         #size-cells = <2>;
3361                         ranges;
3362                         compatible = "arm,armv7-timer-mem";
3363                         reg = <0 0x17c20000 0 0x1000>;
3364
3365                         frame@17c21000 {
3366                                 frame-number = <0>;
3367                                 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
3368                                              <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
3369                                 reg = <0 0x17c21000 0 0x1000>,
3370                                       <0 0x17c22000 0 0x1000>;
3371                         };
3372
3373                         frame@17c23000 {
3374                                 frame-number = <1>;
3375                                 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
3376                                 reg = <0 0x17c23000 0 0x1000>;
3377                                 status = "disabled";
3378                         };
3379
3380                         frame@17c25000 {
3381                                 frame-number = <2>;
3382                                 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
3383                                 reg = <0 0x17c25000 0 0x1000>;
3384                                 status = "disabled";
3385                         };
3386
3387                         frame@17c27000 {
3388                                 frame-number = <3>;
3389                                 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
3390                                 reg = <0 0x17c27000 0 0x1000>;
3391                                 status = "disabled";
3392                         };
3393
3394                         frame@17c29000 {
3395                                 frame-number = <4>;
3396                                 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
3397                                 reg = <0 0x17c29000 0 0x1000>;
3398                                 status = "disabled";
3399                         };
3400
3401                         frame@17c2b000 {
3402                                 frame-number = <5>;
3403                                 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
3404                                 reg = <0 0x17c2b000 0 0x1000>;
3405                                 status = "disabled";
3406                         };
3407
3408                         frame@17c2d000 {
3409                                 frame-number = <6>;
3410                                 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
3411                                 reg = <0 0x17c2d000 0 0x1000>;
3412                                 status = "disabled";
3413                         };
3414                 };
3415
3416                 apps_rsc: rsc@18200000 {
3417                         compatible = "qcom,rpmh-rsc";
3418                         reg = <0 0x18200000 0 0x10000>,
3419                               <0 0x18210000 0 0x10000>,
3420                               <0 0x18220000 0 0x10000>;
3421                         reg-names = "drv-0", "drv-1", "drv-2";
3422                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
3423                                      <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
3424                                      <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
3425                         qcom,tcs-offset = <0xd00>;
3426                         qcom,drv-id = <2>;
3427                         qcom,tcs-config = <ACTIVE_TCS  2>,
3428                                           <SLEEP_TCS   3>,
3429                                           <WAKE_TCS    3>,
3430                                           <CONTROL_TCS 1>;
3431
3432                         rpmhcc: clock-controller {
3433                                 compatible = "qcom,sc7180-rpmh-clk";
3434                                 clocks = <&xo_board>;
3435                                 clock-names = "xo";
3436                                 #clock-cells = <1>;
3437                         };
3438
3439                         rpmhpd: power-controller {
3440                                 compatible = "qcom,sc7180-rpmhpd";
3441                                 #power-domain-cells = <1>;
3442                                 operating-points-v2 = <&rpmhpd_opp_table>;
3443
3444                                 rpmhpd_opp_table: opp-table {
3445                                         compatible = "operating-points-v2";
3446
3447                                         rpmhpd_opp_ret: opp1 {
3448                                                 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
3449                                         };
3450
3451                                         rpmhpd_opp_min_svs: opp2 {
3452                                                 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
3453                                         };
3454
3455                                         rpmhpd_opp_low_svs: opp3 {
3456                                                 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
3457                                         };
3458
3459                                         rpmhpd_opp_svs: opp4 {
3460                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
3461                                         };
3462
3463                                         rpmhpd_opp_svs_l1: opp5 {
3464                                                 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
3465                                         };
3466
3467                                         rpmhpd_opp_svs_l2: opp6 {
3468                                                 opp-level = <224>;
3469                                         };
3470
3471                                         rpmhpd_opp_nom: opp7 {
3472                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
3473                                         };
3474
3475                                         rpmhpd_opp_nom_l1: opp8 {
3476                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
3477                                         };
3478
3479                                         rpmhpd_opp_nom_l2: opp9 {
3480                                                 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
3481                                         };
3482
3483                                         rpmhpd_opp_turbo: opp10 {
3484                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
3485                                         };
3486
3487                                         rpmhpd_opp_turbo_l1: opp11 {
3488                                                 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
3489                                         };
3490                                 };
3491                         };
3492
3493                         apps_bcm_voter: bcm_voter {
3494                                 compatible = "qcom,bcm-voter";
3495                         };
3496                 };
3497
3498                 osm_l3: interconnect@18321000 {
3499                         compatible = "qcom,sc7180-osm-l3";
3500                         reg = <0 0x18321000 0 0x1400>;
3501
3502                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3503                         clock-names = "xo", "alternate";
3504
3505                         #interconnect-cells = <1>;
3506                 };
3507
3508                 cpufreq_hw: cpufreq@18323000 {
3509                         compatible = "qcom,cpufreq-hw";
3510                         reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
3511                         reg-names = "freq-domain0", "freq-domain1";
3512
3513                         clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
3514                         clock-names = "xo", "alternate";
3515
3516                         #freq-domain-cells = <1>;
3517                 };
3518
3519                 wifi: wifi@18800000 {
3520                         compatible = "qcom,wcn3990-wifi";
3521                         reg = <0 0x18800000 0 0x800000>;
3522                         reg-names = "membase";
3523                         iommus = <&apps_smmu 0xc0 0x1>;
3524                         interrupts =
3525                                 <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH /* CE0 */ >,
3526                                 <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH /* CE1 */ >,
3527                                 <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH /* CE2 */ >,
3528                                 <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH /* CE3 */ >,
3529                                 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH /* CE4 */ >,
3530                                 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH /* CE5 */ >,
3531                                 <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH /* CE6 */ >,
3532                                 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH /* CE7 */ >,
3533                                 <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH /* CE8 */ >,
3534                                 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH /* CE9 */ >,
3535                                 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH /* CE10 */>,
3536                                 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH /* CE11 */>;
3537                         memory-region = <&wlan_mem>;
3538                         qcom,msa-fixed-perm;
3539                         status = "disabled";
3540                 };
3541
3542                 lpasscc: clock-controller@62d00000 {
3543                         compatible = "qcom,sc7180-lpasscorecc";
3544                         reg = <0 0x62d00000 0 0x50000>,
3545                               <0 0x62780000 0 0x30000>;
3546                         reg-names = "lpass_core_cc", "lpass_audio_cc";
3547                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3548                                  <&rpmhcc RPMH_CXO_CLK>;
3549                         clock-names = "iface", "bi_tcxo";
3550                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3551                         #clock-cells = <1>;
3552                         #power-domain-cells = <1>;
3553                 };
3554
3555                 lpass_cpu: lpass@62f00000 {
3556                         compatible = "qcom,sc7180-lpass-cpu";
3557
3558                         reg = <0 0x62f00000 0 0x29000>;
3559                         reg-names = "lpass-lpaif";
3560
3561                         iommus = <&apps_smmu 0x1020 0>;
3562
3563                         power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
3564
3565                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3566                                  <&lpasscc LPASS_AUDIO_CORE_CORE_CLK>,
3567                                  <&lpasscc LPASS_AUDIO_CORE_EXT_MCLK0_CLK>,
3568                                  <&lpasscc LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK>,
3569                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK>,
3570                                  <&lpasscc LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK>;
3571
3572                         clock-names = "pcnoc-sway-clk", "audio-core",
3573                                         "mclk0", "pcnoc-mport-clk",
3574                                         "mi2s-bit-clk0", "mi2s-bit-clk1";
3575
3576
3577                         #sound-dai-cells = <1>;
3578                         #address-cells = <1>;
3579                         #size-cells = <0>;
3580
3581                         interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>;
3582                         interrupt-names = "lpass-irq-lpaif";
3583                 };
3584
3585                 lpass_hm: clock-controller@63000000 {
3586                         compatible = "qcom,sc7180-lpasshm";
3587                         reg = <0 0x63000000 0 0x28>;
3588                         clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>,
3589                                  <&rpmhcc RPMH_CXO_CLK>;
3590                         clock-names = "iface", "bi_tcxo";
3591                         #clock-cells = <1>;
3592                         #power-domain-cells = <1>;
3593                 };
3594         };
3595
3596         thermal-zones {
3597                 cpu0-thermal {
3598                         polling-delay-passive = <250>;
3599                         polling-delay = <0>;
3600
3601                         thermal-sensors = <&tsens0 1>;
3602                         sustainable-power = <768>;
3603
3604                         trips {
3605                                 cpu0_alert0: trip-point0 {
3606                                         temperature = <90000>;
3607                                         hysteresis = <2000>;
3608                                         type = "passive";
3609                                 };
3610
3611                                 cpu0_alert1: trip-point1 {
3612                                         temperature = <95000>;
3613                                         hysteresis = <2000>;
3614                                         type = "passive";
3615                                 };
3616
3617                                 cpu0_crit: cpu_crit {
3618                                         temperature = <110000>;
3619                                         hysteresis = <1000>;
3620                                         type = "critical";
3621                                 };
3622                         };
3623
3624                         cooling-maps {
3625                                 map0 {
3626                                         trip = <&cpu0_alert0>;
3627                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3628                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3629                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3630                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3631                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3632                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3633                                 };
3634                                 map1 {
3635                                         trip = <&cpu0_alert1>;
3636                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3637                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3638                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3639                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3640                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3641                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3642                                 };
3643                         };
3644                 };
3645
3646                 cpu1-thermal {
3647                         polling-delay-passive = <250>;
3648                         polling-delay = <0>;
3649
3650                         thermal-sensors = <&tsens0 2>;
3651                         sustainable-power = <768>;
3652
3653                         trips {
3654                                 cpu1_alert0: trip-point0 {
3655                                         temperature = <90000>;
3656                                         hysteresis = <2000>;
3657                                         type = "passive";
3658                                 };
3659
3660                                 cpu1_alert1: trip-point1 {
3661                                         temperature = <95000>;
3662                                         hysteresis = <2000>;
3663                                         type = "passive";
3664                                 };
3665
3666                                 cpu1_crit: cpu_crit {
3667                                         temperature = <110000>;
3668                                         hysteresis = <1000>;
3669                                         type = "critical";
3670                                 };
3671                         };
3672
3673                         cooling-maps {
3674                                 map0 {
3675                                         trip = <&cpu1_alert0>;
3676                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3677                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3678                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3679                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3680                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3681                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3682                                 };
3683                                 map1 {
3684                                         trip = <&cpu1_alert1>;
3685                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3686                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3687                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3688                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3689                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3690                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3691                                 };
3692                         };
3693                 };
3694
3695                 cpu2-thermal {
3696                         polling-delay-passive = <250>;
3697                         polling-delay = <0>;
3698
3699                         thermal-sensors = <&tsens0 3>;
3700                         sustainable-power = <768>;
3701
3702                         trips {
3703                                 cpu2_alert0: trip-point0 {
3704                                         temperature = <90000>;
3705                                         hysteresis = <2000>;
3706                                         type = "passive";
3707                                 };
3708
3709                                 cpu2_alert1: trip-point1 {
3710                                         temperature = <95000>;
3711                                         hysteresis = <2000>;
3712                                         type = "passive";
3713                                 };
3714
3715                                 cpu2_crit: cpu_crit {
3716                                         temperature = <110000>;
3717                                         hysteresis = <1000>;
3718                                         type = "critical";
3719                                 };
3720                         };
3721
3722                         cooling-maps {
3723                                 map0 {
3724                                         trip = <&cpu2_alert0>;
3725                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3726                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3727                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3728                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3729                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3730                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3731                                 };
3732                                 map1 {
3733                                         trip = <&cpu2_alert1>;
3734                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3735                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3736                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3737                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3738                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3739                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3740                                 };
3741                         };
3742                 };
3743
3744                 cpu3-thermal {
3745                         polling-delay-passive = <250>;
3746                         polling-delay = <0>;
3747
3748                         thermal-sensors = <&tsens0 4>;
3749                         sustainable-power = <768>;
3750
3751                         trips {
3752                                 cpu3_alert0: trip-point0 {
3753                                         temperature = <90000>;
3754                                         hysteresis = <2000>;
3755                                         type = "passive";
3756                                 };
3757
3758                                 cpu3_alert1: trip-point1 {
3759                                         temperature = <95000>;
3760                                         hysteresis = <2000>;
3761                                         type = "passive";
3762                                 };
3763
3764                                 cpu3_crit: cpu_crit {
3765                                         temperature = <110000>;
3766                                         hysteresis = <1000>;
3767                                         type = "critical";
3768                                 };
3769                         };
3770
3771                         cooling-maps {
3772                                 map0 {
3773                                         trip = <&cpu3_alert0>;
3774                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3775                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3776                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3777                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3778                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3779                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3780                                 };
3781                                 map1 {
3782                                         trip = <&cpu3_alert1>;
3783                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3784                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3785                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3786                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3787                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3788                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3789                                 };
3790                         };
3791                 };
3792
3793                 cpu4-thermal {
3794                         polling-delay-passive = <250>;
3795                         polling-delay = <0>;
3796
3797                         thermal-sensors = <&tsens0 5>;
3798                         sustainable-power = <768>;
3799
3800                         trips {
3801                                 cpu4_alert0: trip-point0 {
3802                                         temperature = <90000>;
3803                                         hysteresis = <2000>;
3804                                         type = "passive";
3805                                 };
3806
3807                                 cpu4_alert1: trip-point1 {
3808                                         temperature = <95000>;
3809                                         hysteresis = <2000>;
3810                                         type = "passive";
3811                                 };
3812
3813                                 cpu4_crit: cpu_crit {
3814                                         temperature = <110000>;
3815                                         hysteresis = <1000>;
3816                                         type = "critical";
3817                                 };
3818                         };
3819
3820                         cooling-maps {
3821                                 map0 {
3822                                         trip = <&cpu4_alert0>;
3823                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3824                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3825                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3826                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3827                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3828                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3829                                 };
3830                                 map1 {
3831                                         trip = <&cpu4_alert1>;
3832                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3833                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3834                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3835                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3836                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3837                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3838                                 };
3839                         };
3840                 };
3841
3842                 cpu5-thermal {
3843                         polling-delay-passive = <250>;
3844                         polling-delay = <0>;
3845
3846                         thermal-sensors = <&tsens0 6>;
3847                         sustainable-power = <768>;
3848
3849                         trips {
3850                                 cpu5_alert0: trip-point0 {
3851                                         temperature = <90000>;
3852                                         hysteresis = <2000>;
3853                                         type = "passive";
3854                                 };
3855
3856                                 cpu5_alert1: trip-point1 {
3857                                         temperature = <95000>;
3858                                         hysteresis = <2000>;
3859                                         type = "passive";
3860                                 };
3861
3862                                 cpu5_crit: cpu_crit {
3863                                         temperature = <110000>;
3864                                         hysteresis = <1000>;
3865                                         type = "critical";
3866                                 };
3867                         };
3868
3869                         cooling-maps {
3870                                 map0 {
3871                                         trip = <&cpu5_alert0>;
3872                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3873                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3874                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3875                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3876                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3877                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3878                                 };
3879                                 map1 {
3880                                         trip = <&cpu5_alert1>;
3881                                         cooling-device = <&CPU0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3882                                                          <&CPU1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3883                                                          <&CPU2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3884                                                          <&CPU3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3885                                                          <&CPU4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3886                                                          <&CPU5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3887                                 };
3888                         };
3889                 };
3890
3891                 cpu6-thermal {
3892                         polling-delay-passive = <250>;
3893                         polling-delay = <0>;
3894
3895                         thermal-sensors = <&tsens0 9>;
3896                         sustainable-power = <1202>;
3897
3898                         trips {
3899                                 cpu6_alert0: trip-point0 {
3900                                         temperature = <90000>;
3901                                         hysteresis = <2000>;
3902                                         type = "passive";
3903                                 };
3904
3905                                 cpu6_alert1: trip-point1 {
3906                                         temperature = <95000>;
3907                                         hysteresis = <2000>;
3908                                         type = "passive";
3909                                 };
3910
3911                                 cpu6_crit: cpu_crit {
3912                                         temperature = <110000>;
3913                                         hysteresis = <1000>;
3914                                         type = "critical";
3915                                 };
3916                         };
3917
3918                         cooling-maps {
3919                                 map0 {
3920                                         trip = <&cpu6_alert0>;
3921                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3922                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3923                                 };
3924                                 map1 {
3925                                         trip = <&cpu6_alert1>;
3926                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3927                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3928                                 };
3929                         };
3930                 };
3931
3932                 cpu7-thermal {
3933                         polling-delay-passive = <250>;
3934                         polling-delay = <0>;
3935
3936                         thermal-sensors = <&tsens0 10>;
3937                         sustainable-power = <1202>;
3938
3939                         trips {
3940                                 cpu7_alert0: trip-point0 {
3941                                         temperature = <90000>;
3942                                         hysteresis = <2000>;
3943                                         type = "passive";
3944                                 };
3945
3946                                 cpu7_alert1: trip-point1 {
3947                                         temperature = <95000>;
3948                                         hysteresis = <2000>;
3949                                         type = "passive";
3950                                 };
3951
3952                                 cpu7_crit: cpu_crit {
3953                                         temperature = <110000>;
3954                                         hysteresis = <1000>;
3955                                         type = "critical";
3956                                 };
3957                         };
3958
3959                         cooling-maps {
3960                                 map0 {
3961                                         trip = <&cpu7_alert0>;
3962                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3963                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3964                                 };
3965                                 map1 {
3966                                         trip = <&cpu7_alert1>;
3967                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
3968                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
3969                                 };
3970                         };
3971                 };
3972
3973                 cpu8-thermal {
3974                         polling-delay-passive = <250>;
3975                         polling-delay = <0>;
3976
3977                         thermal-sensors = <&tsens0 11>;
3978                         sustainable-power = <1202>;
3979
3980                         trips {
3981                                 cpu8_alert0: trip-point0 {
3982                                         temperature = <90000>;
3983                                         hysteresis = <2000>;
3984                                         type = "passive";
3985                                 };
3986
3987                                 cpu8_alert1: trip-point1 {
3988                                         temperature = <95000>;
3989                                         hysteresis = <2000>;
3990                                         type = "passive";
3991                                 };
3992
3993                                 cpu8_crit: cpu_crit {
3994                                         temperature = <110000>;
3995                                         hysteresis = <1000>;
3996                                         type = "critical";
3997                                 };
3998                         };
3999
4000                         cooling-maps {
4001                                 map0 {
4002                                         trip = <&cpu8_alert0>;
4003                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4004                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4005                                 };
4006                                 map1 {
4007                                         trip = <&cpu8_alert1>;
4008                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4009                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4010                                 };
4011                         };
4012                 };
4013
4014                 cpu9-thermal {
4015                         polling-delay-passive = <250>;
4016                         polling-delay = <0>;
4017
4018                         thermal-sensors = <&tsens0 12>;
4019                         sustainable-power = <1202>;
4020
4021                         trips {
4022                                 cpu9_alert0: trip-point0 {
4023                                         temperature = <90000>;
4024                                         hysteresis = <2000>;
4025                                         type = "passive";
4026                                 };
4027
4028                                 cpu9_alert1: trip-point1 {
4029                                         temperature = <95000>;
4030                                         hysteresis = <2000>;
4031                                         type = "passive";
4032                                 };
4033
4034                                 cpu9_crit: cpu_crit {
4035                                         temperature = <110000>;
4036                                         hysteresis = <1000>;
4037                                         type = "critical";
4038                                 };
4039                         };
4040
4041                         cooling-maps {
4042                                 map0 {
4043                                         trip = <&cpu9_alert0>;
4044                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4045                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4046                                 };
4047                                 map1 {
4048                                         trip = <&cpu9_alert1>;
4049                                         cooling-device = <&CPU6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
4050                                                          <&CPU7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4051                                 };
4052                         };
4053                 };
4054
4055                 aoss0-thermal {
4056                         polling-delay-passive = <250>;
4057                         polling-delay = <0>;
4058
4059                         thermal-sensors = <&tsens0 0>;
4060
4061                         trips {
4062                                 aoss0_alert0: trip-point0 {
4063                                         temperature = <90000>;
4064                                         hysteresis = <2000>;
4065                                         type = "hot";
4066                                 };
4067
4068                                 aoss0_crit: aoss0_crit {
4069                                         temperature = <110000>;
4070                                         hysteresis = <2000>;
4071                                         type = "critical";
4072                                 };
4073                         };
4074                 };
4075
4076                 cpuss0-thermal {
4077                         polling-delay-passive = <250>;
4078                         polling-delay = <0>;
4079
4080                         thermal-sensors = <&tsens0 7>;
4081
4082                         trips {
4083                                 cpuss0_alert0: trip-point0 {
4084                                         temperature = <90000>;
4085                                         hysteresis = <2000>;
4086                                         type = "hot";
4087                                 };
4088                                 cpuss0_crit: cluster0_crit {
4089                                         temperature = <110000>;
4090                                         hysteresis = <2000>;
4091                                         type = "critical";
4092                                 };
4093                         };
4094                 };
4095
4096                 cpuss1-thermal {
4097                         polling-delay-passive = <250>;
4098                         polling-delay = <0>;
4099
4100                         thermal-sensors = <&tsens0 8>;
4101
4102                         trips {
4103                                 cpuss1_alert0: trip-point0 {
4104                                         temperature = <90000>;
4105                                         hysteresis = <2000>;
4106                                         type = "hot";
4107                                 };
4108                                 cpuss1_crit: cluster0_crit {
4109                                         temperature = <110000>;
4110                                         hysteresis = <2000>;
4111                                         type = "critical";
4112                                 };
4113                         };
4114                 };
4115
4116                 gpuss0-thermal {
4117                         polling-delay-passive = <250>;
4118                         polling-delay = <0>;
4119
4120                         thermal-sensors = <&tsens0 13>;
4121
4122                         trips {
4123                                 gpuss0_alert0: trip-point0 {
4124                                         temperature = <95000>;
4125                                         hysteresis = <2000>;
4126                                         type = "passive";
4127                                 };
4128
4129                                 gpuss0_crit: gpuss0_crit {
4130                                         temperature = <110000>;
4131                                         hysteresis = <2000>;
4132                                         type = "critical";
4133                                 };
4134                         };
4135
4136                         cooling-maps {
4137                                 map0 {
4138                                         trip = <&gpuss0_alert0>;
4139                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4140                                 };
4141                         };
4142                 };
4143
4144                 gpuss1-thermal {
4145                         polling-delay-passive = <250>;
4146                         polling-delay = <0>;
4147
4148                         thermal-sensors = <&tsens0 14>;
4149
4150                         trips {
4151                                 gpuss1_alert0: trip-point0 {
4152                                         temperature = <95000>;
4153                                         hysteresis = <2000>;
4154                                         type = "passive";
4155                                 };
4156
4157                                 gpuss1_crit: gpuss1_crit {
4158                                         temperature = <110000>;
4159                                         hysteresis = <2000>;
4160                                         type = "critical";
4161                                 };
4162                         };
4163
4164                         cooling-maps {
4165                                 map0 {
4166                                         trip = <&gpuss1_alert0>;
4167                                         cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
4168                                 };
4169                         };
4170                 };
4171
4172                 aoss1-thermal {
4173                         polling-delay-passive = <250>;
4174                         polling-delay = <0>;
4175
4176                         thermal-sensors = <&tsens1 0>;
4177
4178                         trips {
4179                                 aoss1_alert0: trip-point0 {
4180                                         temperature = <90000>;
4181                                         hysteresis = <2000>;
4182                                         type = "hot";
4183                                 };
4184
4185                                 aoss1_crit: aoss1_crit {
4186                                         temperature = <110000>;
4187                                         hysteresis = <2000>;
4188                                         type = "critical";
4189                                 };
4190                         };
4191                 };
4192
4193                 cwlan-thermal {
4194                         polling-delay-passive = <250>;
4195                         polling-delay = <0>;
4196
4197                         thermal-sensors = <&tsens1 1>;
4198
4199                         trips {
4200                                 cwlan_alert0: trip-point0 {
4201                                         temperature = <90000>;
4202                                         hysteresis = <2000>;
4203                                         type = "hot";
4204                                 };
4205
4206                                 cwlan_crit: cwlan_crit {
4207                                         temperature = <110000>;
4208                                         hysteresis = <2000>;
4209                                         type = "critical";
4210                                 };
4211                         };
4212                 };
4213
4214                 audio-thermal {
4215                         polling-delay-passive = <250>;
4216                         polling-delay = <0>;
4217
4218                         thermal-sensors = <&tsens1 2>;
4219
4220                         trips {
4221                                 audio_alert0: trip-point0 {
4222                                         temperature = <90000>;
4223                                         hysteresis = <2000>;
4224                                         type = "hot";
4225                                 };
4226
4227                                 audio_crit: audio_crit {
4228                                         temperature = <110000>;
4229                                         hysteresis = <2000>;
4230                                         type = "critical";
4231                                 };
4232                         };
4233                 };
4234
4235                 ddr-thermal {
4236                         polling-delay-passive = <250>;
4237                         polling-delay = <0>;
4238
4239                         thermal-sensors = <&tsens1 3>;
4240
4241                         trips {
4242                                 ddr_alert0: trip-point0 {
4243                                         temperature = <90000>;
4244                                         hysteresis = <2000>;
4245                                         type = "hot";
4246                                 };
4247
4248                                 ddr_crit: ddr_crit {
4249                                         temperature = <110000>;
4250                                         hysteresis = <2000>;
4251                                         type = "critical";
4252                                 };
4253                         };
4254                 };
4255
4256                 q6-hvx-thermal {
4257                         polling-delay-passive = <250>;
4258                         polling-delay = <0>;
4259
4260                         thermal-sensors = <&tsens1 4>;
4261
4262                         trips {
4263                                 q6_hvx_alert0: trip-point0 {
4264                                         temperature = <90000>;
4265                                         hysteresis = <2000>;
4266                                         type = "hot";
4267                                 };
4268
4269                                 q6_hvx_crit: q6_hvx_crit {
4270                                         temperature = <110000>;
4271                                         hysteresis = <2000>;
4272                                         type = "critical";
4273                                 };
4274                         };
4275                 };
4276
4277                 camera-thermal {
4278                         polling-delay-passive = <250>;
4279                         polling-delay = <0>;
4280
4281                         thermal-sensors = <&tsens1 5>;
4282
4283                         trips {
4284                                 camera_alert0: trip-point0 {
4285                                         temperature = <90000>;
4286                                         hysteresis = <2000>;
4287                                         type = "hot";
4288                                 };
4289
4290                                 camera_crit: camera_crit {
4291                                         temperature = <110000>;
4292                                         hysteresis = <2000>;
4293                                         type = "critical";
4294                                 };
4295                         };
4296                 };
4297
4298                 mdm-core-thermal {
4299                         polling-delay-passive = <250>;
4300                         polling-delay = <0>;
4301
4302                         thermal-sensors = <&tsens1 6>;
4303
4304                         trips {
4305                                 mdm_alert0: trip-point0 {
4306                                         temperature = <90000>;
4307                                         hysteresis = <2000>;
4308                                         type = "hot";
4309                                 };
4310
4311                                 mdm_crit: mdm_crit {
4312                                         temperature = <110000>;
4313                                         hysteresis = <2000>;
4314                                         type = "critical";
4315                                 };
4316                         };
4317                 };
4318
4319                 mdm-dsp-thermal {
4320                         polling-delay-passive = <250>;
4321                         polling-delay = <0>;
4322
4323                         thermal-sensors = <&tsens1 7>;
4324
4325                         trips {
4326                                 mdm_dsp_alert0: trip-point0 {
4327                                         temperature = <90000>;
4328                                         hysteresis = <2000>;
4329                                         type = "hot";
4330                                 };
4331
4332                                 mdm_dsp_crit: mdm_dsp_crit {
4333                                         temperature = <110000>;
4334                                         hysteresis = <2000>;
4335                                         type = "critical";
4336                                 };
4337                         };
4338                 };
4339
4340                 npu-thermal {
4341                         polling-delay-passive = <250>;
4342                         polling-delay = <0>;
4343
4344                         thermal-sensors = <&tsens1 8>;
4345
4346                         trips {
4347                                 npu_alert0: trip-point0 {
4348                                         temperature = <90000>;
4349                                         hysteresis = <2000>;
4350                                         type = "hot";
4351                                 };
4352
4353                                 npu_crit: npu_crit {
4354                                         temperature = <110000>;
4355                                         hysteresis = <2000>;
4356                                         type = "critical";
4357                                 };
4358                         };
4359                 };
4360
4361                 video-thermal {
4362                         polling-delay-passive = <250>;
4363                         polling-delay = <0>;
4364
4365                         thermal-sensors = <&tsens1 9>;
4366
4367                         trips {
4368                                 video_alert0: trip-point0 {
4369                                         temperature = <90000>;
4370                                         hysteresis = <2000>;
4371                                         type = "hot";
4372                                 };
4373
4374                                 video_crit: video_crit {
4375                                         temperature = <110000>;
4376                                         hysteresis = <2000>;
4377                                         type = "critical";
4378                                 };
4379                         };
4380                 };
4381         };
4382
4383         timer {
4384                 compatible = "arm,armv8-timer";
4385                 interrupts = <GIC_PPI 1 IRQ_TYPE_LEVEL_LOW>,
4386                              <GIC_PPI 2 IRQ_TYPE_LEVEL_LOW>,
4387                              <GIC_PPI 3 IRQ_TYPE_LEVEL_LOW>,
4388                              <GIC_PPI 0 IRQ_TYPE_LEVEL_LOW>;
4389         };
4390 };