1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2020 Marvell International Ltd.
6 #include "cn9130.dtsi" /* include SoC device tree */
8 #include <dt-bindings/gpio/gpio.h>
12 stdout-path = "serial0:115200n8";
17 ethernet0 = &cp0_eth0;
18 ethernet1 = &cp0_eth1;
19 ethernet2 = &cp0_eth2;
23 device_type = "memory";
24 reg = <0x0 0x0 0x0 0x80000000>;
27 ap0_reg_mmc_vccq: ap0_mmc_vccq@0 {
28 compatible = "regulator-gpio";
29 regulator-name = "ap0_mmc_vccq";
30 regulator-min-microvolt = <1800000>;
31 regulator-max-microvolt = <3300000>;
32 gpios = <&expander0 5 GPIO_ACTIVE_HIGH>;
37 cp0_reg_usb3_vbus1: cp0_usb3_vbus@1 {
38 compatible = "regulator-fixed";
39 regulator-name = "cp0-xhci1-vbus";
40 regulator-min-microvolt = <5000000>;
41 regulator-max-microvolt = <5000000>;
43 gpio = <&expander0 8 GPIO_ACTIVE_HIGH>;
46 cp0_usb3_0_phy0: cp0_usb3_phy0 {
47 compatible = "usb-nop-xceiv";
50 cp0_usb3_0_phy1: cp0_usb3_phy1 {
51 compatible = "usb-nop-xceiv";
52 vcc-supply = <&cp0_reg_usb3_vbus1>;
55 cp0_reg_sd_vccq: cp0_sd_vccq@0 {
56 compatible = "regulator-gpio";
57 regulator-name = "cp0_sd_vccq";
58 regulator-min-microvolt = <1800000>;
59 regulator-max-microvolt = <3300000>;
60 gpios = <&cp0_gpio2 18 GPIO_ACTIVE_HIGH>;
65 cp0_reg_sd_vcc: cp0_sd_vcc@0 {
66 compatible = "regulator-fixed";
67 regulator-name = "cp0_sd_vcc";
68 regulator-min-microvolt = <3300000>;
69 regulator-max-microvolt = <3300000>;
70 gpio = <&cp0_gpio2 19 GPIO_ACTIVE_HIGH>;
80 /* on-board eMMC U6 */
82 pinctrl-names = "default";
86 vqmmc-supply = <&ap0_reg_mmc_vccq>;
90 cp0_pinctrl: pinctrl {
91 compatible = "marvell,cp115-standalone-pinctrl";
93 cp0_i2c0_pins: cp0-i2c-pins-0 {
94 marvell,pins = "mpp37", "mpp38";
95 marvell,function = "i2c0";
97 cp0_i2c1_pins: cp0-i2c-pins-1 {
98 marvell,pins = "mpp35", "mpp36";
99 marvell,function = "i2c1";
101 cp0_sdhci_cd_pins_crb: cp0-sdhci-cd-pins-crb {
102 marvell,pins = "mpp55";
103 marvell,function = "gpio";
105 cp0_sdhci_pins: cp0-sdhi-pins-0 {
106 marvell,pins = "mpp56", "mpp57", "mpp58",
107 "mpp59", "mpp60", "mpp61";
108 marvell,function = "sdio";
110 cp0_spi0_pins: cp0-spi-pins-0 {
111 marvell,pins = "mpp13", "mpp14", "mpp15", "mpp16";
112 marvell,function = "spi1";
118 pinctrl-names = "default";
119 pinctrl-0 = <&cp0_i2c0_pins>;
121 clock-frequency = <100000>;
122 expander0: mcp23x17@20 {
123 compatible = "microchip,mcp23017";
132 pinctrl-names = "default";
133 pinctrl-0 = <&cp0_i2c1_pins>;
134 clock-frequency = <100000>;
140 pinctrl-names = "default";
141 pinctrl-0 = <&cp0_sdhci_pins
142 &cp0_sdhci_cd_pins_crb>;
144 cd-gpios = <&cp0_gpio2 23 GPIO_ACTIVE_HIGH>;
145 vqmmc-supply = <&cp0_reg_sd_vccq>;
146 vmmc-supply = <&cp0_reg_sd_vcc>;
151 pinctrl-names = "default";
152 pinctrl-0 = <&cp0_spi0_pins>;
153 reg = <0x700680 0x50>, /* control */
154 <0x2000000 0x1000000>; /* CS0 */
158 #address-cells = <0x1>;
160 compatible = "jedec,spi-nor";
162 /* On-board MUX does not allow higher frequencies */
163 spi-max-frequency = <40000000>;
166 compatible = "fixed-partitions";
167 #address-cells = <1>;
172 reg = <0x0 0x200000>;
176 label = "Filesystem";
177 reg = <0x200000 0xe00000>;
185 phy0: ethernet-phy@0 {
192 nbaset_phy0: ethernet-phy@0 {
193 compatible = "ethernet-phy-ieee802.3-c45";
203 /* This port is connected to 88E6393X switch */
205 phy-mode = "10gbase-r";
206 managed = "in-band-status";
207 phys = <&cp0_comphy4 0>;
213 phy-mode = "rgmii-id";
217 /* This port uses "2500base-t" phy-mode */
219 phy = <&nbaset_phy0>;
220 phys = <&cp0_comphy5 2>;