1 /* linux/arch/arm/mach-exynos4/platsmp.c
3 * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
4 * http://www.samsung.com
6 * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
8 * Copyright (C) 2002 ARM Ltd.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/delay.h>
19 #include <linux/device.h>
20 #include <linux/jiffies.h>
21 #include <linux/smp.h>
24 #include <asm/cacheflush.h>
25 #include <asm/hardware/gic.h>
26 #include <asm/smp_scu.h>
27 #include <asm/unified.h>
29 #include <mach/hardware.h>
30 #include <mach/regs-clock.h>
31 #include <mach/regs-pmu.h>
35 extern unsigned int gic_bank_offset;
36 extern void exynos4_secondary_startup(void);
38 #define CPU1_BOOT_REG (samsung_rev() == EXYNOS4210_REV_1_1 ? \
39 S5P_INFORM5 : S5P_VA_SYSRAM)
42 * control for which core is the next to come out of the secondary
46 volatile int __cpuinitdata pen_release = -1;
49 * Write pen_release in a way that is guaranteed to be visible to all
50 * observers, irrespective of whether they're taking part in coherency
51 * or not. This is necessary for the hotplug code to work reliably.
53 static void write_pen_release(int val)
57 __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
58 outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
61 static void __iomem *scu_base_addr(void)
63 return (void __iomem *)(S5P_VA_SCU);
66 static DEFINE_SPINLOCK(boot_lock);
68 static void __cpuinit exynos4_gic_secondary_init(void)
70 void __iomem *dist_base = S5P_VA_GIC_DIST +
71 (gic_bank_offset * smp_processor_id());
72 void __iomem *cpu_base = S5P_VA_GIC_CPU +
73 (gic_bank_offset * smp_processor_id());
77 * Deal with the banked PPI and SGI interrupts - disable all
78 * PPI interrupts, ensure all SGI interrupts are enabled.
80 __raw_writel(0xffff0000, dist_base + GIC_DIST_ENABLE_CLEAR);
81 __raw_writel(0x0000ffff, dist_base + GIC_DIST_ENABLE_SET);
84 * Set priority on PPI and SGI interrupts
86 for (i = 0; i < 32; i += 4)
87 __raw_writel(0xa0a0a0a0, dist_base + GIC_DIST_PRI + i * 4 / 4);
89 __raw_writel(0xf0, cpu_base + GIC_CPU_PRIMASK);
90 __raw_writel(1, cpu_base + GIC_CPU_CTRL);
93 void __cpuinit platform_secondary_init(unsigned int cpu)
96 * if any interrupts are already enabled for the primary
97 * core (e.g. timer irq), then they will not have been enabled
100 exynos4_gic_secondary_init();
103 * let the primary processor know we're out of the
104 * pen, then head off into the C entry point
106 write_pen_release(-1);
109 * Synchronise with the boot thread.
111 spin_lock(&boot_lock);
112 spin_unlock(&boot_lock);
114 set_cpu_online(cpu, true);
117 int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
119 unsigned long timeout;
122 * Set synchronisation state between this boot processor
123 * and the secondary one
125 spin_lock(&boot_lock);
128 * The secondary processor is waiting to be released from
129 * the holding pen - release it, then wait for it to flag
130 * that it has been released by resetting pen_release.
132 * Note that "pen_release" is the hardware CPU ID, whereas
133 * "cpu" is Linux's internal ID.
135 write_pen_release(cpu_logical_map(cpu));
137 if (!(__raw_readl(S5P_ARM_CORE1_STATUS) & S5P_CORE_LOCAL_PWR_EN)) {
138 __raw_writel(S5P_CORE_LOCAL_PWR_EN,
139 S5P_ARM_CORE1_CONFIGURATION);
143 /* wait max 10 ms until cpu1 is on */
144 while ((__raw_readl(S5P_ARM_CORE1_STATUS)
145 & S5P_CORE_LOCAL_PWR_EN) != S5P_CORE_LOCAL_PWR_EN) {
153 printk(KERN_ERR "cpu1 power enable failed");
154 spin_unlock(&boot_lock);
159 * Send the secondary CPU a soft interrupt, thereby causing
160 * the boot monitor to read the system wide flags register,
161 * and branch to the address found there.
164 timeout = jiffies + (1 * HZ);
165 while (time_before(jiffies, timeout)) {
168 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),
170 gic_raise_softirq(cpumask_of(cpu), 1);
172 if (pen_release == -1)
179 * now the secondary core is starting up let it run its
180 * calibrations, then wait for it to finish
182 spin_unlock(&boot_lock);
184 return pen_release != -1 ? -ENOSYS : 0;
188 * Initialise the CPU possible map early - this describes the CPUs
189 * which may be present or become present in the system.
192 void __init smp_init_cpus(void)
194 void __iomem *scu_base = scu_base_addr();
195 unsigned int i, ncores;
197 ncores = scu_base ? scu_get_core_count(scu_base) : 1;
200 if (ncores > nr_cpu_ids) {
201 pr_warn("SMP: %u cores greater than maximum (%u), clipping\n",
206 for (i = 0; i < ncores; i++)
207 set_cpu_possible(i, true);
209 set_smp_cross_call(gic_raise_softirq);
212 void __init platform_smp_prepare_cpus(unsigned int max_cpus)
215 scu_enable(scu_base_addr());
218 * Write the address of secondary startup into the
219 * system-wide flags register. The boot monitor waits
220 * until it receives a soft interrupt, and then the
221 * secondary CPU branches to this address.
223 __raw_writel(BSYM(virt_to_phys(exynos4_secondary_startup)),