1 # SPDX-License-Identifier: GPL-2.0
5 select ARCH_32BIT_OFF_T
6 select ARCH_HAS_BINFMT_FLAT
7 select ARCH_HAS_DEBUG_VIRTUAL if MMU
8 select ARCH_HAS_DMA_WRITE_COMBINE if !ARM_DMA_MEM_BUFFERABLE
9 select ARCH_HAS_ELF_RANDOMIZE
10 select ARCH_HAS_FORTIFY_SOURCE
11 select ARCH_HAS_KEEPINITRD
13 select ARCH_HAS_MEMBARRIER_SYNC_CORE
14 select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
15 select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
16 select ARCH_HAS_PHYS_TO_DMA
17 select ARCH_HAS_SETUP_DMA_OPS
18 select ARCH_HAS_SET_MEMORY
19 select ARCH_HAS_STRICT_KERNEL_RWX if MMU && !XIP_KERNEL
20 select ARCH_HAS_STRICT_MODULE_RWX if MMU
21 select ARCH_HAS_SYNC_DMA_FOR_DEVICE if SWIOTLB
22 select ARCH_HAS_SYNC_DMA_FOR_CPU if SWIOTLB
23 select ARCH_HAS_TEARDOWN_DMA_OPS if MMU
24 select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
25 select ARCH_HAVE_CUSTOM_GPIO_H
26 select ARCH_HAVE_NMI_SAFE_CMPXCHG if CPU_V7 || CPU_V7M || CPU_V6K
27 select ARCH_HAS_GCOV_PROFILE_ALL
28 select ARCH_KEEP_MEMBLOCK
29 select ARCH_MIGHT_HAVE_PC_PARPORT
30 select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
31 select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
32 select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
33 select ARCH_SUPPORTS_ATOMIC_RMW
34 select ARCH_SUPPORTS_HUGETLBFS if ARM_LPAE
35 select ARCH_USE_BUILTIN_BSWAP
36 select ARCH_USE_CMPXCHG_LOCKREF
37 select ARCH_USE_MEMTEST
38 select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT if MMU
39 select ARCH_WANT_IPC_PARSE_VERSION
40 select ARCH_WANT_LD_ORPHAN_WARN
41 select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
42 select BUILDTIME_TABLE_SORT if MMU
43 select CLONE_BACKWARDS
44 select CPU_PM if SUSPEND || CPU_IDLE
45 select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
46 select DMA_DECLARE_COHERENT
48 select DMA_REMAP if MMU
50 select EDAC_ATOMIC_SCRUB
51 select GENERIC_ALLOCATOR
52 select GENERIC_ARCH_TOPOLOGY if ARM_CPU_TOPOLOGY
53 select GENERIC_ATOMIC64 if CPU_V7M || CPU_V6 || !CPU_32v6K || !AEABI
54 select GENERIC_CLOCKEVENTS_BROADCAST if SMP
55 select GENERIC_IRQ_IPI if SMP
56 select GENERIC_CPU_AUTOPROBE
57 select GENERIC_EARLY_IOREMAP
58 select GENERIC_IDLE_POLL_SETUP
59 select GENERIC_IRQ_PROBE
60 select GENERIC_IRQ_SHOW
61 select GENERIC_IRQ_SHOW_LEVEL
62 select GENERIC_LIB_DEVMEM_IS_ALLOWED
63 select GENERIC_PCI_IOMAP
64 select GENERIC_SCHED_CLOCK
65 select GENERIC_SMP_IDLE_THREAD
66 select HANDLE_DOMAIN_IRQ
67 select HARDIRQS_SW_RESEND
68 select HAVE_ARCH_AUDITSYSCALL if AEABI && !OABI_COMPAT
69 select HAVE_ARCH_BITREVERSE if (CPU_32v7M || CPU_32v7) && !CPU_32v6
70 select HAVE_ARCH_JUMP_LABEL if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
71 select HAVE_ARCH_KGDB if !CPU_ENDIAN_BE32 && MMU
72 select HAVE_ARCH_KASAN if MMU && !XIP_KERNEL
73 select HAVE_ARCH_MMAP_RND_BITS if MMU
74 select HAVE_ARCH_PFN_VALID
75 select HAVE_ARCH_SECCOMP
76 select HAVE_ARCH_SECCOMP_FILTER if AEABI && !OABI_COMPAT
77 select HAVE_ARCH_THREAD_STRUCT_WHITELIST
78 select HAVE_ARCH_TRACEHOOK
79 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARM_LPAE
80 select HAVE_ARM_SMCCC if CPU_V7
81 select HAVE_EBPF_JIT if !CPU_ENDIAN_BE32
82 select HAVE_CONTEXT_TRACKING
83 select HAVE_C_RECORDMCOUNT
84 select HAVE_DEBUG_KMEMLEAK if !XIP_KERNEL
85 select HAVE_DMA_CONTIGUOUS if MMU
86 select HAVE_DYNAMIC_FTRACE if !XIP_KERNEL && !CPU_ENDIAN_BE32 && MMU
87 select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
88 select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
89 select HAVE_EXIT_THREAD
90 select HAVE_FAST_GUP if ARM_LPAE
91 select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
92 select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
93 select HAVE_FUNCTION_TRACER if !XIP_KERNEL
94 select HAVE_GCC_PLUGINS
95 select HAVE_HW_BREAKPOINT if PERF_EVENTS && (CPU_V6 || CPU_V6K || CPU_V7)
96 select HAVE_IRQ_TIME_ACCOUNTING
97 select HAVE_KERNEL_GZIP
98 select HAVE_KERNEL_LZ4
99 select HAVE_KERNEL_LZMA
100 select HAVE_KERNEL_LZO
101 select HAVE_KERNEL_XZ
102 select HAVE_KPROBES if !XIP_KERNEL && !CPU_ENDIAN_BE32 && !CPU_V7M
103 select HAVE_KRETPROBES if HAVE_KPROBES
104 select HAVE_MOD_ARCH_SPECIFIC
106 select HAVE_OPTPROBES if !THUMB2_KERNEL
107 select HAVE_PERF_EVENTS
108 select HAVE_PERF_REGS
109 select HAVE_PERF_USER_STACK_DUMP
110 select MMU_GATHER_RCU_TABLE_FREE if SMP && ARM_LPAE
111 select HAVE_REGS_AND_STACK_ACCESS_API
113 select HAVE_STACKPROTECTOR
114 select HAVE_SYSCALL_TRACEPOINTS
116 select HAVE_VIRT_CPU_ACCOUNTING_GEN
117 select IRQ_FORCED_THREADING
118 select MODULES_USE_ELF_REL
119 select NEED_DMA_MAP_STATE
120 select OF_EARLY_FLATTREE if OF
122 select OLD_SIGSUSPEND3
123 select PCI_SYSCALL if PCI
124 select PERF_USE_VMALLOC
127 select SYS_SUPPORTS_APM_EMULATION
128 # Above selects are sorted alphabetically; please add new ones
129 # according to that. Thanks.
131 The ARM series is a line of low-power-consumption RISC chip designs
132 licensed by ARM Ltd and targeted at embedded applications and
133 handhelds such as the Compaq IPAQ. ARM-based PCs are no longer
134 manufactured, but legacy ARM-based PC hardware remains popular in
135 Europe. There is an ARM Linux project with a web page at
136 <http://www.arm.linux.org.uk/>.
138 config ARM_HAS_SG_CHAIN
141 config ARM_DMA_USE_IOMMU
143 select ARM_HAS_SG_CHAIN
144 select NEED_SG_DMA_LENGTH
148 config ARM_DMA_IOMMU_ALIGNMENT
149 int "Maximum PAGE_SIZE order of alignment for DMA IOMMU buffers"
153 DMA mapping framework by default aligns all buffers to the smallest
154 PAGE_SIZE order which is greater than or equal to the requested buffer
155 size. This works well for buffers up to a few hundreds kilobytes, but
156 for larger buffers it just a waste of address space. Drivers which has
157 relatively small addressing window (like 64Mib) might run out of
158 virtual space with just a few allocations.
160 With this parameter you can specify the maximum PAGE_SIZE order for
161 DMA IOMMU buffers. Larger buffers will be aligned only to this
162 specified order. The order is expressed as a power of two multiplied
167 config SYS_SUPPORTS_APM_EMULATION
172 select GENERIC_ALLOCATOR
183 config STACKTRACE_SUPPORT
187 config LOCKDEP_SUPPORT
191 config TRACE_IRQFLAGS_SUPPORT
195 config ARCH_HAS_ILOG2_U32
198 config ARCH_HAS_ILOG2_U64
201 config ARCH_HAS_BANDGAP
204 config FIX_EARLYCON_MEM
207 config GENERIC_HWEIGHT
211 config GENERIC_CALIBRATE_DELAY
215 config ARCH_MAY_HAVE_PC_FDC
218 config ARCH_SUPPORTS_UPROBES
221 config ARCH_HAS_DMA_SET_COHERENT_MASK
224 config GENERIC_ISA_DMA
230 config NEED_RET_TO_USER
236 config ARM_PATCH_PHYS_VIRT
237 bool "Patch physical to virtual translations at runtime" if EMBEDDED
239 depends on !XIP_KERNEL && MMU
241 Patch phys-to-virt and virt-to-phys translation functions at
242 boot and module load time according to the position of the
243 kernel in system memory.
245 This can only be used with non-XIP MMU kernels where the base
246 of physical memory is at a 2 MiB boundary.
248 Only disable this option if you know that you do not require
249 this feature (eg, building a kernel for a single machine) and
250 you need to shrink the kernel to the minimal size.
252 config NEED_MACH_IO_H
255 Select this when mach/io.h is required to provide special
256 definitions for this platform. The need for mach/io.h should
257 be avoided when possible.
259 config NEED_MACH_MEMORY_H
262 Select this when mach/memory.h is required to provide special
263 definitions for this platform. The need for mach/memory.h should
264 be avoided when possible.
267 hex "Physical address of main memory" if MMU
268 depends on !ARM_PATCH_PHYS_VIRT
269 default DRAM_BASE if !MMU
270 default 0x00000000 if ARCH_FOOTBRIDGE
271 default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
272 default 0x20000000 if ARCH_S5PV210
273 default 0xc0000000 if ARCH_SA1100
275 Please provide the physical address corresponding to the
276 location of main memory in your system.
282 config PGTABLE_LEVELS
284 default 3 if ARM_LPAE
290 bool "MMU-based Paged Memory Management Support"
293 Select if you want MMU-based virtualised addressing space
294 support by paged memory management. If unsure, say 'Y'.
296 config ARCH_MMAP_RND_BITS_MIN
299 config ARCH_MMAP_RND_BITS_MAX
300 default 14 if PAGE_OFFSET=0x40000000
301 default 15 if PAGE_OFFSET=0x80000000
305 # The "ARM system type" choice list is ordered alphabetically by option
306 # text. Please add new entries in the option alphabetic order.
309 prompt "ARM system type"
310 default ARM_SINGLE_ARMV7M if !MMU
311 default ARCH_MULTIPLATFORM if MMU
313 config ARCH_MULTIPLATFORM
314 bool "Allow multiple platforms to be selected"
316 select ARCH_FLATMEM_ENABLE
317 select ARCH_SPARSEMEM_ENABLE
318 select ARCH_SELECT_MEMORY_MODEL
319 select ARM_HAS_SG_CHAIN
320 select ARM_PATCH_PHYS_VIRT
324 select GENERIC_IRQ_MULTI_HANDLER
326 select PCI_DOMAINS_GENERIC if PCI
330 config ARM_SINGLE_ARMV7M
331 bool "ARMv7-M based platforms (Cortex-M0/M3/M4)"
344 select ARCH_SPARSEMEM_ENABLE
346 imply ARM_PATCH_PHYS_VIRT
348 select GENERIC_IRQ_MULTI_HANDLER
353 select HAVE_LEGACY_CLK
355 This enables support for the Cirrus EP93xx series of CPUs.
357 config ARCH_FOOTBRIDGE
361 select NEED_MACH_IO_H if !MMU
362 select NEED_MACH_MEMORY_H
364 Support for systems based on the DC21285 companion chip
365 ("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
373 select NEED_RET_TO_USER
377 Support for Intel's 80219 and IOP32X (XScale) family of
383 select ARCH_HAS_DMA_SET_COHERENT_MASK
384 select ARCH_SUPPORTS_BIG_ENDIAN
386 select DMABOUNCE if PCI
387 select GENERIC_IRQ_MULTI_HANDLER
393 # With the new PCI driver this is not needed
394 select NEED_MACH_IO_H if IXP4XX_PCI_LEGACY
395 select USB_EHCI_BIG_ENDIAN_DESC
396 select USB_EHCI_BIG_ENDIAN_MMIO
398 Support for Intel's IXP4XX (XScale) family of processors.
403 select GENERIC_IRQ_MULTI_HANDLER
409 select PLAT_ORION_LEGACY
411 select PM_GENERIC_DOMAINS if PM
413 Support for the Marvell Dove SoC 88AP510
416 bool "PXA2xx/PXA3xx-based"
419 select ARM_CPU_SUSPEND if PM
425 select CPU_XSCALE if !CPU_XSC3
426 select GENERIC_IRQ_MULTI_HANDLER
433 Support for Intel/Marvell's PXA2xx/PXA3xx processor line.
439 select ARCH_MAY_HAVE_PC_FDC
440 select ARCH_SPARSEMEM_ENABLE
441 select ARM_HAS_SG_CHAIN
444 select HAVE_PATA_PLATFORM
446 select LEGACY_TIMER_TICK
447 select NEED_MACH_IO_H
448 select NEED_MACH_MEMORY_H
451 On the Acorn Risc-PC, Linux can support the internal IDE disk and
452 CD-ROM interface, serial and parallel port, and the floppy drive.
457 select ARCH_SPARSEMEM_ENABLE
460 select TIMER_OF if OF
464 select GENERIC_IRQ_MULTI_HANDLER
468 select NEED_MACH_MEMORY_H
471 Support for StrongARM 11x0 based boards.
474 bool "Samsung S3C24XX SoCs"
476 select CLKSRC_SAMSUNG_PWM
479 select GENERIC_IRQ_MULTI_HANDLER
480 select HAVE_S3C2410_I2C if I2C
481 select HAVE_S3C_RTC if RTC_CLASS
482 select NEED_MACH_IO_H
483 select S3C2410_WATCHDOG
488 Samsung S3C2410, S3C2412, S3C2413, S3C2416, S3C2440, S3C2442, S3C2443
489 and S3C2450 SoCs based systems, such as the Simtec Electronics BAST
490 (<http://www.simtec.co.uk/products/EB110ITX/>), the IPAQ 1940 or the
491 Samsung SMDK2410 development board (and derivatives).
498 select GENERIC_IRQ_CHIP
499 select GENERIC_IRQ_MULTI_HANDLER
501 select HAVE_LEGACY_CLK
503 select NEED_MACH_IO_H if PCCARD
504 select NEED_MACH_MEMORY_H
507 Support for older TI OMAP1 (omap7xx, omap15xx or omap16xx)
511 menu "Multiple platform selection"
512 depends on ARCH_MULTIPLATFORM
514 comment "CPU Core family selection"
517 bool "ARMv4 based platforms (FA526)"
518 depends on !ARCH_MULTI_V6_V7
519 select ARCH_MULTI_V4_V5
522 config ARCH_MULTI_V4T
523 bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
524 depends on !ARCH_MULTI_V6_V7
525 select ARCH_MULTI_V4_V5
526 select CPU_ARM920T if !(CPU_ARM7TDMI || CPU_ARM720T || \
527 CPU_ARM740T || CPU_ARM9TDMI || CPU_ARM922T || \
528 CPU_ARM925T || CPU_ARM940T)
531 bool "ARMv5 based platforms (ARM926T, XSCALE, PJ1, ...)"
532 depends on !ARCH_MULTI_V6_V7
533 select ARCH_MULTI_V4_V5
534 select CPU_ARM926T if !(CPU_ARM946E || CPU_ARM1020 || \
535 CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || \
536 CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_FEROCEON)
538 config ARCH_MULTI_V4_V5
542 bool "ARMv6 based platforms (ARM11)"
543 select ARCH_MULTI_V6_V7
547 bool "ARMv7 based platforms (Cortex-A, PJ4, Scorpion, Krait)"
549 select ARCH_MULTI_V6_V7
553 config ARCH_MULTI_V6_V7
555 select MIGHT_HAVE_CACHE_L2X0
557 config ARCH_MULTI_CPU_AUTO
558 def_bool !(ARCH_MULTI_V4 || ARCH_MULTI_V4T || ARCH_MULTI_V6_V7)
564 bool "Dummy Virtual Machine"
565 depends on ARCH_MULTI_V7
568 select ARM_GIC_V2M if PCI
570 select ARM_GIC_V3_ITS if PCI
572 select HAVE_ARM_ARCH_TIMER
573 select ARCH_SUPPORTS_BIG_ENDIAN
576 # This is sorted alphabetically by mach-* pathname. However, plat-*
577 # Kconfigs may be included either alphabetically (according to the
578 # plat- suffix) or along side the corresponding mach-* source.
580 source "arch/arm/mach-actions/Kconfig"
582 source "arch/arm/mach-alpine/Kconfig"
584 source "arch/arm/mach-artpec/Kconfig"
586 source "arch/arm/mach-asm9260/Kconfig"
588 source "arch/arm/mach-aspeed/Kconfig"
590 source "arch/arm/mach-at91/Kconfig"
592 source "arch/arm/mach-axxia/Kconfig"
594 source "arch/arm/mach-bcm/Kconfig"
596 source "arch/arm/mach-berlin/Kconfig"
598 source "arch/arm/mach-clps711x/Kconfig"
600 source "arch/arm/mach-cns3xxx/Kconfig"
602 source "arch/arm/mach-davinci/Kconfig"
604 source "arch/arm/mach-digicolor/Kconfig"
606 source "arch/arm/mach-dove/Kconfig"
608 source "arch/arm/mach-ep93xx/Kconfig"
610 source "arch/arm/mach-exynos/Kconfig"
612 source "arch/arm/mach-footbridge/Kconfig"
614 source "arch/arm/mach-gemini/Kconfig"
616 source "arch/arm/mach-highbank/Kconfig"
618 source "arch/arm/mach-hisi/Kconfig"
620 source "arch/arm/mach-imx/Kconfig"
622 source "arch/arm/mach-integrator/Kconfig"
624 source "arch/arm/mach-iop32x/Kconfig"
626 source "arch/arm/mach-ixp4xx/Kconfig"
628 source "arch/arm/mach-keystone/Kconfig"
630 source "arch/arm/mach-lpc32xx/Kconfig"
632 source "arch/arm/mach-mediatek/Kconfig"
634 source "arch/arm/mach-meson/Kconfig"
636 source "arch/arm/mach-milbeaut/Kconfig"
638 source "arch/arm/mach-mmp/Kconfig"
640 source "arch/arm/mach-moxart/Kconfig"
642 source "arch/arm/mach-mstar/Kconfig"
644 source "arch/arm/mach-mv78xx0/Kconfig"
646 source "arch/arm/mach-mvebu/Kconfig"
648 source "arch/arm/mach-mxs/Kconfig"
650 source "arch/arm/mach-nomadik/Kconfig"
652 source "arch/arm/mach-npcm/Kconfig"
654 source "arch/arm/mach-nspire/Kconfig"
656 source "arch/arm/plat-omap/Kconfig"
658 source "arch/arm/mach-omap1/Kconfig"
660 source "arch/arm/mach-omap2/Kconfig"
662 source "arch/arm/mach-orion5x/Kconfig"
664 source "arch/arm/mach-oxnas/Kconfig"
666 source "arch/arm/mach-pxa/Kconfig"
667 source "arch/arm/plat-pxa/Kconfig"
669 source "arch/arm/mach-qcom/Kconfig"
671 source "arch/arm/mach-rda/Kconfig"
673 source "arch/arm/mach-realtek/Kconfig"
675 source "arch/arm/mach-realview/Kconfig"
677 source "arch/arm/mach-rockchip/Kconfig"
679 source "arch/arm/mach-s3c/Kconfig"
681 source "arch/arm/mach-s5pv210/Kconfig"
683 source "arch/arm/mach-sa1100/Kconfig"
685 source "arch/arm/mach-shmobile/Kconfig"
687 source "arch/arm/mach-socfpga/Kconfig"
689 source "arch/arm/mach-spear/Kconfig"
691 source "arch/arm/mach-sti/Kconfig"
693 source "arch/arm/mach-stm32/Kconfig"
695 source "arch/arm/mach-sunxi/Kconfig"
697 source "arch/arm/mach-tegra/Kconfig"
699 source "arch/arm/mach-uniphier/Kconfig"
701 source "arch/arm/mach-ux500/Kconfig"
703 source "arch/arm/mach-versatile/Kconfig"
705 source "arch/arm/mach-vexpress/Kconfig"
707 source "arch/arm/mach-vt8500/Kconfig"
709 source "arch/arm/mach-zynq/Kconfig"
711 # ARMv7-M architecture
713 bool "NXP LPC18xx/LPC43xx"
714 depends on ARM_SINGLE_ARMV7M
715 select ARCH_HAS_RESET_CONTROLLER
717 select CLKSRC_LPC32XX
720 Support for NXP's LPC18xx Cortex-M3 and LPC43xx Cortex-M4
721 high performance microcontrollers.
724 bool "ARM MPS2 platform"
725 depends on ARM_SINGLE_ARMV7M
729 Support for Cortex-M Prototyping System (or V2M-MPS2) which comes
730 with a range of available cores like Cortex-M3/M4/M7.
732 Please, note that depends which Application Note is used memory map
733 for the platform may vary, so adjustment of RAM base might be needed.
735 # Definitions to make life easier
746 select GENERIC_IRQ_CHIP
749 config PLAT_ORION_LEGACY
756 config PLAT_VERSATILE
759 source "arch/arm/mm/Kconfig"
762 bool "Enable iWMMXt support"
763 depends on CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_PJ4 || CPU_PJ4B
764 default y if PXA27x || PXA3xx || ARCH_MMP || CPU_PJ4 || CPU_PJ4B
766 Enable support for iWMMXt context switching at run time if
767 running on a CPU that supports it.
770 source "arch/arm/Kconfig-nommu"
773 config PJ4B_ERRATA_4742
774 bool "PJ4B Errata 4742: IDLE Wake Up Commands can Cause the CPU Core to Cease Operation"
775 depends on CPU_PJ4B && MACH_ARMADA_370
778 When coming out of either a Wait for Interrupt (WFI) or a Wait for
779 Event (WFE) IDLE states, a specific timing sensitivity exists between
780 the retiring WFI/WFE instructions and the newly issued subsequent
781 instructions. This sensitivity can result in a CPU hang scenario.
783 The software must insert either a Data Synchronization Barrier (DSB)
784 or Data Memory Barrier (DMB) command immediately after the WFI/WFE
787 config ARM_ERRATA_326103
788 bool "ARM errata: FSR write bit incorrect on a SWP to read-only memory"
791 Executing a SWP instruction to read-only memory does not set bit 11
792 of the FSR on the ARM 1136 prior to r1p0. This causes the kernel to
793 treat the access as a read, preventing a COW from occurring and
794 causing the faulting task to livelock.
796 config ARM_ERRATA_411920
797 bool "ARM errata: Invalidation of the Instruction Cache operation can fail"
798 depends on CPU_V6 || CPU_V6K
800 Invalidation of the Instruction Cache operation can
801 fail. This erratum is present in 1136 (before r1p4), 1156 and 1176.
802 It does not affect the MPCore. This option enables the ARM Ltd.
803 recommended workaround.
805 config ARM_ERRATA_430973
806 bool "ARM errata: Stale prediction on replaced interworking branch"
809 This option enables the workaround for the 430973 Cortex-A8
810 r1p* erratum. If a code sequence containing an ARM/Thumb
811 interworking branch is replaced with another code sequence at the
812 same virtual address, whether due to self-modifying code or virtual
813 to physical address re-mapping, Cortex-A8 does not recover from the
814 stale interworking branch prediction. This results in Cortex-A8
815 executing the new code sequence in the incorrect ARM or Thumb state.
816 The workaround enables the BTB/BTAC operations by setting ACTLR.IBE
817 and also flushes the branch target cache at every context switch.
818 Note that setting specific bits in the ACTLR register may not be
819 available in non-secure mode.
821 config ARM_ERRATA_458693
822 bool "ARM errata: Processor deadlock when a false hazard is created"
824 depends on !ARCH_MULTIPLATFORM
826 This option enables the workaround for the 458693 Cortex-A8 (r2p0)
827 erratum. For very specific sequences of memory operations, it is
828 possible for a hazard condition intended for a cache line to instead
829 be incorrectly associated with a different cache line. This false
830 hazard might then cause a processor deadlock. The workaround enables
831 the L1 caching of the NEON accesses and disables the PLD instruction
832 in the ACTLR register. Note that setting specific bits in the ACTLR
833 register may not be available in non-secure mode.
835 config ARM_ERRATA_460075
836 bool "ARM errata: Data written to the L2 cache can be overwritten with stale data"
838 depends on !ARCH_MULTIPLATFORM
840 This option enables the workaround for the 460075 Cortex-A8 (r2p0)
841 erratum. Any asynchronous access to the L2 cache may encounter a
842 situation in which recent store transactions to the L2 cache are lost
843 and overwritten with stale memory contents from external memory. The
844 workaround disables the write-allocate mode for the L2 cache via the
845 ACTLR register. Note that setting specific bits in the ACTLR register
846 may not be available in non-secure mode.
848 config ARM_ERRATA_742230
849 bool "ARM errata: DMB operation may be faulty"
850 depends on CPU_V7 && SMP
851 depends on !ARCH_MULTIPLATFORM
853 This option enables the workaround for the 742230 Cortex-A9
854 (r1p0..r2p2) erratum. Under rare circumstances, a DMB instruction
855 between two write operations may not ensure the correct visibility
856 ordering of the two writes. This workaround sets a specific bit in
857 the diagnostic register of the Cortex-A9 which causes the DMB
858 instruction to behave as a DSB, ensuring the correct behaviour of
861 config ARM_ERRATA_742231
862 bool "ARM errata: Incorrect hazard handling in the SCU may lead to data corruption"
863 depends on CPU_V7 && SMP
864 depends on !ARCH_MULTIPLATFORM
866 This option enables the workaround for the 742231 Cortex-A9
867 (r2p0..r2p2) erratum. Under certain conditions, specific to the
868 Cortex-A9 MPCore micro-architecture, two CPUs working in SMP mode,
869 accessing some data located in the same cache line, may get corrupted
870 data due to bad handling of the address hazard when the line gets
871 replaced from one of the CPUs at the same time as another CPU is
872 accessing it. This workaround sets specific bits in the diagnostic
873 register of the Cortex-A9 which reduces the linefill issuing
874 capabilities of the processor.
876 config ARM_ERRATA_643719
877 bool "ARM errata: LoUIS bit field in CLIDR register is incorrect"
878 depends on CPU_V7 && SMP
881 This option enables the workaround for the 643719 Cortex-A9 (prior to
882 r1p0) erratum. On affected cores the LoUIS bit field of the CLIDR
883 register returns zero when it should return one. The workaround
884 corrects this value, ensuring cache maintenance operations which use
885 it behave as intended and avoiding data corruption.
887 config ARM_ERRATA_720789
888 bool "ARM errata: TLBIASIDIS and TLBIMVAIS operations can broadcast a faulty ASID"
891 This option enables the workaround for the 720789 Cortex-A9 (prior to
892 r2p0) erratum. A faulty ASID can be sent to the other CPUs for the
893 broadcasted CP15 TLB maintenance operations TLBIASIDIS and TLBIMVAIS.
894 As a consequence of this erratum, some TLB entries which should be
895 invalidated are not, resulting in an incoherency in the system page
896 tables. The workaround changes the TLB flushing routines to invalidate
897 entries regardless of the ASID.
899 config ARM_ERRATA_743622
900 bool "ARM errata: Faulty hazard checking in the Store Buffer may lead to data corruption"
902 depends on !ARCH_MULTIPLATFORM
904 This option enables the workaround for the 743622 Cortex-A9
905 (r2p*) erratum. Under very rare conditions, a faulty
906 optimisation in the Cortex-A9 Store Buffer may lead to data
907 corruption. This workaround sets a specific bit in the diagnostic
908 register of the Cortex-A9 which disables the Store Buffer
909 optimisation, preventing the defect from occurring. This has no
910 visible impact on the overall performance or power consumption of the
913 config ARM_ERRATA_751472
914 bool "ARM errata: Interrupted ICIALLUIS may prevent completion of broadcasted operation"
916 depends on !ARCH_MULTIPLATFORM
918 This option enables the workaround for the 751472 Cortex-A9 (prior
919 to r3p0) erratum. An interrupted ICIALLUIS operation may prevent the
920 completion of a following broadcasted operation if the second
921 operation is received by a CPU before the ICIALLUIS has completed,
922 potentially leading to corrupted entries in the cache or TLB.
924 config ARM_ERRATA_754322
925 bool "ARM errata: possible faulty MMU translations following an ASID switch"
928 This option enables the workaround for the 754322 Cortex-A9 (r2p*,
929 r3p*) erratum. A speculative memory access may cause a page table walk
930 which starts prior to an ASID switch but completes afterwards. This
931 can populate the micro-TLB with a stale entry which may be hit with
932 the new ASID. This workaround places two dsb instructions in the mm
933 switching code so that no page table walks can cross the ASID switch.
935 config ARM_ERRATA_754327
936 bool "ARM errata: no automatic Store Buffer drain"
937 depends on CPU_V7 && SMP
939 This option enables the workaround for the 754327 Cortex-A9 (prior to
940 r2p0) erratum. The Store Buffer does not have any automatic draining
941 mechanism and therefore a livelock may occur if an external agent
942 continuously polls a memory location waiting to observe an update.
943 This workaround defines cpu_relax() as smp_mb(), preventing correctly
944 written polling loops from denying visibility of updates to memory.
946 config ARM_ERRATA_364296
947 bool "ARM errata: Possible cache data corruption with hit-under-miss enabled"
950 This options enables the workaround for the 364296 ARM1136
951 r0p2 erratum (possible cache data corruption with
952 hit-under-miss enabled). It sets the undocumented bit 31 in
953 the auxiliary control register and the FI bit in the control
954 register, thus disabling hit-under-miss without putting the
955 processor into full low interrupt latency mode. ARM11MPCore
958 config ARM_ERRATA_764369
959 bool "ARM errata: Data cache line maintenance operation by MVA may not succeed"
960 depends on CPU_V7 && SMP
962 This option enables the workaround for erratum 764369
963 affecting Cortex-A9 MPCore with two or more processors (all
964 current revisions). Under certain timing circumstances, a data
965 cache line maintenance operation by MVA targeting an Inner
966 Shareable memory region may fail to proceed up to either the
967 Point of Coherency or to the Point of Unification of the
968 system. This workaround adds a DSB instruction before the
969 relevant cache maintenance functions and sets a specific bit
970 in the diagnostic control register of the SCU.
972 config ARM_ERRATA_775420
973 bool "ARM errata: A data cache maintenance operation which aborts, might lead to deadlock"
976 This option enables the workaround for the 775420 Cortex-A9 (r2p2,
977 r2p6,r2p8,r2p10,r3p0) erratum. In case a data cache maintenance
978 operation aborts with MMU exception, it might cause the processor
979 to deadlock. This workaround puts DSB before executing ISB if
980 an abort may occur on cache maintenance.
982 config ARM_ERRATA_798181
983 bool "ARM errata: TLBI/DSB failure on Cortex-A15"
984 depends on CPU_V7 && SMP
986 On Cortex-A15 (r0p0..r3p2) the TLBI*IS/DSB operations are not
987 adequately shooting down all use of the old entries. This
988 option enables the Linux kernel workaround for this erratum
989 which sends an IPI to the CPUs that are running the same ASID
990 as the one being invalidated.
992 config ARM_ERRATA_773022
993 bool "ARM errata: incorrect instructions may be executed from loop buffer"
996 This option enables the workaround for the 773022 Cortex-A15
997 (up to r0p4) erratum. In certain rare sequences of code, the
998 loop buffer may deliver incorrect instructions. This
999 workaround disables the loop buffer to avoid the erratum.
1001 config ARM_ERRATA_818325_852422
1002 bool "ARM errata: A12: some seqs of opposed cond code instrs => deadlock or corruption"
1005 This option enables the workaround for:
1006 - Cortex-A12 818325: Execution of an UNPREDICTABLE STR or STM
1007 instruction might deadlock. Fixed in r0p1.
1008 - Cortex-A12 852422: Execution of a sequence of instructions might
1009 lead to either a data corruption or a CPU deadlock. Not fixed in
1010 any Cortex-A12 cores yet.
1011 This workaround for all both errata involves setting bit[12] of the
1012 Feature Register. This bit disables an optimisation applied to a
1013 sequence of 2 instructions that use opposing condition codes.
1015 config ARM_ERRATA_821420
1016 bool "ARM errata: A12: sequence of VMOV to core registers might lead to a dead lock"
1019 This option enables the workaround for the 821420 Cortex-A12
1020 (all revs) erratum. In very rare timing conditions, a sequence
1021 of VMOV to Core registers instructions, for which the second
1022 one is in the shadow of a branch or abort, can lead to a
1023 deadlock when the VMOV instructions are issued out-of-order.
1025 config ARM_ERRATA_825619
1026 bool "ARM errata: A12: DMB NSHST/ISHST mixed ... might cause deadlock"
1029 This option enables the workaround for the 825619 Cortex-A12
1030 (all revs) erratum. Within rare timing constraints, executing a
1031 DMB NSHST or DMB ISHST instruction followed by a mix of Cacheable
1032 and Device/Strongly-Ordered loads and stores might cause deadlock
1034 config ARM_ERRATA_857271
1035 bool "ARM errata: A12: CPU might deadlock under some very rare internal conditions"
1038 This option enables the workaround for the 857271 Cortex-A12
1039 (all revs) erratum. Under very rare timing conditions, the CPU might
1040 hang. The workaround is expected to have a < 1% performance impact.
1042 config ARM_ERRATA_852421
1043 bool "ARM errata: A17: DMB ST might fail to create order between stores"
1046 This option enables the workaround for the 852421 Cortex-A17
1047 (r1p0, r1p1, r1p2) erratum. Under very rare timing conditions,
1048 execution of a DMB ST instruction might fail to properly order
1049 stores from GroupA and stores from GroupB.
1051 config ARM_ERRATA_852423
1052 bool "ARM errata: A17: some seqs of opposed cond code instrs => deadlock or corruption"
1055 This option enables the workaround for:
1056 - Cortex-A17 852423: Execution of a sequence of instructions might
1057 lead to either a data corruption or a CPU deadlock. Not fixed in
1058 any Cortex-A17 cores yet.
1059 This is identical to Cortex-A12 erratum 852422. It is a separate
1060 config option from the A12 erratum due to the way errata are checked
1063 config ARM_ERRATA_857272
1064 bool "ARM errata: A17: CPU might deadlock under some very rare internal conditions"
1067 This option enables the workaround for the 857272 Cortex-A17 erratum.
1068 This erratum is not known to be fixed in any A17 revision.
1069 This is identical to Cortex-A12 erratum 857271. It is a separate
1070 config option from the A12 erratum due to the way errata are checked
1075 source "arch/arm/common/Kconfig"
1082 Find out whether you have ISA slots on your motherboard. ISA is the
1083 name of a bus system, i.e. the way the CPU talks to the other stuff
1084 inside your box. Other bus systems are PCI, EISA, MicroChannel
1085 (MCA) or VESA. ISA is an older system, now being displaced by PCI;
1086 newer boards don't support it. If you have ISA, say Y, otherwise N.
1088 # Select ISA DMA controller support
1093 # Select ISA DMA interface
1097 config PCI_NANOENGINE
1098 bool "BSE nanoEngine PCI support"
1099 depends on SA1100_NANOENGINE
1101 Enable PCI on the BSE nanoEngine board.
1103 config ARM_ERRATA_814220
1104 bool "ARM errata: Cache maintenance by set/way operations can execute out of order"
1107 The v7 ARM states that all cache and branch predictor maintenance
1108 operations that do not specify an address execute, relative to
1109 each other, in program order.
1110 However, because of this erratum, an L2 set/way cache maintenance
1111 operation can overtake an L1 set/way cache maintenance operation.
1112 This ERRATA only affected the Cortex-A7 and present in r0p2, r0p3,
1117 menu "Kernel Features"
1122 This option should be selected by machines which have an SMP-
1125 The only effect of this option is to make the SMP-related
1126 options available to the user for configuration.
1129 bool "Symmetric Multi-Processing"
1130 depends on CPU_V6K || CPU_V7
1132 depends on MMU || ARM_MPU
1135 This enables support for systems with more than one CPU. If you have
1136 a system with only one CPU, say N. If you have a system with more
1137 than one CPU, say Y.
1139 If you say N here, the kernel will run on uni- and multiprocessor
1140 machines, but will use only one CPU of a multiprocessor machine. If
1141 you say Y here, the kernel will run on many, but not all,
1142 uniprocessor machines. On a uniprocessor machine, the kernel
1143 will run faster if you say N here.
1145 See also <file:Documentation/x86/i386/IO-APIC.rst>,
1146 <file:Documentation/admin-guide/lockup-watchdogs.rst> and the SMP-HOWTO available at
1147 <http://tldp.org/HOWTO/SMP-HOWTO.html>.
1149 If you don't know what to do here, say N.
1152 bool "Allow booting SMP kernel on uniprocessor systems"
1153 depends on SMP && !XIP_KERNEL && MMU
1156 SMP kernels contain instructions which fail on non-SMP processors.
1157 Enabling this option allows the kernel to modify itself to make
1158 these instructions safe. Disabling it allows about 1K of space
1161 If you don't know what to do here, say Y.
1163 config ARM_CPU_TOPOLOGY
1164 bool "Support cpu topology definition"
1165 depends on SMP && CPU_V7
1168 Support ARM cpu topology definition. The MPIDR register defines
1169 affinity between processors which is then used to describe the cpu
1170 topology of an ARM System.
1173 bool "Multi-core scheduler support"
1174 depends on ARM_CPU_TOPOLOGY
1176 Multi-core scheduler support improves the CPU scheduler's decision
1177 making when dealing with multi-core CPU chips at a cost of slightly
1178 increased overhead in some places. If unsure say N here.
1181 bool "SMT scheduler support"
1182 depends on ARM_CPU_TOPOLOGY
1184 Improves the CPU scheduler's decision making when dealing with
1185 MultiThreading at a cost of slightly increased overhead in some
1186 places. If unsure say N here.
1191 This option enables support for the ARM snoop control unit
1193 config HAVE_ARM_ARCH_TIMER
1194 bool "Architected timer support"
1196 select ARM_ARCH_TIMER
1198 This option enables support for the ARM architected timer
1203 This options enables support for the ARM timer and watchdog unit
1206 bool "Multi-Cluster Power Management"
1207 depends on CPU_V7 && SMP
1209 This option provides the common power management infrastructure
1210 for (multi-)cluster based systems, such as big.LITTLE based
1213 config MCPM_QUAD_CLUSTER
1217 To avoid wasting resources unnecessarily, MCPM only supports up
1218 to 2 clusters by default.
1219 Platforms with 3 or 4 clusters that use MCPM must select this
1220 option to allow the additional clusters to be managed.
1223 bool "big.LITTLE support (Experimental)"
1224 depends on CPU_V7 && SMP
1227 This option enables support selections for the big.LITTLE
1228 system architecture.
1231 bool "big.LITTLE switcher support"
1232 depends on BIG_LITTLE && MCPM && HOTPLUG_CPU && ARM_GIC
1235 The big.LITTLE "switcher" provides the core functionality to
1236 transparently handle transition between a cluster of A15's
1237 and a cluster of A7's in a big.LITTLE system.
1239 config BL_SWITCHER_DUMMY_IF
1240 tristate "Simple big.LITTLE switcher user interface"
1241 depends on BL_SWITCHER && DEBUG_KERNEL
1243 This is a simple and dummy char dev interface to control
1244 the big.LITTLE switcher core code. It is meant for
1245 debugging purposes only.
1248 prompt "Memory split"
1252 Select the desired split between kernel and user memory.
1254 If you are not absolutely sure what you are doing, leave this
1258 bool "3G/1G user/kernel split"
1259 config VMSPLIT_3G_OPT
1260 depends on !ARM_LPAE
1261 bool "3G/1G user/kernel split (for full 1G low memory)"
1263 bool "2G/2G user/kernel split"
1265 bool "1G/3G user/kernel split"
1270 default PHYS_OFFSET if !MMU
1271 default 0x40000000 if VMSPLIT_1G
1272 default 0x80000000 if VMSPLIT_2G
1273 default 0xB0000000 if VMSPLIT_3G_OPT
1276 config KASAN_SHADOW_OFFSET
1279 default 0x1f000000 if PAGE_OFFSET=0x40000000
1280 default 0x5f000000 if PAGE_OFFSET=0x80000000
1281 default 0x9f000000 if PAGE_OFFSET=0xC0000000
1282 default 0x8f000000 if PAGE_OFFSET=0xB0000000
1286 int "Maximum number of CPUs (2-32)"
1287 range 2 16 if DEBUG_KMAP_LOCAL
1288 range 2 32 if !DEBUG_KMAP_LOCAL
1292 The maximum number of CPUs that the kernel can support.
1293 Up to 32 CPUs can be supported, or up to 16 if kmap_local()
1294 debugging is enabled, which uses half of the per-CPU fixmap
1295 slots as guard regions.
1298 bool "Support for hot-pluggable CPUs"
1300 select GENERIC_IRQ_MIGRATION
1302 Say Y here to experiment with turning CPUs off and on. CPUs
1303 can be controlled through /sys/devices/system/cpu.
1306 bool "Support for the ARM Power State Coordination Interface (PSCI)"
1307 depends on HAVE_ARM_SMCCC
1310 Say Y here if you want Linux to communicate with system firmware
1311 implementing the PSCI specification for CPU-centric power
1312 management operations described in ARM document number ARM DEN
1313 0022A ("Power State Coordination Interface System Software on
1316 # The GPIO number here must be sorted by descending number. In case of
1317 # a multiplatform kernel, we just want the highest value required by the
1318 # selected platforms.
1321 default 2048 if ARCH_INTEL_SOCFPGA
1322 default 1024 if ARCH_BRCMSTB || ARCH_RENESAS || ARCH_TEGRA || \
1323 ARCH_ZYNQ || ARCH_ASPEED
1324 default 512 if ARCH_EXYNOS || ARCH_KEYSTONE || SOC_OMAP5 || \
1325 SOC_DRA7XX || ARCH_S3C24XX || ARCH_S3C64XX || ARCH_S5PV210
1326 default 416 if ARCH_SUNXI
1327 default 392 if ARCH_U8500
1328 default 352 if ARCH_VT8500
1329 default 288 if ARCH_ROCKCHIP
1330 default 264 if MACH_H4700
1333 Maximum number of GPIOs in the system.
1335 If unsure, leave the default value.
1339 default 128 if SOC_AT91RM9200
1343 depends on HZ_FIXED = 0
1344 prompt "Timer frequency"
1368 default HZ_FIXED if HZ_FIXED != 0
1369 default 100 if HZ_100
1370 default 200 if HZ_200
1371 default 250 if HZ_250
1372 default 300 if HZ_300
1373 default 500 if HZ_500
1377 def_bool HIGH_RES_TIMERS
1379 config THUMB2_KERNEL
1380 bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
1381 depends on (CPU_V7 || CPU_V7M) && !CPU_V6 && !CPU_V6K
1382 default y if CPU_THUMBONLY
1385 By enabling this option, the kernel will be compiled in
1390 config ARM_PATCH_IDIV
1391 bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
1392 depends on CPU_32v7 && !XIP_KERNEL
1395 The ARM compiler inserts calls to __aeabi_idiv() and
1396 __aeabi_uidiv() when it needs to perform division on signed
1397 and unsigned integers. Some v7 CPUs have support for the sdiv
1398 and udiv instructions that can be used to implement those
1401 Enabling this option allows the kernel to modify itself to
1402 replace the first two instructions of these library functions
1403 with the sdiv or udiv plus "bx lr" instructions when the CPU
1404 it is running on supports them. Typically this will be faster
1405 and less power intensive than running the original library
1406 code to do integer division.
1409 bool "Use the ARM EABI to compile the kernel" if !CPU_V7 && \
1410 !CPU_V7M && !CPU_V6 && !CPU_V6K && !CC_IS_CLANG
1411 default CPU_V7 || CPU_V7M || CPU_V6 || CPU_V6K || CC_IS_CLANG
1413 This option allows for the kernel to be compiled using the latest
1414 ARM ABI (aka EABI). This is only useful if you are using a user
1415 space environment that is also compiled with EABI.
1417 Since there are major incompatibilities between the legacy ABI and
1418 EABI, especially with regard to structure member alignment, this
1419 option also changes the kernel syscall calling convention to
1420 disambiguate both ABIs and allow for backward compatibility support
1421 (selected with CONFIG_OABI_COMPAT).
1423 To use this you need GCC version 4.0.0 or later.
1426 bool "Allow old ABI binaries to run with this kernel (EXPERIMENTAL)"
1427 depends on AEABI && !THUMB2_KERNEL
1429 This option preserves the old syscall interface along with the
1430 new (ARM EABI) one. It also provides a compatibility layer to
1431 intercept syscalls that have structure arguments which layout
1432 in memory differs between the legacy ABI and the new ARM EABI
1433 (only for non "thumb" binaries). This option adds a tiny
1434 overhead to all syscalls and produces a slightly larger kernel.
1436 The seccomp filter system will not be available when this is
1437 selected, since there is no way yet to sensibly distinguish
1438 between calling conventions during filtering.
1440 If you know you'll be using only pure EABI user space then you
1441 can say N here. If this option is not selected and you attempt
1442 to execute a legacy ABI binary then the result will be
1443 UNPREDICTABLE (in fact it can be predicted that it won't work
1444 at all). If in doubt say N.
1446 config ARCH_SELECT_MEMORY_MODEL
1449 config ARCH_FLATMEM_ENABLE
1452 config ARCH_SPARSEMEM_ENABLE
1454 select SPARSEMEM_STATIC if SPARSEMEM
1457 bool "High Memory Support"
1461 The address space of ARM processors is only 4 Gigabytes large
1462 and it has to accommodate user address space, kernel address
1463 space as well as some memory mapped IO. That means that, if you
1464 have a large amount of physical memory and/or IO, not all of the
1465 memory can be "permanently mapped" by the kernel. The physical
1466 memory that is not permanently mapped is called "high memory".
1468 Depending on the selected kernel/user memory split, minimum
1469 vmalloc space and actual amount of RAM, you may not need this
1470 option which should result in a slightly faster kernel.
1475 bool "Allocate 2nd-level pagetables from highmem" if EXPERT
1479 The VM uses one page of physical memory for each page table.
1480 For systems with a lot of processes, this can use a lot of
1481 precious low memory, eventually leading to low memory being
1482 consumed by page tables. Setting this option will allow
1483 user-space 2nd level page tables to reside in high memory.
1485 config CPU_SW_DOMAIN_PAN
1486 bool "Enable use of CPU domains to implement privileged no-access"
1487 depends on MMU && !ARM_LPAE
1490 Increase kernel security by ensuring that normal kernel accesses
1491 are unable to access userspace addresses. This can help prevent
1492 use-after-free bugs becoming an exploitable privilege escalation
1493 by ensuring that magic values (such as LIST_POISON) will always
1494 fault when dereferenced.
1496 CPUs with low-vector mappings use a best-efforts implementation.
1497 Their lower 1MB needs to remain accessible for the vectors, but
1498 the remainder of userspace will become appropriately inaccessible.
1500 config HW_PERF_EVENTS
1504 config ARCH_WANT_GENERAL_HUGETLB
1507 config ARM_MODULE_PLTS
1508 bool "Use PLTs to allow module memory to spill over into vmalloc area"
1512 Allocate PLTs when loading modules so that jumps and calls whose
1513 targets are too far away for their relative offsets to be encoded
1514 in the instructions themselves can be bounced via veneers in the
1515 module's PLT. This allows modules to be allocated in the generic
1516 vmalloc area after the dedicated module memory area has been
1517 exhausted. The modules will use slightly more memory, but after
1518 rounding up to page size, the actual memory footprint is usually
1521 Disabling this is usually safe for small single-platform
1522 configurations. If unsure, say y.
1524 config FORCE_MAX_ZONEORDER
1525 int "Maximum zone order"
1526 default "12" if SOC_AM33XX
1527 default "9" if SA1111
1530 The kernel memory allocator divides physically contiguous memory
1531 blocks into "zones", where each zone is a power of two number of
1532 pages. This option selects the largest power of two that the kernel
1533 keeps in the memory allocator. If you need to allocate very large
1534 blocks of physically contiguous memory, then you may need to
1535 increase this value.
1537 This config option is actually maximum order plus one. For example,
1538 a value of 11 means that the largest free memory block is 2^10 pages.
1540 config ALIGNMENT_TRAP
1541 def_bool CPU_CP15_MMU
1542 select HAVE_PROC_CPU if PROC_FS
1544 ARM processors cannot fetch/store information which is not
1545 naturally aligned on the bus, i.e., a 4 byte fetch must start at an
1546 address divisible by 4. On 32-bit ARM processors, these non-aligned
1547 fetch/store instructions will be emulated in software if you say
1548 here, which has a severe performance impact. This is necessary for
1549 correct operation of some network protocols. With an IP-only
1550 configuration it is safe to say N, otherwise say Y.
1552 config UACCESS_WITH_MEMCPY
1553 bool "Use kernel mem{cpy,set}() for {copy_to,clear}_user()"
1555 default y if CPU_FEROCEON
1557 Implement faster copy_to_user and clear_user methods for CPU
1558 cores where a 8-word STM instruction give significantly higher
1559 memory write throughput than a sequence of individual 32bit stores.
1561 A possible side effect is a slight increase in scheduling latency
1562 between threads sharing the same address space if they invoke
1563 such copy operations with large buffers.
1565 However, if the CPU data cache is using a write-allocate mode,
1566 this option is unlikely to provide any performance gain.
1569 bool "Enable paravirtualization code"
1571 This changes the kernel so it can modify itself when it is run
1572 under a hypervisor, potentially improving performance significantly
1573 over full virtualization.
1575 config PARAVIRT_TIME_ACCOUNTING
1576 bool "Paravirtual steal time accounting"
1579 Select this option to enable fine granularity task steal time
1580 accounting. Time spent executing other tasks in parallel with
1581 the current vCPU is discounted from the vCPU power. To account for
1582 that, there can be a small performance impact.
1584 If in doubt, say N here.
1591 bool "Xen guest support on ARM"
1592 depends on ARM && AEABI && OF
1593 depends on CPU_V7 && !CPU_V6
1594 depends on !GENERIC_ATOMIC64
1596 select ARCH_DMA_ADDR_T_64BIT
1602 Say Y if you want to run Linux in a Virtual Machine on Xen on ARM.
1604 config STACKPROTECTOR_PER_TASK
1605 bool "Use a unique stack canary value for each task"
1606 depends on GCC_PLUGINS && STACKPROTECTOR && SMP && !XIP_DEFLATED_DATA
1607 select GCC_PLUGIN_ARM_SSP_PER_TASK
1610 Due to the fact that GCC uses an ordinary symbol reference from
1611 which to load the value of the stack canary, this value can only
1612 change at reboot time on SMP systems, and all tasks running in the
1613 kernel's address space are forced to use the same canary value for
1614 the entire duration that the system is up.
1616 Enable this option to switch to a different method that uses a
1617 different canary value for each task.
1624 bool "Flattened Device Tree support"
1628 Include support for flattened device tree machine descriptions.
1631 bool "Support for the traditional ATAGS boot data passing" if USE_OF
1634 This is the traditional way of passing data to the kernel at boot
1635 time. If you are solely relying on the flattened device tree (or
1636 the ARM_ATAG_DTB_COMPAT option) then you may unselect this option
1637 to remove ATAGS support from your kernel binary. If unsure,
1640 config DEPRECATED_PARAM_STRUCT
1641 bool "Provide old way to pass kernel parameters"
1644 This was deprecated in 2001 and announced to live on for 5 years.
1645 Some old boot loaders still use this way.
1647 # Compressed boot loader in ROM. Yes, we really want to ask about
1648 # TEXT and BSS so we preserve their values in the config files.
1649 config ZBOOT_ROM_TEXT
1650 hex "Compressed ROM boot loader base address"
1653 The physical address at which the ROM-able zImage is to be
1654 placed in the target. Platforms which normally make use of
1655 ROM-able zImage formats normally set this to a suitable
1656 value in their defconfig file.
1658 If ZBOOT_ROM is not enabled, this has no effect.
1660 config ZBOOT_ROM_BSS
1661 hex "Compressed ROM boot loader BSS address"
1664 The base address of an area of read/write memory in the target
1665 for the ROM-able zImage which must be available while the
1666 decompressor is running. It must be large enough to hold the
1667 entire decompressed kernel plus an additional 128 KiB.
1668 Platforms which normally make use of ROM-able zImage formats
1669 normally set this to a suitable value in their defconfig file.
1671 If ZBOOT_ROM is not enabled, this has no effect.
1674 bool "Compressed boot loader in ROM/flash"
1675 depends on ZBOOT_ROM_TEXT != ZBOOT_ROM_BSS
1676 depends on !ARM_APPENDED_DTB && !XIP_KERNEL && !AUTO_ZRELADDR
1678 Say Y here if you intend to execute your compressed kernel image
1679 (zImage) directly from ROM or flash. If unsure, say N.
1681 config ARM_APPENDED_DTB
1682 bool "Use appended device tree blob to zImage (EXPERIMENTAL)"
1685 With this option, the boot code will look for a device tree binary
1686 (DTB) appended to zImage
1687 (e.g. cat zImage <filename>.dtb > zImage_w_dtb).
1689 This is meant as a backward compatibility convenience for those
1690 systems with a bootloader that can't be upgraded to accommodate
1691 the documented boot protocol using a device tree.
1693 Beware that there is very little in terms of protection against
1694 this option being confused by leftover garbage in memory that might
1695 look like a DTB header after a reboot if no actual DTB is appended
1696 to zImage. Do not leave this option active in a production kernel
1697 if you don't intend to always append a DTB. Proper passing of the
1698 location into r2 of a bootloader provided DTB is always preferable
1701 config ARM_ATAG_DTB_COMPAT
1702 bool "Supplement the appended DTB with traditional ATAG information"
1703 depends on ARM_APPENDED_DTB
1705 Some old bootloaders can't be updated to a DTB capable one, yet
1706 they provide ATAGs with memory configuration, the ramdisk address,
1707 the kernel cmdline string, etc. Such information is dynamically
1708 provided by the bootloader and can't always be stored in a static
1709 DTB. To allow a device tree enabled kernel to be used with such
1710 bootloaders, this option allows zImage to extract the information
1711 from the ATAG list and store it at run time into the appended DTB.
1714 prompt "Kernel command line type" if ARM_ATAG_DTB_COMPAT
1715 default ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1717 config ARM_ATAG_DTB_COMPAT_CMDLINE_FROM_BOOTLOADER
1718 bool "Use bootloader kernel arguments if available"
1720 Uses the command-line options passed by the boot loader instead of
1721 the device tree bootargs property. If the boot loader doesn't provide
1722 any, the device tree bootargs property will be used.
1724 config ARM_ATAG_DTB_COMPAT_CMDLINE_EXTEND
1725 bool "Extend with bootloader kernel arguments"
1727 The command-line arguments provided by the boot loader will be
1728 appended to the the device tree bootargs property.
1733 string "Default kernel command string"
1736 On some architectures (e.g. CATS), there is currently no way
1737 for the boot loader to pass arguments to the kernel. For these
1738 architectures, you should supply some command-line options at build
1739 time by entering them here. As a minimum, you should specify the
1740 memory size and the root device (e.g., mem=64M root=/dev/nfs).
1743 prompt "Kernel command line type" if CMDLINE != ""
1744 default CMDLINE_FROM_BOOTLOADER
1747 config CMDLINE_FROM_BOOTLOADER
1748 bool "Use bootloader kernel arguments if available"
1750 Uses the command-line options passed by the boot loader. If
1751 the boot loader doesn't provide any, the default kernel command
1752 string provided in CMDLINE will be used.
1754 config CMDLINE_EXTEND
1755 bool "Extend bootloader kernel arguments"
1757 The command-line arguments provided by the boot loader will be
1758 appended to the default kernel command string.
1760 config CMDLINE_FORCE
1761 bool "Always use the default kernel command string"
1763 Always use the default kernel command string, even if the boot
1764 loader passes other arguments to the kernel.
1765 This is useful if you cannot or don't want to change the
1766 command-line options your boot loader passes to the kernel.
1770 bool "Kernel Execute-In-Place from ROM"
1771 depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
1773 Execute-In-Place allows the kernel to run from non-volatile storage
1774 directly addressable by the CPU, such as NOR flash. This saves RAM
1775 space since the text section of the kernel is not loaded from flash
1776 to RAM. Read-write sections, such as the data section and stack,
1777 are still copied to RAM. The XIP kernel is not compressed since
1778 it has to run directly from flash, so it will take more space to
1779 store it. The flash address used to link the kernel object files,
1780 and for storing it, is configuration dependent. Therefore, if you
1781 say Y here, you must know the proper physical address where to
1782 store the kernel image depending on your own flash memory usage.
1784 Also note that the make target becomes "make xipImage" rather than
1785 "make zImage" or "make Image". The final kernel binary to put in
1786 ROM memory will be arch/arm/boot/xipImage.
1790 config XIP_PHYS_ADDR
1791 hex "XIP Kernel Physical Location"
1792 depends on XIP_KERNEL
1793 default "0x00080000"
1795 This is the physical address in your flash memory the kernel will
1796 be linked for and stored to. This address is dependent on your
1799 config XIP_DEFLATED_DATA
1800 bool "Store kernel .data section compressed in ROM"
1801 depends on XIP_KERNEL
1804 Before the kernel is actually executed, its .data section has to be
1805 copied to RAM from ROM. This option allows for storing that data
1806 in compressed form and decompressed to RAM rather than merely being
1807 copied, saving some precious ROM space. A possible drawback is a
1808 slightly longer boot delay.
1811 bool "Kexec system call (EXPERIMENTAL)"
1812 depends on (!SMP || PM_SLEEP_SMP)
1816 kexec is a system call that implements the ability to shutdown your
1817 current kernel, and to start another kernel. It is like a reboot
1818 but it is independent of the system firmware. And like a reboot
1819 you can start any kernel with it, not just Linux.
1821 It is an ongoing process to be certain the hardware in a machine
1822 is properly shutdown, so do not be surprised if this code does not
1823 initially work for you.
1826 bool "Export atags in procfs"
1827 depends on ATAGS && KEXEC
1830 Should the atags used to boot the kernel be exported in an "atags"
1831 file in procfs. Useful with kexec.
1834 bool "Build kdump crash kernel (EXPERIMENTAL)"
1836 Generate crash dump after being started by kexec. This should
1837 be normally only set in special crash dump kernels which are
1838 loaded in the main kernel with kexec-tools into a specially
1839 reserved region and then later executed after a crash by
1840 kdump/kexec. The crash dump kernel must be compiled to a
1841 memory address not used by the main kernel
1843 For more details see Documentation/admin-guide/kdump/kdump.rst
1845 config AUTO_ZRELADDR
1846 bool "Auto calculation of the decompressed kernel image address"
1848 ZRELADDR is the physical address where the decompressed kernel
1849 image will be placed. If AUTO_ZRELADDR is selected, the address
1850 will be determined at run-time, either by masking the current IP
1851 with 0xf8000000, or, if invalid, from the DTB passed in r2.
1852 This assumes the zImage being placed in the first 128MB from
1859 bool "UEFI runtime support"
1860 depends on OF && !CPU_BIG_ENDIAN && MMU && AUTO_ZRELADDR && !XIP_KERNEL
1862 select EFI_PARAMS_FROM_FDT
1864 select EFI_GENERIC_STUB
1865 select EFI_RUNTIME_WRAPPERS
1867 This option provides support for runtime services provided
1868 by UEFI firmware (such as non-volatile variables, realtime
1869 clock, and platform reset). A UEFI stub is also provided to
1870 allow the kernel to be booted as an EFI application. This
1871 is only useful for kernels that may run on systems that have
1875 bool "Enable support for SMBIOS (DMI) tables"
1879 This enables SMBIOS/DMI feature for systems.
1881 This option is only useful on systems that have UEFI firmware.
1882 However, even with this option, the resultant kernel should
1883 continue to boot on existing non-UEFI platforms.
1885 NOTE: This does *NOT* enable or encourage the use of DMI quirks,
1886 i.e., the the practice of identifying the platform via DMI to
1887 decide whether certain workarounds for buggy hardware and/or
1888 firmware need to be enabled. This would require the DMI subsystem
1889 to be enabled much earlier than we do on ARM, which is non-trivial.
1893 menu "CPU Power Management"
1895 source "drivers/cpufreq/Kconfig"
1897 source "drivers/cpuidle/Kconfig"
1901 menu "Floating point emulation"
1903 comment "At least one emulation must be selected"
1906 bool "NWFPE math emulation"
1907 depends on (!AEABI || OABI_COMPAT) && !THUMB2_KERNEL
1909 Say Y to include the NWFPE floating point emulator in the kernel.
1910 This is necessary to run most binaries. Linux does not currently
1911 support floating point hardware so you need to say Y here even if
1912 your machine has an FPA or floating point co-processor podule.
1914 You may say N here if you are going to load the Acorn FPEmulator
1915 early in the bootup.
1918 bool "Support extended precision"
1919 depends on FPE_NWFPE
1921 Say Y to include 80-bit support in the kernel floating-point
1922 emulator. Otherwise, only 32 and 64-bit support is compiled in.
1923 Note that gcc does not generate 80-bit operations by default,
1924 so in most cases this option only enlarges the size of the
1925 floating point emulator without any good reason.
1927 You almost surely want to say N here.
1930 bool "FastFPE math emulation (EXPERIMENTAL)"
1931 depends on (!AEABI || OABI_COMPAT) && !CPU_32v3
1933 Say Y here to include the FAST floating point emulator in the kernel.
1934 This is an experimental much faster emulator which now also has full
1935 precision for the mantissa. It does not support any exceptions.
1936 It is very simple, and approximately 3-6 times faster than NWFPE.
1938 It should be sufficient for most programs. It may be not suitable
1939 for scientific calculations, but you have to check this for yourself.
1940 If you do not feel you need a faster FP emulation you should better
1944 bool "VFP-format floating point maths"
1945 depends on CPU_V6 || CPU_V6K || CPU_ARM926T || CPU_V7 || CPU_FEROCEON
1947 Say Y to include VFP support code in the kernel. This is needed
1948 if your hardware includes a VFP unit.
1950 Please see <file:Documentation/arm/vfp/release-notes.rst> for
1951 release notes and additional status information.
1953 Say N if your target does not have VFP hardware.
1961 bool "Advanced SIMD (NEON) Extension support"
1962 depends on VFPv3 && CPU_V7
1964 Say Y to include support code for NEON, the ARMv7 Advanced SIMD
1967 config KERNEL_MODE_NEON
1968 bool "Support for NEON in kernel mode"
1969 depends on NEON && AEABI
1971 Say Y to include support for NEON in kernel mode.
1975 menu "Power management options"
1977 source "kernel/power/Kconfig"
1979 config ARCH_SUSPEND_POSSIBLE
1980 depends on CPU_ARM920T || CPU_ARM926T || CPU_FEROCEON || CPU_SA1100 || \
1981 CPU_V6 || CPU_V6K || CPU_V7 || CPU_V7M || CPU_XSC3 || CPU_XSCALE || CPU_MOHAWK
1984 config ARM_CPU_SUSPEND
1985 def_bool PM_SLEEP || BL_SWITCHER || ARM_PSCI_FW
1986 depends on ARCH_SUSPEND_POSSIBLE
1988 config ARCH_HIBERNATION_POSSIBLE
1991 default y if ARCH_SUSPEND_POSSIBLE
1995 source "drivers/firmware/Kconfig"
1998 source "arch/arm/crypto/Kconfig"
2001 source "arch/arm/Kconfig.assembler"