1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI Controller Generic Binding
10 - Mark Brown <broonie@kernel.org>
13 SPI busses can be described with a node for the SPI controller device
14 and a set of child nodes for each SPI slave on the bus. The system SPI
15 controller may be described for use in SPI master mode or in SPI slave mode,
16 but not for both at the same time.
20 pattern: "^spi(@.*|-[0-9a-f])*$"
30 GPIOs used as chip selects.
31 If that property is used, the number of chip selects will be
32 increased automatically with max(cs-gpios, hardware chip selects).
34 So if, for example, the controller has 4 CS lines, and the
35 cs-gpios looks like this
36 cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
38 Then it should be configured so that num_chipselect = 4, with
45 The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
46 or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.
48 There is a special rule set for combining the second flag of an
49 cs-gpio with the optional spi-cs-high flag for SPI slaves.
51 Each table entry defines how the CS pin is to be physically
52 driven (not considering potential gpio inversions by pinmux):
54 device node | cs-gpio | CS pin state active | Note
55 ================+===============+=====================+=====
58 spi-cs-high | ACTIVE_HIGH | H |
59 - | ACTIVE_HIGH | L | 1
60 spi-cs-high | ACTIVE_LOW | H | 2
64 1) Should print a warning about polarity inversion.
65 Here it would be wise to avoid and define the gpio as
67 2) Should print a warning about polarity inversion
68 because ACTIVE_LOW is overridden by spi-cs-high.
69 Should be generally avoided and be replaced by
70 spi-cs-high + ACTIVE_HIGH.
73 $ref: /schemas/types.yaml#/definitions/uint32
75 Total number of chip selects.
78 $ref: /schemas/types.yaml#/definitions/flag
80 The SPI controller acts as a slave, instead of a master.
103 Compatible of the SPI device.
114 Compatible of the SPI device.
123 Chip select used by the device.
126 $ref: /schemas/types.yaml#/definitions/flag
128 The device requires 3-wire mode.
131 $ref: /schemas/types.yaml#/definitions/flag
133 The device requires shifted clock phase (CPHA) mode.
136 $ref: /schemas/types.yaml#/definitions/flag
138 The device requires inverse clock polarity (CPOL) mode.
141 $ref: /schemas/types.yaml#/definitions/flag
143 The device requires the chip select active high.
146 $ref: /schemas/types.yaml#/definitions/flag
148 The device requires the LSB first mode.
151 $ref: /schemas/types.yaml#/definitions/uint32
153 Maximum SPI clocking speed of the device in Hz.
157 Bus width to the SPI bus used for read transfers.
158 If 0 is provided, then no RX will be possible on this device.
159 $ref: /schemas/types.yaml#/definitions/uint32
160 enum: [0, 1, 2, 4, 8]
165 Delay, in microseconds, after a read transfer.
169 Bus width to the SPI bus used for write transfers.
170 If 0 is provided, then no TX will be possible on this device.
171 $ref: /schemas/types.yaml#/definitions/uint32
172 enum: [0, 1, 2, 4, 8]
177 Delay, in microseconds, after a write transfer.
183 additionalProperties: true
188 #address-cells = <1>;
190 compatible = "fsl,imx28-spi";
191 reg = <0x80010000 0x2000>;
193 dmas = <&dma_apbh 0>;
197 compatible = "lg,lg4573";
198 spi-max-frequency = <1000000>;
203 compatible = "bosch,bme680";
204 spi-max-frequency = <100000>;