Documentation/devicetree/bindings/spi/spi-controller.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/spi/spi-controller.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SPI Controller Generic Binding
   8
   9 maintainers:
  10   - Mark Brown <broonie@kernel.org>
  11
  12 description: |
  13   SPI busses can be described with a node for the SPI controller device
  14   and a set of child nodes for each SPI slave on the bus. The system SPI
  15   controller may be described for use in SPI master mode or in SPI slave mode,
  16   but not for both at the same time.
  17
  18 properties:
  19   $nodename:
  20     pattern: "^spi(@.*|-[0-9a-f])*$"
  21
  22   "#address-cells":
  23     const: 1
  24
  25   "#size-cells":
  26     const: 0
  27
  28   cs-gpios:
  29     description: |
  30       GPIOs used as chip selects.
  31       If that property is used, the number of chip selects will be
  32       increased automatically with max(cs-gpios, hardware chip selects).
  33
  34       So if, for example, the controller has 4 CS lines, and the
  35       cs-gpios looks like this
  36         cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
  37
  38       Then it should be configured so that num_chipselect = 4, with
  39       the following mapping
  40         cs0 : &gpio1 0 0
  41         cs1 : native
  42         cs2 : &gpio1 1 0
  43         cs3 : &gpio1 2 0
  44
  45   num-cs:
  46     $ref: /schemas/types.yaml#/definitions/uint32
  47     description:
  48       Total number of chip selects.
  49
  50   spi-slave:
  51     $ref: /schemas/types.yaml#/definitions/flag
  52     description:
  53       The SPI controller acts as a slave, instead of a master.
  54
  55 oneOf:
  56   - required:
  57       - "#address-cells"
  58   - required:
  59       - spi-slave
  60
  61 patternProperties:
  62   "^slave$":
  63     type: object
  64
  65     properties:
  66       compatible:
  67         description:
  68           Compatible of the SPI device.
  69
  70     required:
  71       - compatible
  72
  73   "^.*@[0-9a-f]+$":
  74     type: object
  75
  76     properties:
  77       compatible:
  78         description:
  79           Compatible of the SPI device.
  80
  81       reg:
  82         minimum: 0
  83         maximum: 256
  84         description:
  85           Chip select used by the device.
  86
  87       spi-3wire:
  88         $ref: /schemas/types.yaml#/definitions/flag
  89         description:
  90           The device requires 3-wire mode.
  91
  92       spi-cpha:
  93         $ref: /schemas/types.yaml#/definitions/flag
  94         description:
  95           The device requires shifted clock phase (CPHA) mode.
  96
  97       spi-cpol:
  98         $ref: /schemas/types.yaml#/definitions/flag
  99         description:
 100           The device requires inverse clock polarity (CPOL) mode.
 101
 102       spi-cs-high:
 103         $ref: /schemas/types.yaml#/definitions/flag
 104         description:
 105           The device requires the chip select active high.
 106
 107       spi-lsb-first:
 108         $ref: /schemas/types.yaml#/definitions/flag
 109         description:
 110           The device requires the LSB first mode.
 111
 112       spi-max-frequency:
 113         $ref: /schemas/types.yaml#/definitions/uint32
 114         description:
 115           Maximum SPI clocking speed of the device in Hz.
 116
 117       spi-rx-bus-width:
 118         description:
 119           Bus width to the SPI bus used for read transfers.
 120         $ref: /schemas/types.yaml#/definitions/uint32
 121         enum: [1, 2, 4, 8]
 122         default: 1
 123
 124       spi-rx-delay-us:
 125         description:
 126           Delay, in microseconds, after a read transfer.
 127
 128       spi-tx-bus-width:
 129         description:
 130           Bus width to the SPI bus used for write transfers.
 131         $ref: /schemas/types.yaml#/definitions/uint32
 132         enum: [1, 2, 4, 8]
 133         default: 1
 134
 135       spi-tx-delay-us:
 136         description:
 137           Delay, in microseconds, after a write transfer.
 138
 139     required:
 140       - compatible
 141       - reg
 142
 143 examples:
 144   - |
 145     spi@f00 {
 146         #address-cells = <1>;
 147         #size-cells = <0>;
 148         compatible = "fsl,mpc5200b-spi","fsl,mpc5200-spi";
 149         reg = <0xf00 0x20>;
 150         interrupts = <2 13 0 2 14 0>;
 151         interrupt-parent = <&mpc5200_pic>;
 152
 153         ethernet-switch@0 {
 154             compatible = "micrel,ks8995m";
 155             spi-max-frequency = <1000000>;
 156             reg = <0>;
 157         };
 158
 159         codec@1 {
 160             compatible = "ti,tlv320aic26";
 161             spi-max-frequency = <100000>;
 162             reg = <1>;
 163         };
 164     };