Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm QMP PHY controller
   9
  10 maintainers:
  11   - Manu Gautam <mgautam@codeaurora.org>
  12
  13 description:
  14   QMP phy controller supports physical layer functionality for a number of
  15   controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
  16
  17 properties:
  18   compatible:
  19     enum:
  20       - qcom,ipq8074-qmp-pcie-phy
  21       - qcom,ipq8074-qmp-usb3-phy
  22       - qcom,msm8996-qmp-pcie-phy
  23       - qcom,msm8996-qmp-ufs-phy
  24       - qcom,msm8996-qmp-usb3-phy
  25       - qcom,msm8998-qmp-pcie-phy
  26       - qcom,msm8998-qmp-ufs-phy
  27       - qcom,msm8998-qmp-usb3-phy
  28       - qcom,sdm845-qhp-pcie-phy
  29       - qcom,sdm845-qmp-pcie-phy
  30       - qcom,sdm845-qmp-ufs-phy
  31       - qcom,sdm845-qmp-usb3-uni-phy
  32       - qcom,sm8150-qmp-ufs-phy
  33       - qcom,sm8250-qmp-ufs-phy
  34
  35   reg:
  36     items:
  37       - description: Address and length of PHY's common serdes block.
  38
  39   "#clock-cells":
  40      enum: [ 1, 2 ]
  41
  42   "#address-cells":
  43     enum: [ 1, 2 ]
  44
  45   "#size-cells":
  46     enum: [ 1, 2 ]
  47
  48   ranges: true
  49
  50   clocks:
  51     minItems: 1
  52     maxItems: 4
  53
  54   clock-names:
  55     minItems: 1
  56     maxItems: 4
  57
  58   resets:
  59     minItems: 1
  60     maxItems: 3
  61
  62   reset-names:
  63     minItems: 1
  64     maxItems: 3
  65
  66   vdda-phy-supply:
  67     description:
  68         Phandle to a regulator supply to PHY core block.
  69
  70   vdda-pll-supply:
  71     description:
  72         Phandle to 1.8V regulator supply to PHY refclk pll block.
  73
  74   vddp-ref-clk-supply:
  75     description:
  76         Phandle to a regulator supply to any specific refclk
  77         pll block.
  78
  79 #Required nodes:
  80 patternProperties:
  81   "^phy@[0-9a-f]+$":
  82     type: object
  83     description:
  84       Each device node of QMP phy is required to have as many child nodes as
  85       the number of lanes the PHY has.
  86
  87 required:
  88   - compatible
  89   - reg
  90   - "#clock-cells"
  91   - "#address-cells"
  92   - "#size-cells"
  93   - ranges
  94   - clocks
  95   - clock-names
  96   - resets
  97   - reset-names
  98   - vdda-phy-supply
  99   - vdda-pll-supply
 100
 101 additionalProperties: false
 102
 103 allOf:
 104   - if:
 105       properties:
 106         compatible:
 107           contains:
 108             enum:
 109               - qcom,sdm845-qmp-usb3-uni-phy
 110     then:
 111       properties:
 112         clocks:
 113           items:
 114             - description: Phy aux clock.
 115             - description: Phy config clock.
 116             - description: 19.2 MHz ref clk.
 117             - description: Phy common block aux clock.
 118         clock-names:
 119           items:
 120             - const: aux
 121             - const: cfg_ahb
 122             - const: ref
 123             - const: com_aux
 124         resets:
 125           items:
 126             - description: reset of phy block.
 127             - description: phy common block reset.
 128         reset-names:
 129           items:
 130             - const: phy
 131             - const: common
 132   - if:
 133       properties:
 134         compatible:
 135           contains:
 136             enum:
 137               - qcom,msm8996-qmp-pcie-phy
 138     then:
 139       properties:
 140         clocks:
 141           items:
 142             - description: Phy aux clock.
 143             - description: Phy config clock.
 144             - description: 19.2 MHz ref clk.
 145         clock-names:
 146           items:
 147             - const: aux
 148             - const: cfg_ahb
 149             - const: ref
 150         resets:
 151           items:
 152             - description: reset of phy block.
 153             - description: phy common block reset.
 154             - description: phy's ahb cfg block reset.
 155         reset-names:
 156           items:
 157             - const: phy
 158             - const: common
 159             - const: cfg
 160   - if:
 161       properties:
 162         compatible:
 163           contains:
 164             enum:
 165               - qcom,ipq8074-qmp-usb3-phy
 166               - qcom,msm8996-qmp-usb3-phy
 167               - qcom,msm8998-qmp-pcie-phy
 168               - qcom,msm8998-qmp-usb3-phy
 169     then:
 170       properties:
 171         clocks:
 172           items:
 173             - description: Phy aux clock.
 174             - description: Phy config clock.
 175             - description: 19.2 MHz ref clk.
 176         clock-names:
 177           items:
 178             - const: aux
 179             - const: cfg_ahb
 180             - const: ref
 181         resets:
 182           items:
 183             - description: reset of phy block.
 184             - description: phy common block reset.
 185         reset-names:
 186           items:
 187              - const: phy
 188              - const: common
 189   - if:
 190       properties:
 191         compatible:
 192           contains:
 193             enum:
 194               - qcom,msm8996-qmp-ufs-phy
 195     then:
 196       properties:
 197         clocks:
 198           items:
 199             - description: 19.2 MHz ref clk.
 200         clock-names:
 201           items:
 202             - const: ref
 203         resets:
 204           items:
 205             - description: PHY reset in the UFS controller.
 206         reset-names:
 207           items:
 208             - const: ufsphy
 209   - if:
 210       properties:
 211         compatible:
 212           contains:
 213             enum:
 214               - qcom,msm8998-qmp-ufs-phy
 215               - qcom,sdm845-qmp-ufs-phy
 216               - qcom,sm8150-qmp-ufs-phy
 217               - qcom,sm8250-qmp-ufs-phy
 218     then:
 219       properties:
 220         clocks:
 221           items:
 222             - description: 19.2 MHz ref clk.
 223             - description: Phy reference aux clock.
 224         clock-names:
 225           items:
 226             - const: ref
 227             - const: ref_aux
 228         resets:
 229           items:
 230             - description: PHY reset in the UFS controller.
 231         reset-names:
 232           items:
 233             - const: ufsphy
 234   - if:
 235       properties:
 236         compatible:
 237           contains:
 238             enum:
 239               - qcom,ipq8074-qmp-pcie-phy
 240     then:
 241       properties:
 242         clocks:
 243           items:
 244             - description: pipe clk.
 245         clock-names:
 246           items:
 247             - const: pipe_clk
 248         resets:
 249           items:
 250             - description: reset of phy block.
 251             - description: phy common block reset.
 252         reset-names:
 253           items:
 254             - const: phy
 255             - const: common
 256   - if:
 257       properties:
 258         compatible:
 259           contains:
 260             enum:
 261               - qcom,sdm845-qhp-pcie-phy
 262               - qcom,sdm845-qmp-pcie-phy
 263     then:
 264       properties:
 265         clocks:
 266           items:
 267             - description: Phy aux clock.
 268             - description: Phy config clock.
 269             - description: 19.2 MHz ref clk.
 270             - description: Phy refgen clk.
 271         clock-names:
 272           items:
 273             - const: aux
 274             - const: cfg_ahb
 275             - const: ref
 276             - const: refgen
 277         resets:
 278           items:
 279             - description: reset of phy block.
 280         reset-names:
 281           items:
 282             - const: phy
 283
 284 examples:
 285   - |
 286     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 287     usb_2_qmpphy: phy-wrapper@88eb000 {
 288         compatible = "qcom,sdm845-qmp-usb3-uni-phy";
 289         reg = <0x088eb000 0x18c>;
 290         #clock-cells = <1>;
 291         #address-cells = <1>;
 292         #size-cells = <1>;
 293         ranges = <0x0 0x088eb000 0x2000>;
 294
 295         clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
 296                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 297                  <&gcc GCC_USB3_SEC_CLKREF_CLK>,
 298                  <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
 299         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 300
 301         resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
 302                  <&gcc GCC_USB3_PHY_SEC_BCR>;
 303         reset-names = "phy", "common";
 304
 305         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
 306         vdda-pll-supply = <&vdda_usb2_ss_core>;
 307
 308         usb_2_ssphy: phy@200 {
 309                 reg = <0x200 0x128>,
 310                       <0x400 0x1fc>,
 311                       <0x800 0x218>,
 312                       <0x600 0x70>;
 313                 #clock-cells = <0>;
 314                 #phy-cells = <0>;
 315                 clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
 316                 clock-names = "pipe0";
 317                 clock-output-names = "usb3_uni_phy_pipe_clk_src";
 318             };
 319         };