1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/phy/intel,combo-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Intel ComboPhy Subsystem
10 - Dilip Kota <eswara.kota@linux.intel.com>
13 Intel Combophy subsystem supports PHYs for PCIe, EMAC and SATA
14 controllers. A single Combophy provides two PHY instances.
18 pattern: "combophy(@.*|-[0-9a-f])*$"
22 - const: intel,combophy-lgm
23 - const: intel,combo-phy
30 - description: ComboPhy core registers
31 - description: PCIe app core control registers
49 $ref: /schemas/types.yaml#/definitions/phandle-array
50 description: Chip configuration registers handle and ComboPhy instance id
53 $ref: /schemas/types.yaml#/definitions/phandle-array
54 description: HSIO registers handle and ComboPhy instance id on NOC
59 Specify the flag to configure ComboPHY in dual lane mode.
62 $ref: /schemas/types.yaml#/definitions/uint32
64 Mode of the two phys in ComboPhy.
65 See dt-bindings/phy/phy.h for values.
80 additionalProperties: false
84 #include <dt-bindings/phy/phy.h>
86 compatible = "intel,combophy-lgm", "intel,combo-phy";
89 reg = <0xd0a00000 0x40000>,
91 reg-names = "core", "app";
92 resets = <&rcu0 0x50 6>,
96 reset-names = "phy", "core", "iphy0", "iphy1";
97 intel,syscfg = <&sysconf 0>;
98 intel,hsio = <&hsiol 0>;
99 intel,phy-mode = <PHY_TYPE_PCIE>;