1 # SPDX-License-Identifier: (GPL-2.0)
4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NVIDIA Tegra30 SoC Memory Controller
10 - Dmitry Osipenko <digetx@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
12 - Thierry Reding <thierry.reding@gmail.com>
15 Tegra30 Memory Controller architecturally consists of the following parts:
17 Arbitration Domains, which can handle a single request or response per
18 clock from a group of clients. Typically, a system has a single Arbitration
19 Domain, but an implementation may divide the client space into multiple
20 Arbitration Domains to increase the effective system bandwidth.
22 Protocol Arbiter, which manage a related pool of memory devices. A system
23 may have a single Protocol Arbiter or multiple Protocol Arbiters.
25 Memory Crossbar, which routes request and responses between Arbitration
26 Domains and Protocol Arbiters. In the simplest version of the system, the
27 Memory Crossbar is just a pass through between a single Arbitration Domain
28 and a single Protocol Arbiter.
30 Global Resources, which include things like configuration registers which
31 are shared across the Memory Subsystem.
33 The Tegra30 Memory Controller handles memory requests from internal clients
34 and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2
39 const: nvidia,tegra30-mc
61 "^emc-timings-[0-9]+$":
65 $ref: /schemas/types.yaml#/definitions/uint32
67 Value of RAM_CODE this timing set is used for.
75 Memory clock rate in Hz.
79 nvidia,emem-configuration:
80 $ref: /schemas/types.yaml#/definitions/uint32-array
82 Values to be written to the EMEM register block. See section
83 "18.13.1 MC Registers" in the TRM.
85 - description: MC_EMEM_ARB_CFG
86 - description: MC_EMEM_ARB_OUTSTANDING_REQ
87 - description: MC_EMEM_ARB_TIMING_RCD
88 - description: MC_EMEM_ARB_TIMING_RP
89 - description: MC_EMEM_ARB_TIMING_RC
90 - description: MC_EMEM_ARB_TIMING_RAS
91 - description: MC_EMEM_ARB_TIMING_FAW
92 - description: MC_EMEM_ARB_TIMING_RRD
93 - description: MC_EMEM_ARB_TIMING_RAP2PRE
94 - description: MC_EMEM_ARB_TIMING_WAP2PRE
95 - description: MC_EMEM_ARB_TIMING_R2R
96 - description: MC_EMEM_ARB_TIMING_W2W
97 - description: MC_EMEM_ARB_TIMING_R2W
98 - description: MC_EMEM_ARB_TIMING_W2R
99 - description: MC_EMEM_ARB_DA_TURNS
100 - description: MC_EMEM_ARB_DA_COVERS
101 - description: MC_EMEM_ARB_MISC0
102 - description: MC_EMEM_ARB_RING1_THROTTLE
106 - nvidia,emem-configuration
108 additionalProperties: false
113 additionalProperties: false
124 additionalProperties: false
128 memory-controller@7000f000 {
129 compatible = "nvidia,tegra30-mc";
130 reg = <0x7000f000 0x400>;
131 clocks = <&tegra_car 32>;
134 interrupts = <0 77 4>;
140 nvidia,ram-code = <1>;
143 clock-frequency = <667000000>;
145 nvidia,emem-configuration = <
146 0x0000000a /* MC_EMEM_ARB_CFG */
147 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */
148 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */
149 0x00000004 /* MC_EMEM_ARB_TIMING_RP */
150 0x00000010 /* MC_EMEM_ARB_TIMING_RC */
151 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */
152 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */
153 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */
154 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */
155 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */
156 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */
157 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */
158 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */
159 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */
160 0x08040202 /* MC_EMEM_ARB_DA_TURNS */
161 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */
162 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */
163 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */