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drm/i915: Reset sched_engine.no_priolist immediately after dequeue
2021-06-18 Matthew Brostdrm/i915: Reset sched_engine.no_priolist immediately...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-06-18 Matthew Brostdrm/i915: Add i915_sched_engine_is_empty function
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-06-18 Matthew Brostdrm/i915: Move priolist to new i915_sched_engine object
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-06-18 Matt Roperdrm/i915: Add support for explicit L3BANK steering
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210617211425.1943662-4-matthew.d.roper@intel.com
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2021-06-18 Matt Roperdrm/i915: Add GT support for multiple types of multicast...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210617211425.1943662-3-matthew.d.roper@intel.com
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2021-06-18 Daniele Ceraolo... drm/i915: extract steered reg access to common function
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210617211425.1943662-2-matthew.d.roper@intel.com
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2021-05-27 Aditya Swarupdrm/i915: Add Wa_14010733141
Cc: Matt Roper <matthew.d.roper@intel.com>
Co-developed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2021-05-26 Gwan-gyeong Mundrm/i915/display: Remove a redundant function argument...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210526000656.3060314-4-matthew.d.roper@intel.com
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2021-05-26 Manasi Navaredrm/i915/xelpd: Add VRR guardband for VRR CTL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210526000656.3060314-3-matthew.d.roper@intel.com
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2021-05-26 Matt Roperdrm/i915/xelpd: Enhanced pipe underrun reporting
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210526000656.3060314-2-matthew.d.roper@intel.com
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2021-05-15 José Roberto de... drm/i915/adl_p: Disable CCS on a-step (Wa_22011186057)
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-20-matthew.d.roper@intel.com
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2021-05-15 José Roberto de... drm/i915/display/adl_p: Implement Wa_22011320316
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-19-matthew.d.roper@intel.com
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2021-05-15 José Roberto de... drm/i915/adl_p: Implement Wa_22011091694
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-18-matthew.d.roper@intel.com
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2021-05-15 José Roberto de... drm/i915/adl_p: Add IPs stepping mapping
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-17-matthew.d.roper@intel.com
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2021-05-15 Animesh Mannadrm/i915/bigjoiner: atomic commit changes for uncompressed...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-16-matthew.d.roper@intel.com
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2021-05-15 Animesh Mannadrm/i915/bigjoiner: Avoid dsc_compute_config for uncompresse...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-15-matthew.d.roper@intel.com
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2021-05-15 Animesh Mannadrm/i915/bigjoiner: Mode validation with uncompressed...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-14-matthew.d.roper@intel.com
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2021-05-15 Mika Kaholadrm/i915/adl_p: Enable/disable loadgen sharing
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-13-matthew.d.roper@intel.com
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2021-05-15 Ville Syrjälädrm/i915: Move intel_modeset_all_pipes()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-12-matthew.d.roper@intel.com
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2021-05-15 José Roberto de... drm/i915/adl_p: Enable modular fia
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-11-matthew.d.roper@intel.com
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2021-05-15 José Roberto de... drm/i915/display/tc: Rename safe_mode functions ownership
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-10-matthew.d.roper@intel.com
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2021-05-15 Anusha Srivatsadrm/i915/adl_p: Add cdclk support for ADL-P
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-9-matthew.d.roper@intel.com
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2021-05-15 Matt Roperdrm/i915/adl_p: Extend PLANE_WM bits for blocks & lines
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-8-matthew.d.roper@intel.com
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2021-05-15 José Roberto de... drm/i915/xelpd: Provide port/phy mapping for vbt
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-7-matthew.d.roper@intel.com
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2021-05-15 Vandita Kulkarnidrm/i915: Get slice height before computing rc params
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-6-matthew.d.roper@intel.com
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2021-05-15 Vandita Kulkarnidrm/i915/xelpd: Support DP1.4 compression BPPs
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-5-matthew.d.roper@intel.com
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2021-05-15 Vandita Kulkarnidrm/i915/display/dsc: Refactor intel_dp_dsc_compute_bpp
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-4-matthew.d.roper@intel.com
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2021-05-15 Matt Roperdrm/i915/xelpd: Increase maximum watermark lines to 255
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-3-matthew.d.roper@intel.com
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2021-05-15 Matt Roperdrm/i915/xelpd: Handle new location of outputs D and E
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210514153711.2359617-2-matthew.d.roper@intel.com
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2021-05-12 Umesh Nerlige Ramappadrm/i915/perf: Enable OA formats for ADL_P
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-8-matthew.d.roper@intel.com
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2021-05-12 Clinton Taylordrm/i915/adl_p: Add PCH support
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-7-matthew.d.roper@intel.com
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2021-05-12 Matt Roperdrm/i915/xelpd: Add Wa_14011503030
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-6-matthew.d.roper@intel.com
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2021-05-12 Matt Roperdrm/i915/xelpd: Required bandwidth increases when VT...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-5-matthew.d.roper@intel.com
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2021-05-12 Matt Roperdrm/i915/xelpd: Add XE_LPD power wells
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-4-matthew.d.roper@intel.com
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2021-05-12 Matt Roperdrm/i915/xelpd: Define plane capabilities
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-3-matthew.d.roper@intel.com
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2021-05-12 Matt Roperdrm/i915/xelpd: Handle proper AUX interrupt bits
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210512042144.2089071-2-matthew.d.roper@intel.com
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2021-04-07 Matt Roperdrm/i915/display: Eliminate IS_GEN9_{BC,LP}
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210407203945.1432531-1-matthew.d.roper@intel.com
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2021-03-23 Matt Roperdrm/i915/display: Simplify GLK display version tests
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210322233840.4056851-1-matthew.d.roper@intel.com
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2021-03-23 Matt Roperdrm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriat...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210320044245.3920043-6-matthew.d.roper@intel.com
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2021-03-23 Matt Roperdrm/i915: Convert INTEL_GEN() to DISPLAY_VER() as appropriat...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210320044245.3920043-5-matthew.d.roper@intel.com
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2021-03-23 Matt Roperdrm/i915/display: Eliminate most usage of INTEL_GEN()
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210320044245.3920043-4-matthew.d.roper@intel.com
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2021-03-23 Matt Roperdrm/i915: Add DISPLAY_VER() and related macros
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210320044245.3920043-3-matthew.d.roper@intel.com
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2021-03-23 Matt Roperdrm/i915/display: Convert gen5/gen6 tests to IS_IRONLAKE...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210320044245.3920043-2-matthew.d.roper@intel.com
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2021-02-13 Matt Roperdrm/i915: Try to detect sudden loss of MMIO access
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210212211925.3418280-2-matthew.d.roper@intel.com
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2021-02-13 Matt Roperdrm/i915: FPGA_DBG is display-specific
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210212222049.3516344-1-matthew.d.roper@intel.com
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2021-01-12 Matt Roperdrm/i915/dg1: Update voltage swing tables for DP
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20210108222528.1954514-1-matthew.d.roper@intel.com
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2021-01-06 Matt Roperdrm/i915/rkl: Add DP vswing programming tables
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201218040535.45492-1-matthew.d.roper@intel.com
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2020-11-17 Bob Paauwedrm/i915: Tweaked Wa_14010685332 for PCHs used on gen11...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-10-16 Matt Roperdrm/i915/rkl: Add new cdclk table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201015220038.271740-1-matthew.d.roper@intel.com
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2020-10-10 Matt Roperdrm/i915: Update gen12 multicast register ranges
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201009194442.3668677-4-matthew.d.roper@intel.com
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2020-10-10 Matt Roperdrm/i915: Update gen12 forcewake table
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201009194442.3668677-3-matthew.d.roper@intel.com
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2020-10-10 Matt Roperdrm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GT
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20201009194442.3668677-2-matthew.d.roper@intel.com
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2020-06-26 Matt Roperdrm/i915: Extend Wa_14010685332 to all ICP+ PCH's
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200617180006.4130501-1-matthew.d.roper@intel.com
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2020-06-09 Aditya Swarupdrm/i915/rkl: Don't try to read out DSI transcoders
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200606025740.3308880-5-matthew.d.roper@intel.com
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2020-06-09 Matt Roperdrm/i915/rkl: Update TGP's pin mapping when paired...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200606025740.3308880-4-matthew.d.roper@intel.com
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2020-06-09 Matt Roperdrm/i915/rkl: RKL uses ABOX0 for pixel transfers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200606025740.3308880-2-matthew.d.roper@intel.com
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2020-06-04 José Roberto de... drm/i915/rkl: Disable PSR2
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-15-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Don't try to access transcoder D
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-10-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Setup ports/phys
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-6-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Handle comp master/slave relationships...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-12-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Add DDC pin mapping
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-9-matthew.d.roper@intel.com
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2020-06-04 Lucas De Marchidrm/i915/rkl: provide port/phy mapping for vbt
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-7-matthew.d.roper@intel.com
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2020-06-04 Matt Roperdrm/i915/rkl: Set transcoder mask properly
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200603211529.3005059-2-matthew.d.roper@intel.com
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2020-05-05 Matt Roperdrm/i915/icp: Add Wa_14010685332
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200501213701.371443-1-matthew.d.roper@intel.com
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2020-04-27 Matt Roperdrm/i915: Use proper fault mask in interrupt postinstall too
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200424231423.4065231-1-matthew.d.roper@intel.com
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2020-04-21 Matt Roperdrm/i915: Use single set of AUX powerwell ops for gen11+
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200415233435.3064257-2-matthew.d.roper@intel.com
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2020-04-17 Matt Roperdrm/i915/tgl: TBT AUX should use TC power well ops
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200415233435.3064257-1-matthew.d.roper@intel.com
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2020-04-15 Matt Roperdrm/i915/tgl: Initialize multicast register steering...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200414211118.2787489-4-matthew.d.roper@intel.com
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2020-04-15 Matt Roperdrm/i915/tgl: Extend Wa_1409767108:tgl to B0 stepping
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200414211118.2787489-2-matthew.d.roper@intel.com
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2020-04-15 Matt Roperdrm/i915/tgl: Add Wa_14010477008:tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200414211118.2787489-3-matthew.d.roper@intel.com
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2020-04-15 Matt Atwooddrm/i915/ehl: extended Wa_2006604312 to ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-04-02 Swathi Dhanavanthridrm/i915/tgl: Make Wa_14010229206 permanent
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-19 Swathi Dhanavanthridrm/i915/tgl: Add new PCI IDs to TGL
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-03-13 Matt Roperdrm/i915: Add Wa_1605460711 / Wa_1408767742 to ICL...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-7-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Apply Wa_1406680159:icl,ehl as an engine...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-6-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Add Wa_1406306137:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-5-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Add Wa_1604278689:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-4-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Add Wa_1209644611:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-3-matthew.d.roper@intel.com
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2020-03-13 Matt Roperdrm/i915: Handle all MCR ranges
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200311162300.1838847-2-matthew.d.roper@intel.com
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2020-03-09 Matt Roperdrm/i915/tgl: Don't treat unslice registers as masked
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200306171139.1414649-1-matthew.d.roper@intel.com
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2020-03-04 Matt Roperdrm/i915/ehl: Check PHY type before reading DPLL frequency
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200303195043.959913-1-matthew.d.roper@intel.com
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2020-02-26 Matt Atwooddrm/i915/tgl: Add Wa_1606054188:tgl
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200224223651.3801646-1-matthew.d.roper@intel.com
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2020-02-26 Matt Roperdrm/i915/tgl: Allow DC5/DC6 entry while PG2 is active
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200220231843.3127468-1-matthew.d.roper@intel.com
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2020-02-21 Matt Roperdrm/i915/tgl: Add Wa_22010178259:tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200219215655.2923650-1-matthew.d.roper@intel.com
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2020-02-20 Matt Roperdrm/i915/tgl: Program MBUS_ABOX{1,2}_CTL during display...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200204011032.582737-2-matthew.d.roper@intel.com
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2020-02-20 Matt Roperdrm/i915: Program MBUS with rmw during initialization
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200204011032.582737-1-matthew.d.roper@intel.com
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2020-02-18 Rafael Antognollidrm/i915/tgl: Add Wa_1808121037 to tgl.
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
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2020-02-10 Matt Roperdrm/i915/tgl: Update cdclk voltage level settings
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200207001417.1229251-2-matthew.d.roper@intel.com
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2020-02-10 Matt Roperdrm/i915/ehl: Update port clock voltage level requirements
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200207001417.1229251-1-matthew.d.roper@intel.com
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2020-01-16 Matt Atwooddrm/i915: add Wa_14010594013: icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-15 Radhakrishna Sripadadrm/i915/tgl: Add Wa_1409825376 to tgl
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-14 Matt Roperdrm/i915/gen11: Add additional pcode status values
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20200111014511.2988923-1-matthew.d.roper@intel.com
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2020-01-10 Vivek Kasireddydrm/i915/dsi: Parse the I2C element from the VBT MIPI...
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-06 Kai Vehmanendrm/i915: Limit audio CDCLK>=2*BCLK constraint back...
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
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2020-01-01 Matt Roperdrm/i915: Add Wa_1407352427:icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191231190713.1549533-1-matthew.d.roper@intel.com
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2019-12-31 Matt Roperdrm/i915/tgl: Assume future platforms will inherit...
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224231521.3430660-1-matthew.d.roper@intel.com
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2019-12-27 Matt Roperdrm/i915/tgl: Extend Wa_1408615072 to tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224012026.3157766-4-matthew.d.roper@intel.com
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2019-12-27 Matt Roperdrm/i915: Add Wa_1408615072 and Wa_1407596294 to icl,ehl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224012026.3157766-3-matthew.d.roper@intel.com
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2019-12-27 Matt Roperdrm/i915: Extend WaDisableDARBFClkGating to icl,ehl,tgl
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191224012026.3157766-2-matthew.d.roper@intel.com
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2019-12-13 Matt Roperdrm/i915/icl: Cleanup combo PHY aux power well handlers
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
...msgid/20191213010600.701315-1-matthew.d.roper@intel.com
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