From 0aec75a5963e8d72c59a42055c5b5c524893b910 Mon Sep 17 00:00:00 2001 From: Heiner Kallweit Date: Tue, 8 Dec 2020 18:57:02 +0100 Subject: [PATCH] PCI: Reduce pci_set_cacheline_size() message to debug level Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an annnoying message like the following that results in user questions whether something is broken: xhci_hcd 0000:00:15.0: cache line size of 64 is not supported Root cause of the message is that on several chips the Cache Line Size register is hard-wired to 0. Change this message to debug level; an interested caller can still inform the user (if deemed helpful) based on the return code. Link: https://lore.kernel.org/r/be1ed3a2-98b9-ee1d-20b8-477f3d93961d@gmail.com Signed-off-by: Heiner Kallweit Signed-off-by: Bjorn Helgaas --- drivers/pci/pci.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c index dd4bbb699abd..556fb5e00d86 100644 --- a/drivers/pci/pci.c +++ b/drivers/pci/pci.c @@ -4317,7 +4317,7 @@ int pci_set_cacheline_size(struct pci_dev *dev) if (cacheline_size == pci_cache_line_size) return 0; - pci_info(dev, "cache line size of %d is not supported\n", + pci_dbg(dev, "cache line size of %d is not supported\n", pci_cache_line_size << 2); return -EINVAL; -- 2.20.1