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(parent: 8a30923) | patch
cxgb4/chcr: complete record tx handling
authorRohit Maheshwari <rohitm@chelsio.com>
Sat, 7 Mar 2020 14:36:05 +0000 (20:06 +0530)
committerDavid S. Miller <davem@davemloft.net>
Mon, 9 Mar 2020 04:16:23 +0000 (21:16 -0700)
commit5a4b9fe7fece62ecab6fb28fe92362f83b41c33e
tree2c7d7dae74fe96071650099bb131d92609781cd1tree | snapshot
parent8a30923e1598c050f2670b88d51e3752b52b49aecommit | diff
cxgb4/chcr: complete record tx handling

Added tx handling in this patch. This includes handling of segments
contain single complete record.

v1->v2:
- chcr_write_cpl_set_tcb_ulp is added in this patch.

v3->v4:
- mss calculation logic.
- replaced kfree_skb with dev_kfree_skb_any.
- corrected error message reported by kbuild test robot <lkp@intel.com>

Signed-off-by: Rohit Maheshwari <rohitm@chelsio.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/crypto/chelsio/chcr_common.h diff | blob | history
drivers/crypto/chelsio/chcr_core.c diff | blob | history
drivers/crypto/chelsio/chcr_core.h diff | blob | history
drivers/crypto/chelsio/chcr_ktls.c diff | blob | history
drivers/crypto/chelsio/chcr_ktls.h diff | blob | history
drivers/net/ethernet/chelsio/cxgb4/sge.c diff | blob | history
drivers/net/ethernet/chelsio/cxgb4/t4_msg.h diff | blob | history
drivers/net/ethernet/chelsio/cxgb4/t4_tcb.h diff | blob | history
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