linux-2.6-microblaze.git
3 months agoPCI: dwc: Fix inverted condition of DMA mask setup warning
Alexander Lobakin [Tue, 22 Dec 2020 15:07:43 +0000 (15:07 +0000)]
PCI: dwc: Fix inverted condition of DMA mask setup warning

Commit 660c486590aa ("PCI: dwc: Set 32-bit DMA mask for MSI target address
allocation") added dma_mask_set() call to explicitly set 32-bit DMA mask
for MSI message mapping, but for now it throws a warning on ret == 0, while
dma_set_mask() returns 0 in case of success.

Fix this by inverting the condition.

[bhelgaas: join string to make it greppable]
Fixes: 660c486590aa ("PCI: dwc: Set 32-bit DMA mask for MSI target address allocation")
Link: https://lore.kernel.org/r/20201222150708.67983-1-alobakin@pm.me
Signed-off-by: Alexander Lobakin <alobakin@pm.me>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: tegra: Fix host link initialization
Rob Herring [Fri, 18 Dec 2020 14:39:05 +0000 (08:39 -0600)]
PCI: tegra: Fix host link initialization

Commit b9ac0f9dc8ea ("PCI: dwc: Move dw_pcie_setup_rc() to DWC common
code") broke enumeration of downstream devices on Tegra:

In non-working case (next-20201211):

  0001:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad2 (rev a1)
  0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13)
  0005:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad0 (rev a1)

In working case (v5.10-rc7):

  0001:00:00.0 PCI bridge: Molex Incorporated Device 1ad2 (rev a1)
  0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13)
  0005:00:00.0 PCI bridge: Molex Incorporated Device 1ad0 (rev a1)
  0005:01:00.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab)
  0005:02:02.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab)
  0005:03:00.0 USB controller: PLX Technology, Inc. Device 3380 (rev ab)

The problem seems to be dw_pcie_setup_rc() is now called twice before and
after the link up handling. The fix is to move Tegra's link up handling to
.start_link() function like other DWC drivers. Tegra is a bit more
complicated than others as it re-inits the whole DWC controller to retry
the link. With this, the initialization ordering is restored to match the
prior sequence.

Fixes: b9ac0f9dc8ea ("PCI: dwc: Move dw_pcie_setup_rc() to DWC common code")
Link: https://lore.kernel.org/r/20201218143905.1614098-1-robh@kernel.org
Reported-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Tested-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Vidya Sagar <vidyas@nvidia.com>
3 months agoMerge branch 'remotes/lorenzo/pci/misc'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:14 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/misc'

- Add PCI endpoint subsystem references to MAINTAINERS (Gustavo Pimentel)

* remotes/lorenzo/pci/misc:
  MAINTAINERS: Add missing documentation references to PCI Endpoint Subsystem

3 months agoMerge branch 'remotes/lorenzo/pci/vmd'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:13 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/vmd'

- Offset client VMD MSI-X vectors (Jon Derrick)

* remotes/lorenzo/pci/vmd:
  PCI: vmd: Offset Client VMD MSI-X vectors

3 months agoMerge branch 'remotes/lorenzo/pci/rcar'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:13 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/rcar'

- Convert DT bindings to json-schema (Yoshihiro Shimoda)

- Document r8a77965 DT bindings (Yoshihiro Shimoda)

- Document r8a774e1 DT bindings (Lad Prabhakar)

* remotes/lorenzo/pci/rcar:
  dt-bindings: PCI: rcar-pci-host: Document r8a774e1 bindings
  dt-bindings: PCI: rcar-pci-host: Document r8a77965 bindings
  dt-bindings: PCI: rcar-pci-host: Convert bindings to json-schema
  PCI: rcar: Drop unused members from struct rcar_pcie_host

3 months agoMerge branch 'remotes/lorenzo/pci/keystone'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:12 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/keystone'

- Enable keystone compile testing on non-ARM arches (Alex Dewar)

* remotes/lorenzo/pci/keystone:
  PCI: keystone: Enable compile-testing on !ARM

3 months agoMerge branch 'remotes/lorenzo/pci/iproc'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:12 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/iproc'

- Declare iproc register set sizes to help avoid out-of-bound accesses
  (Bharat Gooty)

- Invalidate iproc PAXB IARR1/IMAP1 inbound windows to erase bootloader
  footprint (Roman Bacik)

- Log Root Port link speed & width at startup (Srinath Mannam)

* remotes/lorenzo/pci/iproc:
  PCI: iproc: Enhance PCIe Link information display
  PCI: iproc: Invalidate correct PAXB inbound windows
  PCI: iproc: Fix out-of-bound array accesses

3 months agoMerge branch 'remotes/lorenzo/pci/dwc'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:11 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/dwc'

- Support multiple ATU memory regions (Rob Herring)

- Warn if non-prefetchable memory aperture is > 32-bit (Vidya Sagar)

- Allow programming ATU for >4GB memory (Vidya Sagar)

- Move ATU offset out of driver match data (Rob Herring)

- Move "dbi", "dbi2", and "addr_space" resource setup to common code (Rob
  Herring)

- Remove unneeded function wrappers (Rob Herring)

- Ensure all outbound ATU windows are reset to reduce dependencies on
  bootloader (Rob Herring)

- Use the default MSI irq_chip for dra7xx (Rob Herring)

- Drop the .set_num_vectors() host op (Rob Herring)

- Move MSI interrupt setup into DWC common code (Rob Herring)

- Rework and simplify DWC MSI initialization (Rob Herring)

- Move link handling to DWC common code (Rob Herring)

- Move dw_pcie_msi_init() calls to DWC common code (Rob Herring)

- Move dw_pcie_setup_rc() calls to DWC common code (Rob Herring)

- Remove unnecessary wrappers around dw_pcie_host_init() (Rob Herring)

- Revert "keystone: Drop duplicated 'num-viewport'" to prepare for
  detecting number of iATU regions without help from DT (Rob Herring)

- Move inbound and outbound windows to common struct (Rob Herring)

- Detect number of DWC iATU windows from device registers (Rob Herring)

- Drop samsung,exynos5440-pcie binding (Marek Szyprowski)

- Add samsung,exynos-pcie and samsung,exynos-pcie-phy bindings for
  Exynos5433 variant (Marek Szyprowski)

- Rework phy-exynos-pcie driver to support Exynos5433 PCIe PHY (Jaehoon
  Chung)

- Rework pci-exynos.c to support Exynos5433 PCIe host (Jaehoon Chung)

- Move tegra "dbi" accesses to post common DWC initialization (Vidya Sagar)

- Read tegra dbi" base address in application logic (Vidya Sagar)

- Fix tegra ASPM-L1SS advertisement disable code (Vidya Sagar)

- Set Tegra194 DesignWare IP version to 0x490A (Vidya Sagar)

- Continue tegra unconfig sequence even if parts fail (Vidya Sagar)

- Check return value of tegra_pcie_init_controller() (Vidya Sagar)

- Disable tegra LTSSM during L2 entry (Vidya Sagar)

- Add SM8250 SoC PCIe DT bindings and support (Manivannan Sadhasivam)

- Add SM8250 BDF to SID mapping (Manivannan Sadhasivam)

- Set 32-bit DMA mask for DWC MSI target address allocation (Vidya Sagar)

* remotes/lorenzo/pci/dwc:
  PCI: dwc: Set 32-bit DMA mask for MSI target address allocation
  PCI: qcom: Add support for configuring BDF to SID mapping for SM8250
  PCI: qcom: Add SM8250 SoC support
  dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
  PCI: tegra: Disable LTSSM during L2 entry
  PCI: tegra: Check return value of tegra_pcie_init_controller()
  PCI: tegra: Continue unconfig sequence even if parts fail
  PCI: tegra: Set DesignWare IP version
  PCI: tegra: Fix ASPM-L1SS advertisement disable code
  PCI: tegra: Read "dbi" base address to program in application logic
  PCI: tegra: Move "dbi" accesses to post common DWC initialization
  PCI: dwc: exynos: Rework the driver to support Exynos5433 variant
  phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
  dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding
  dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding
  dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding
  PCI: dwc: Detect number of iATU windows
  PCI: dwc: Move inbound and outbound windows to common struct
  Revert "PCI: dwc/keystone: Drop duplicated 'num-viewport'"
  PCI: dwc: Remove unnecessary wrappers around dw_pcie_host_init()
  PCI: dwc: Move dw_pcie_setup_rc() to DWC common code
  PCI: dwc: Move dw_pcie_msi_init() into core
  PCI: dwc: Move link handling into common code
  PCI: dwc: Rework MSI initialization
  PCI: dwc: Move MSI interrupt setup into DWC common code
  PCI: dwc: Drop the .set_num_vectors() host op
  PCI: dwc/dra7xx: Use the common MSI irq_chip
  PCI: dwc: Ensure all outbound ATU windows are reset
  PCI: dwc/intel-gw: Remove some unneeded function wrappers
  PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code
  PCI: dwc/intel-gw: Move ATU offset out of driver match data
  PCI: dwc: Add support to program ATU for >4GB memory
  PCI: of: Warn if non-prefetchable memory aperture size is > 32-bit
  PCI: dwc: Support multiple ATU memory regions

3 months agoMerge branch 'remotes/lorenzo/pci/cadence'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:11 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/cadence'

- Make "cdns,max-outbound-regions" optional (Kishon Vijay Abraham I)

- Fix "ti,syscon-pcie-ctrl" DT property to take argument (Kishon Vijay
  Abraham I)

- Add TI J7200 host and endpoint mode DT bindings (Kishon Vijay Abraham I)

* remotes/lorenzo/pci/cadence:
  PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
  dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
  dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
  dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
  PCI: cadence: Do not error if "cdns,max-outbound-regions" is not found
  dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property

3 months agoMerge branch 'remotes/lorenzo/pci/brcmstb'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:11 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/brcmstb'

- Initialize "tmp" before use (Jim Quinlan)

* remotes/lorenzo/pci/brcmstb:
  PCI: brcmstb: Initialize "tmp" before use

3 months agoMerge branch 'remotes/lorenzo/pci/aardvark'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:10 +0000 (15:11 -0600)]
Merge branch 'remotes/lorenzo/pci/aardvark'

- Update comment about delay before link training (Pali Rohár)

* remotes/lorenzo/pci/aardvark:
  PCI: aardvark: Update comment about disabling link training

3 months agoMerge branch 'pci/ecam'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:10 +0000 (15:11 -0600)]
Merge branch 'pci/ecam'

- Unify ECAM constants in native PCI Express drivers (Krzysztof Wilczyński)

- Add thunder-pem constant for custom ".bus_shift" initialiser (Krzysztof
  Wilczyński)

- Convert iproc to use new ECAM constants (Krzysztof Wilczyński)

- Change vmd __iomem pointers from "char *" to "void *" (Krzysztof
  Wilczyński)

- Remove unused xgene .bus_shift initialisers (Krzysztof Wilczyński)

* pci/ecam:
  PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c
  PCI: vmd: Update type of the __iomem pointers
  PCI: iproc: Convert to use the new ECAM constants
  PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser
  PCI: Unify ECAM constants in native PCI Express drivers

3 months agoMerge branch 'pci/virtualization'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:09 +0000 (15:11 -0600)]
Merge branch 'pci/virtualization'

- Mark AMD Raven iGPU ATS as broken in some Emerson platforms to avoid
  issues (Alex Deucher)

- Add function 1 DMA alias quirk for Marvell 9215 SATA controller (Bjorn
  Helgaas)

* pci/virtualization:
  PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller
  PCI: Mark AMD Raven iGPU ATS as broken in some platforms

3 months agoMerge branch 'pci/ptm'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:09 +0000 (15:11 -0600)]
Merge branch 'pci/ptm'

- Save/restore Precision Time Measurement Capability for suspend/resume
  (David E. Box)

- Disable PTM during suspend to save power (David E. Box)

* pci/ptm:
  PCI: Disable PTM during suspend to save power
  PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume

3 months agoMerge branch 'pci/pm'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:08 +0000 (15:11 -0600)]
Merge branch 'pci/pm'

- Add sysfs attribute for device power state (Maximilian Luz)

- Rename pci_wakeup_bus() to pci_resume_bus() (Mika Westerberg)

- Do not generate wakeup event when runtime resuming bus (Mika Westerberg)

* pci/pm:
  PCI/PM: Do not generate wakeup event when runtime resuming device
  PCI/PM: Rename pci_wakeup_bus() to pci_resume_bus()
  PCI: Add sysfs attribute for device power state

3 months agoMerge branch 'pci/msi'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:08 +0000 (15:11 -0600)]
Merge branch 'pci/msi'

- Disable MSI for broken Pericom PCIe-USB adapter (Andy Shevchenko)

- Move MSI/MSI-X init to msi.c (Bjorn Helgaas)

- Move MSI/MSI-X flags updaters to msi.c (Bjorn Helgaas)

- Warn if we assign 64-bit MSI address to device that only supports 32-bit
  MSI (Vidya Sagar)

* pci/msi:
  PCI/MSI: Set device flag indicating only 32-bit MSI support
  PCI/MSI: Move MSI/MSI-X flags updaters to msi.c
  PCI/MSI: Move MSI/MSI-X init to msi.c
  PCI: Use predefined Pericom Vendor ID
  PCI: Disable MSI for Pericom PCIe-USB adapter

3 months agoMerge branch 'pci/misc'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:08 +0000 (15:11 -0600)]
Merge branch 'pci/misc'

- Update kernel-doc to match function prototypes (Mauro Carvalho Chehab)

- Bounds-check "pci=resource_alignment=" requests (Bjorn Helgaas)

- Fix integer overflow in "pci=resource_alignment=" requests (Colin Ian
  King)

- Remove unused HAVE_PCI_SET_MWI definition (Heiner Kallweit)

- Reduce pci_set_cacheline_size() message to debug level (Heiner Kallweit)

* pci/misc:
  PCI: Reduce pci_set_cacheline_size() message to debug level
  PCI: Remove unused HAVE_PCI_SET_MWI
  PCI: Fix overflow in command-line resource alignment requests
  PCI: Bounds-check command-line resource alignment requests
  PCI: Fix kernel-doc markup

# Conflicts:
# drivers/pci/pci-driver.c

3 months agoMerge branch 'pci/hotplug'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:07 +0000 (15:11 -0600)]
Merge branch 'pci/hotplug'

- Remove unneeded break in ibmphp (Bjorn Helgaas)

- Fix pci_slot_release() NULL pointer dereference (Jubin Zhong)

* pci/hotplug:
  PCI: Fix pci_slot_release() NULL pointer dereference
  PCI: ibmphp: Remove unneeded break

3 months agoMerge branch 'pci/err'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:06 +0000 (15:11 -0600)]
Merge branch 'pci/err'

- Stop writing AER Capability when we don't own it (Sean V Kelley)

- Bind RCEC devices to the Port driver (Qiuxu Zhuo)

- Cache the RCEC RA Capability offset (Sean V Kelley)

- Add pci_walk_bridge() (Sean V Kelley)

- Clear AER status only when we control AER (Sean V Kelley)

- Recover from RCEC AER errors (Sean V Kelley)

- Add pcie_link_rcec() to associate RCiEPs with RCECs (Sean V Kelley)

- Recover from RCiEP AER errors (Sean V Kelley)

- Add pcie_walk_rcec() for RCEC AER handling (Sean V Kelley)

- Add pcie_walk_rcec() for RCEC PME handling (Sean V Kelley)

- Add RCEC AER error injection support (Qiuxu Zhuo)

* pci/err:
  PCI/AER: Add RCEC AER error injection support
  PCI/PME: Add pcie_walk_rcec() to RCEC PME handling
  PCI/AER: Add pcie_walk_rcec() to RCEC AER handling
  PCI/ERR: Recover from RCiEP AER errors
  PCI/ERR: Add pcie_link_rcec() to associate RCiEPs
  PCI/ERR: Recover from RCEC AER errors
  PCI/ERR: Clear AER status only when we control AER
  PCI/ERR: Add pci_walk_bridge() to pcie_do_recovery()
  PCI/ERR: Avoid negated conditional for clarity
  PCI/ERR: Use "bridge" for clarity in pcie_do_recovery()
  PCI/ERR: Simplify by computing pci_pcie_type() once
  PCI/ERR: Simplify by using pci_upstream_bridge()
  PCI/ERR: Rename reset_link() to reset_subordinates()
  PCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities()
  PCI/ERR: Bind RCEC devices to the Root Port driver
  PCI/AER: Write AER Capability only when we control it

3 months agoMerge branch 'pci/enumeration'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:06 +0000 (15:11 -0600)]
Merge branch 'pci/enumeration'

- Decode PCIe 64 GT/s link speed (Gustavo Pimentel)

- De-duplicate Device IDs in the driver dynamic IDs list (Zhenzhong Duan)

- Return u8 from pci_find_capability() and similar (Puranjay Mohan)

- Return u16 from pci_find_ext_capability() and similar (Bjorn Helgaas)

- Include both device and resource name in config space resources
  (Alexander Lobakin)

- Fix ACPI companion lookup for device 0 on the root bus (Rafael J.
  Wysocki)

* pci/enumeration:
  PCI/ACPI: Fix companion lookup for device 0 on the root bus
  PCI: Keep both device and resource name for config space remaps
  PCI: Return u16 from pci_find_ext_capability() and similar
  PCI: Return u8 from pci_find_capability() and similar
  PCI: Avoid duplicate IDs in driver dynamic IDs list
  PCI: Move pci_match_device() ahead of new_id_store()
  PCI: Decode PCIe 64 GT/s link speed

3 months agoMerge branch 'pci/aspm'
Bjorn Helgaas [Tue, 15 Dec 2020 21:11:06 +0000 (15:11 -0600)]
Merge branch 'pci/aspm'

- Save/restore ASPM L1SS Capability for suspend/resume (Vidya Sagar)

* pci/aspm:
  PCI/ASPM: Save/restore L1SS Capability for suspend/resume

3 months agoPCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller
Bjorn Helgaas [Tue, 10 Nov 2020 22:00:57 +0000 (16:00 -0600)]
PCI: Add function 1 DMA alias quirk for Marvell 9215 SATA controller

Add function 1 DMA alias quirk for Marvell 88SS9215 PCIe SSD Controller.

Link: https://bugzilla.kernel.org/show_bug.cgi?id=42679#c135
Link: https://lore.kernel.org/r/20201110220516.697934-1-helgaas@kernel.org
Reported-by: John Smith <LK7S2ED64JHGLKj75shg9klejHWG49h5hk@protonmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI/ACPI: Fix companion lookup for device 0 on the root bus
Rafael J. Wysocki [Fri, 11 Dec 2020 20:17:35 +0000 (21:17 +0100)]
PCI/ACPI: Fix companion lookup for device 0 on the root bus

In some cases acpi_pci_find_companion() returns an incorrect device object
as the ACPI companion for device 0 on the root bus (bus 0).

On the affected systems that device is the PCI interface to the host bridge
and the "ACPI companion" returned for it corresponds to a non-PCI device
located in the SoC (e.g. a sensor on an I2C bus).  As a result of this, the
ACPI device object "attached" to PCI device 00:00.0 cannot be used for
enumerating the device that is really represented by it which (of course)
is problematic.

Address that issue by preventing acpi_pci_find_companion() from returning a
device object with a valid _HID (which by the spec should not be present
uder ACPI device objects corresponding to PCI devices) for PCI device
00:00.0.

[bhelgaas: use pci_is_root_bus()]
Link: https://lore.kernel.org/linux-acpi/1409ba0c-1580-dc09-e6fe-a0c9bcda6462@gmail.com/
Link: https://lore.kernel.org/r/4673285.9aE2nYKHPr@kreacher
Reported-by: Daniel Scally <djrscally@gmail.com>
Tested-by: Daniel Scally <djrscally@gmail.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Daniel Scally <djrscally@gmail.com>
3 months agoPCI: Keep both device and resource name for config space remaps
Alexander Lobakin [Thu, 19 Nov 2020 21:26:33 +0000 (21:26 +0000)]
PCI: Keep both device and resource name for config space remaps

Follow the rule taken in commit 35bd8c07db2c ("devres: keep both device
name and resource name in pretty name") and keep both device and resource
names while requesting memory regions for PCI config space to prettify e.g.
/proc/iomem output:

Before (DWC Host Controller):

  18b00000-18b01fff : dbi
  18b10000-18b11fff : config
  18b20000-18b21fff : dbi
  18b30000-18b31fff : config

After:

  18b00000-18b01fff : 18b00000.pci dbi
  18b10000-18b11fff : 18b00000.pci config
  18b20000-18b21fff : 18b20000.pci dbi
  18b30000-18b31fff : 18b20000.pci config

Link: https://lore.kernel.org/r/WbKfdybjZ6xNIUjcC5oC8NcuLqrJfkxQAlnO80ag@cp3-web-020.plabs.ch
Signed-off-by: Alexander Lobakin <alobakin@pm.me>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c
Krzysztof Wilczyński [Sun, 29 Nov 2020 23:07:43 +0000 (23:07 +0000)]
PCI: xgene: Removed unused ".bus_shift" initialisers from pci-xgene.c

Removed unused ".bus_shift" initialisers from pci-xgene.c as
xgene_pcie_map_bus() did not use these.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-6-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: vmd: Update type of the __iomem pointers
Krzysztof Wilczyński [Sun, 29 Nov 2020 23:07:42 +0000 (23:07 +0000)]
PCI: vmd: Update type of the __iomem pointers

Use "void __iomem" instead "char __iomem" pointer type when working with
the accessor functions (with names like readb() or writel(), etc.) to
better match a given accessor function signature where commonly the address
pointing to an I/O memory region would be a "void __iomem" pointer.

Related: https://lwn.net/Articles/102232/

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-5-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
3 months agoPCI: iproc: Convert to use the new ECAM constants
Krzysztof Wilczyński [Sun, 29 Nov 2020 23:07:41 +0000 (23:07 +0000)]
PCI: iproc: Convert to use the new ECAM constants

Change interface of the function iproc_pcie_map_ep_cfg_reg() so that use
of PCI_SLOT() and PCI_FUNC() macros and most of the local ECAM-specific
constants can be dropped, and the new PCIE_ECAM_OFFSET() macro can be
used instead.  Use the ALIGN_DOWN() macro to ensure that PCI Express
ECAM offset is always 32 bit aligned.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-4-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: thunder-pem: Add constant for custom ".bus_shift" initialiser
Krzysztof Wilczyński [Sun, 29 Nov 2020 23:07:40 +0000 (23:07 +0000)]
PCI: thunder-pem: Add constant for custom ".bus_shift" initialiser

Add a custom constant for the ".bus_shift" initialiser to capture a
non-standard platform-specific ECAM bus shift value.

Standard values otherwise defined in the PCI Express Specification are
available in the include/linux/pci-ecam.h.

Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-3-kw@linux.com
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: Unify ECAM constants in native PCI Express drivers
Krzysztof Wilczyński [Sun, 29 Nov 2020 23:07:39 +0000 (23:07 +0000)]
PCI: Unify ECAM constants in native PCI Express drivers

Add ECAM-related constants to provide a set of standard constants
defining memory address shift values to the byte-level address that can
be used to access the PCI Express Configuration Space, and then move
native PCI Express controller drivers to use the newly introduced
definitions retiring driver-specific ones.

Refactor pci_ecam_map_bus() function to use newly added constants so
that limits to the bus, device function and offset (now limited to 4K as
per the specification) are in place to prevent the defective or
malicious caller from supplying incorrect configuration offset and thus
targeting the wrong device when accessing extended configuration space.

This refactor also allows for the ".bus_shift" initialisers to be
dropped when the user is not using a custom value as a default value
will be used as per the PCI Express Specification.

Thanks to Qian Cai <qcai@redhat.com>, Michael Walle <michael@walle.cc>,
and Vladimir Oltean <olteanv@gmail.com> for reporting a pci_ecam_create()
issue with .bus_shift and to Vladimir for proposing the fix.

[bhelgaas: incorporate Vladimir's fix, update commit log]
Suggested-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://lore.kernel.org/r/20201129230743.3006978-2-kw@linux.com
Tested-by: Michael Walle <michael@walle.cc>
Signed-off-by: Krzysztof Wilczyński <kw@linux.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jon Derrick <jonathan.derrick@intel.com>
Reviewed-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: Disable PTM during suspend to save power
David E. Box [Mon, 7 Dec 2020 22:39:51 +0000 (14:39 -0800)]
PCI: Disable PTM during suspend to save power

There are systems (for example, Intel based mobile platforms since Coffee
Lake) where the power drawn while suspended can be significantly reduced by
disabling Precision Time Measurement (PTM) on PCIe root ports as this
allows the port to enter a lower-power PM state and the SoC to reach a
lower-power idle state. To save this power, disable the PTM feature on root
ports during pci_prepare_to_sleep() and pci_finish_runtime_suspend().  The
feature will be returned to its previous state during restore and error
recovery.

Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=209361
Link: https://lore.kernel.org/r/20201207223951.19667-2-david.e.box@linux.intel.com
Reported-by: Len Brown <len.brown@intel.com>
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume
David E. Box [Mon, 7 Dec 2020 22:39:50 +0000 (14:39 -0800)]
PCI/PTM: Save/restore Precision Time Measurement Capability for suspend/resume

The PCI subsystem does not currently save and restore the configuration
space for the Precision Time Measurement (PTM) Extended Capability leading
to the possibility of the feature returning disabled on S3 resume.  This
has been observed on Intel Coffee Lake desktops. Add save/restore of the
PTM control register. This saves the PTM Enable, Root Select, and Effective
Granularity bits.

Suggested-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Link: https://lore.kernel.org/r/20201207223951.19667-1-david.e.box@linux.intel.com
Signed-off-by: David E. Box <david.e.box@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: Mark AMD Raven iGPU ATS as broken in some platforms
Alex Deucher [Thu, 10 Dec 2020 16:08:47 +0000 (10:08 -0600)]
PCI: Mark AMD Raven iGPU ATS as broken in some platforms

Edgar reported [1] AMD Raven iGPU errors on several of his systems.  There
is no root cause.  Turn off ATS on these systems to avoid the issue.

[1] https://lore.kernel.org/linux-iommu/MWHPR10MB1310CDB6829DDCF5EA84A14689150@MWHPR10MB1310.namprd10.prod.outlook.com/

[bhelgaas: commit log]
Link: https://lore.kernel.org/r/MWHPR10MB131082779A86BE4CCCF190B789CB0@MWHPR10MB1310.namprd10.prod.outlook.com
Reported-by: Edgar Merger <Edgar.Merger@emerson.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
3 months agoPCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg
Kishon Vijay Abraham I [Thu, 10 Dec 2020 12:49:17 +0000 (18:19 +0530)]
PCI: j721e: Get offset within "syscon" from "ti,syscon-pcie-ctrl" phandle arg

Get "syscon" pcie_ctrl offset from the argument of "ti,syscon-pcie-ctrl"
phandle. Previously a subnode to "syscon" node was added which has the
exact memory mapped address of pcie_ctrl but now the offset of pcie_ctrl
within "syscon" is now being passed as argument to "ti,syscon-pcie-ctrl"
phandle.

If the offset is not provided in "ti,syscon-pcie-ctrl", the
full memory mapped address of pcie_ctrl is used in order to maintain old
DT compatibility.

This change is as discussed in [1]

[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: https://lore.kernel.org/r/20201210124917.24185-5-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
3 months agodt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC
Kishon Vijay Abraham I [Thu, 10 Dec 2020 12:49:16 +0000 (18:19 +0530)]
dt-bindings: PCI: Add EP mode dt-bindings for TI's J7200 SoC

Add PCIe EP mode dt-bindings for TI's J7200 SoC.

Link: https://lore.kernel.org/r/20201210124917.24185-4-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
3 months agodt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC
Kishon Vijay Abraham I [Thu, 10 Dec 2020 12:49:15 +0000 (18:19 +0530)]
dt-bindings: PCI: Add host mode dt-bindings for TI's J7200 SoC

Add host mode dt-bindings for TI's J7200 SoC.

Link: https://lore.kernel.org/r/20201210124917.24185-3-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
3 months agodt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument
Kishon Vijay Abraham I [Thu, 10 Dec 2020 12:49:14 +0000 (18:19 +0530)]
dt-bindings: pci: ti,j721e: Fix "ti,syscon-pcie-ctrl" to take argument

Fix binding documentation of "ti,syscon-pcie-ctrl" to take phandle with
argument. The argument is the register offset within "syscon" used to
configure PCIe controller. This change is as discussed in [1]

[1] -> http://lore.kernel.org/r/CAL_JsqKiUcO76bo1GoepWM1TusJWoty_BRy2hFSgtEVMqtrvvQ@mail.gmail.com

Link: https://lore.kernel.org/r/20201210124917.24185-2-kishon@ti.com
Fixes: 431b53b81cdc ("dt-bindings: PCI: Add host mode dt-bindings for TI's J721E SoC")
Fixes: 45b39e928966 ("dt-bindings: PCI: Add EP mode dt-bindings for TI's J721E SoC")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
4 months agoPCI: dwc: Set 32-bit DMA mask for MSI target address allocation
Vidya Sagar [Tue, 17 Nov 2020 16:53:12 +0000 (22:23 +0530)]
PCI: dwc: Set 32-bit DMA mask for MSI target address allocation

Set DMA mask to 32-bit while allocating the MSI target address so that
the address is usable for both 32-bit and 64-bit MSI capable devices.
Throw a warning if it fails to set the mask to 32-bit to alert that
devices that are only 32-bit MSI capable may not work properly.

Link: https://lore.kernel.org/r/20201117165312.25847-1-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
4 months agoPCI: qcom: Add support for configuring BDF to SID mapping for SM8250
Manivannan Sadhasivam [Tue, 8 Dec 2020 12:14:02 +0000 (17:44 +0530)]
PCI: qcom: Add support for configuring BDF to SID mapping for SM8250

For SM8250, we need to write the BDF to SID mapping in PCIe controller
register space for proper working. This is accomplished by extracting
the BDF and SID values from "iommu-map" property in DT and writing those
in the register address calculated from the hash value of BDF. In case
of collisions, the index of the next entry will also be written.

For the sake of it, let's introduce a "config_sid" callback and do it
conditionally for SM8250.

Link: https://lore.kernel.org/r/20201208121402.178011-4-mani@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
4 months agoPCI: Reduce pci_set_cacheline_size() message to debug level
Heiner Kallweit [Tue, 8 Dec 2020 17:57:02 +0000 (18:57 +0100)]
PCI: Reduce pci_set_cacheline_size() message to debug level

Drivers like ehci_hcd and xhci_hcd use pci_set_mwi() and emit an annnoying
message like the following that results in user questions whether something
is broken:

  xhci_hcd 0000:00:15.0: cache line size of 64 is not supported

Root cause of the message is that on several chips the Cache Line Size
register is hard-wired to 0.

Change this message to debug level; an interested caller can still inform
the user (if deemed helpful) based on the return code.

Link: https://lore.kernel.org/r/be1ed3a2-98b9-ee1d-20b8-477f3d93961d@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: Remove unused HAVE_PCI_SET_MWI
Heiner Kallweit [Tue, 8 Dec 2020 12:16:22 +0000 (13:16 +0100)]
PCI: Remove unused HAVE_PCI_SET_MWI

Remove unused HAVE_PCI_SET_MWI.

Link: https://lore.kernel.org/r/03f20cac-708d-7897-c7c7-cb4e63cfd991@gmail.com
Signed-off-by: Heiner Kallweit <hkallweit1@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: qcom: Add SM8250 SoC support
Manivannan Sadhasivam [Tue, 8 Dec 2020 12:14:01 +0000 (17:44 +0530)]
PCI: qcom: Add SM8250 SoC support

The PCIe IP (rev 1.9.0) on SM8250 SoC is similar to the one used on
SDM845. Hence the support is added reusing the members of ops_2_7_0.
The key difference between ops_2_7_0 and ops_1_9_0 is the config_sid
callback, which will be added in successive commit.

Link: https://lore.kernel.org/r/20201208121402.178011-3-mani@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
4 months agodt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC
Manivannan Sadhasivam [Tue, 8 Dec 2020 12:14:00 +0000 (17:44 +0530)]
dt-bindings: pci: qcom: Document PCIe bindings for SM8250 SoC

Document the PCIe DT bindings for SM8250 SoC. The PCIe IP is similar to
the one used on SDM845, hence just add the compatible along with the
optional "atu" register region.

Link: https://lore.kernel.org/r/20201208121402.178011-2-mani@kernel.org
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
4 months agoPCI: tegra: Disable LTSSM during L2 entry
Vidya Sagar [Thu, 3 Dec 2020 13:34:51 +0000 (19:04 +0530)]
PCI: tegra: Disable LTSSM during L2 entry

PCIe cards like Marvell SATA controller and some of the Samsung NVMe
drives don't support taking the link to L2 state. When the link doesn't
go to L2 state, Tegra194 requires the LTSSM to be disabled to allow PHY
to start the next link up process cleanly during suspend/resume sequence.
Failing to disable LTSSM results in the PCIe link not coming up in the
next resume cycle.

Link: https://lore.kernel.org/r/20201203133451.17716-6-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI: tegra: Check return value of tegra_pcie_init_controller()
Vidya Sagar [Thu, 3 Dec 2020 13:34:50 +0000 (19:04 +0530)]
PCI: tegra: Check return value of tegra_pcie_init_controller()

The return value of tegra_pcie_init_controller() must be checked before
PCIe link up check and registering debugfs entries subsequently as it
doesn't make sense to do these when the controller initialization itself
has failed.

Link: https://lore.kernel.org/r/20201203133451.17716-5-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI: tegra: Continue unconfig sequence even if parts fail
Vidya Sagar [Thu, 3 Dec 2020 13:34:49 +0000 (19:04 +0530)]
PCI: tegra: Continue unconfig sequence even if parts fail

Currently the driver checks for error value of different APIs during the
uninitialization sequence. It just returns from there if there is any error
observed for one of those calls. Comparatively it is better to continue the
uninitialization sequence irrespective of whether some of them are
returning error. That way, it is more closer to complete uninitialization.

Link: https://lore.kernel.org/r/20201203133451.17716-4-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI: tegra: Set DesignWare IP version
Vidya Sagar [Thu, 3 Dec 2020 13:34:48 +0000 (19:04 +0530)]
PCI: tegra: Set DesignWare IP version

Set the DesignWare IP version for Tegra194 to 0x490A. This would be used
by the DesigWare sub-system to do any version specific configuration
(Ex:- TD bit programming for ECRC).

Link: https://lore.kernel.org/r/20201203133451.17716-3-vidyas@nvidia.com
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI: tegra: Fix ASPM-L1SS advertisement disable code
Vidya Sagar [Thu, 3 Dec 2020 13:34:47 +0000 (19:04 +0530)]
PCI: tegra: Fix ASPM-L1SS advertisement disable code

If the absence of CLKREQ# signal is indicated by the absence of
"supports-clkreq" in the device-tree node, current driver is disabling
the advertisement of ASPM-L1 Sub-States *before* the ASPM-L1 Sub-States
offset is correctly initialized. Since default value of the ASPM-L1SS
offset is zero, this is causing the Vendor-ID wrongly programmed to 0x10d2
instead of Nvidia's 0x10de thereby the quirks applicable for Tegra194 are
not being applied. This patch fixes this issue by refactoring the
code that disables the ASPM-L1SS advertisement.

Link: https://lore.kernel.org/r/20201203133451.17716-2-vidyas@nvidia.com
Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support")
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
4 months agoPCI: aardvark: Update comment about disabling link training
Pali Rohár [Wed, 2 Dec 2020 18:46:59 +0000 (19:46 +0100)]
PCI: aardvark: Update comment about disabling link training

According to PCI Express Base Specifications (rev 4.0, 6.6.1
"Conventional reset"), after fundamental reset a 100ms delay is needed
prior to enabling link training.

Update comment in code to reflect this requirement.

Link: https://lore.kernel.org/r/20201202184659.3795-1-pali@kernel.org
Signed-off-by: Pali Rohár <pali@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
4 months agoPCI/AER: Add RCEC AER error injection support
Qiuxu Zhuo [Sat, 21 Nov 2020 00:10:36 +0000 (16:10 -0800)]
PCI/AER: Add RCEC AER error injection support

Root Complex Event Collectors (RCEC) appear as peers to Root Ports and may
also have the AER capability.

Add RCEC support to the AER error injection driver.

Co-developed-by: Sean V Kelley <sean.v.kelley@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-16-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
4 months agoPCI/PME: Add pcie_walk_rcec() to RCEC PME handling
Sean V Kelley [Sat, 21 Nov 2020 00:10:35 +0000 (16:10 -0800)]
PCI/PME: Add pcie_walk_rcec() to RCEC PME handling

Root Complex Event Collectors (RCEC) appear as peers of Root Ports and also
have the PME capability. As with AER, there is a need to be able to walk
the RCiEPs associated with their RCEC for purposes of acting upon them with
callbacks.

Add RCEC support through the use of pcie_walk_rcec() to the current PME
service driver and attach the PME service driver to the RCEC device.

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-15-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI/AER: Add pcie_walk_rcec() to RCEC AER handling
Sean V Kelley [Sat, 21 Nov 2020 00:10:34 +0000 (16:10 -0800)]
PCI/AER: Add pcie_walk_rcec() to RCEC AER handling

Root Complex Event Collectors (RCEC) appear as peers to Root Ports and also
have the AER capability. In addition, actions need to be taken for
associated RCiEPs. In such cases the RCECs will need to be walked in order
to find and act upon their respective RCiEPs.

Extend the existing ability to link the RCECs with a walking function
pcie_walk_rcec(). Add RCEC support to the current AER service driver and
attach the AER service driver to the RCEC device.

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-14-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
4 months agoPCI/ERR: Recover from RCiEP AER errors
Qiuxu Zhuo [Sat, 21 Nov 2020 00:10:33 +0000 (16:10 -0800)]
PCI/ERR: Recover from RCiEP AER errors

Add support for handling AER errors detected by Root Complex Integrated
Endpoints (RCiEPs).  These errors are signaled to software natively via a
Root Complex Event Collector (RCEC) or non-natively via ACPI APEI if the
platform retains control of AER or uses a non-standard RCEC-like device.

When recovering from RCiEP errors, the Root Error Command and Status
registers are in the AER Capability of an associated RCEC (if any), not in
a Root Port.  In the non-native case, the platform is responsible for those
registers and we can't touch them.

[bhelgaas: commit log, etc]
Co-developed-by: Sean V Kelley <sean.v.kelley@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-13-sean.v.kelley@intel.com
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI/ERR: Add pcie_link_rcec() to associate RCiEPs
Sean V Kelley [Sat, 21 Nov 2020 00:10:32 +0000 (16:10 -0800)]
PCI/ERR: Add pcie_link_rcec() to associate RCiEPs

A Root Complex Event Collector terminates error and PME messages from
associated RCiEPs.

Use the RCEC Endpoint Association Extended Capability to identify
associated RCiEPs. Link the associated RCiEPs as the RCECs are enumerated.

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-12-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
4 months agoPCI/ERR: Recover from RCEC AER errors
Sean V Kelley [Wed, 2 Dec 2020 17:26:29 +0000 (11:26 -0600)]
PCI/ERR: Recover from RCEC AER errors

A Root Complex Event Collector (RCEC) collects and signals AER errors that
were detected by Root Complex Integrated Endpoints (RCiEPs), but it may
also signal errors it detects itself.  This is analogous to errors detected
and signaled by a Root Port.

Update the AER service driver to claim RCECs in addition to Root Ports.
Add support for handling RCEC-detected AER errors.  This does not
include handling RCiEP-detected errors that are signaled by the RCEC.

Note that we expect these errors only from the native AER and APEI paths,
not from DPC or EDR.

[bhelgaas: split from combined RCEC/RCiEP patch, commit log]
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: Fix pci_slot_release() NULL pointer dereference
Jubin Zhong [Wed, 2 Dec 2020 02:33:42 +0000 (10:33 +0800)]
PCI: Fix pci_slot_release() NULL pointer dereference

If kobject_init_and_add() fails, pci_slot_release() is called to delete
slot->list from parent->slots.  But slot->list hasn't been initialized
yet, so we dereference a NULL pointer:

  Unable to handle kernel NULL pointer dereference at virtual address
00000000
  ...
  CPU: 10 PID: 1 Comm: swapper/0 Not tainted 4.4.240 #197
  task: ffffeb398a45ef10 task.stack: ffffeb398a470000
  PC is at __list_del_entry_valid+0x5c/0xb0
  LR is at pci_slot_release+0x84/0xe4
  ...
  __list_del_entry_valid+0x5c/0xb0
  pci_slot_release+0x84/0xe4
  kobject_put+0x184/0x1c4
  pci_create_slot+0x17c/0x1b4
  __pci_hp_initialize+0x68/0xa4
  pciehp_probe+0x1a4/0x2fc
  pcie_port_probe_service+0x58/0x84
  driver_probe_device+0x320/0x470

Initialize slot->list before calling kobject_init_and_add() to avoid this.

Fixes: 8a94644b440e ("PCI: Fix pci_create_slot() reference count leak")
Link: https://lore.kernel.org/r/1606876422-117457-1-git-send-email-zhongjubin@huawei.com
Signed-off-by: Jubin Zhong <zhongjubin@huawei.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: stable@vger.kernel.org # v5.9+
4 months agoPCI/PM: Do not generate wakeup event when runtime resuming device
Mika Westerberg [Wed, 25 Nov 2020 09:07:32 +0000 (12:07 +0300)]
PCI/PM: Do not generate wakeup event when runtime resuming device

When a PCI bridge is runtime resumed from D3cold, we resume any downstream
devices as well.  Previously, we also generated a wakeup event for each
device even though this is not a wakeup signal coming from the hardware.

Normally this does not cause problems but when combined with
/sys/power/wakeup_count like using the steps below:

  # count=$(cat /sys/power/wakeup_count)
  # echo $count > /sys/power/wakeup_count
  # echo mem > /sys/power/state

The system suspend cycle might fail at this point if a PCI bridge that was
runtime suspended (D3cold) was runtime resumed for any reason. The runtime
resume calls pci_resume_bus(), which generates a wakeup event and increases
wakeup_count.

Since this is not a real wakeup event, remove the call to
pci_wakeup_event() from pci_resume_one().

[bhelgaas: reorder, commit log]
Link: https://lore.kernel.org/r/20201125090733.77782-1-mika.westerberg@linux.intel.com
Reported-by: Utkarsh Patel <utkarsh.h.patel@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
4 months agoPCI/PM: Rename pci_wakeup_bus() to pci_resume_bus()
Mika Westerberg [Wed, 25 Nov 2020 09:07:33 +0000 (12:07 +0300)]
PCI/PM: Rename pci_wakeup_bus() to pci_resume_bus()

A "wakeup" is a signal from a device telling the system that the device or
the whole system should be awakened and made active.  PCI devices are made
active by "resuming" them.

pci_wakeup_bus() is not involved with the wakeup signal; it *resumes*
devices on a bus (possibly in response to a wakeup signal, but that's at a
higher level).

Rename pci_wakeup_bus() to pci_resume_bus() to better reflect what it does.
No functional change intended.

[bhelgaas: commit log, reorder before removal of pci_wakeup_event()]
Link: https://lore.kernel.org/r/20201125090733.77782-2-mika.westerberg@linux.intel.com
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
4 months agoPCI: Add sysfs attribute for device power state
Maximilian Luz [Mon, 2 Nov 2020 14:15:20 +0000 (15:15 +0100)]
PCI: Add sysfs attribute for device power state

While PCI power states D0-D3hot can be queried from user-space via lspci,
D3cold cannot.  lspci cannot provide an accurate value when the device is
in D3cold as it has to restore the device to D0 before it can access its
power state via the configuration space, leading to it reporting D0 or
another on-state. Thus lspci cannot be used to diagnose power consumption
issues for devices that can enter D3cold or to ensure that devices properly
enter D3cold at all.

Add a new sysfs device attribute for the PCI power state, showing the
current power state as seen by the kernel.

[bhelgaas: drop READ_ONCE(), see discussion at the link]
Link: https://lore.kernel.org/r/20201102141520.831630-1-luzmaximilian@gmail.com
Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: Return u16 from pci_find_ext_capability() and similar
Bjorn Helgaas [Fri, 4 Dec 2020 21:14:07 +0000 (15:14 -0600)]
PCI: Return u16 from pci_find_ext_capability() and similar

PCI Express Extended Capabilities are in config space between offsets 256
and 4K.  These offsets all fit in 16 bits.

Change the return type of pci_find_ext_capability() and supporting
functions from int to u16 to match the specification.  Many callers use
"int", which is fine, but there's no need to store more than a u16.

Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: Return u8 from pci_find_capability() and similar
Puranjay Mohan [Sun, 29 Nov 2020 16:46:26 +0000 (22:16 +0530)]
PCI: Return u8 from pci_find_capability() and similar

PCI Capabilities are linked in a list that must appear in the first 256
bytes of config space.  Each capabilities list pointer is 8 bits.

Change the return type of pci_find_capability() and supporting functions
from int to u8 to match the specification.

[bhelgaas: change other related interfaces, fix HyperTransport typos]
Link: https://lore.kernel.org/r/20201129164626.12887-1-puranjay12@gmail.com
Signed-off-by: Puranjay Mohan <puranjay12@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI/MSI: Set device flag indicating only 32-bit MSI support
Vidya Sagar [Thu, 3 Dec 2020 18:51:10 +0000 (12:51 -0600)]
PCI/MSI: Set device flag indicating only 32-bit MSI support

The MSI-X Capability requires devices to support 64-bit Message Addresses,
but the MSI Capability can support either 32- or 64-bit addresses.

Previously, we set dev->no_64bit_msi for a few broken devices that
advertise 64-bit MSI support but don't correctly support it.

In addition, check the MSI "64-bit Address Capable" bit for all devices and
set dev->no_64bit_msi for devices that don't advertise 64-bit support.
This allows msi_verify_entries() to catch arch code defects that assign
64-bit addresses when they're not supported.

The warning is helpful to find defects like the one fixed by
https://lore.kernel.org/r/20201117165312.25847-1-vidyas@nvidia.com

[bhelgaas: set no_64bit_msi in pci_msi_init(), commit log]
Link: https://lore.kernel.org/r/20201124105035.24573-1-vidyas@nvidia.com
Link: https://lore.kernel.org/r/20201203185110.1583077-4-helgaas@kernel.org
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI/MSI: Move MSI/MSI-X flags updaters to msi.c
Bjorn Helgaas [Thu, 3 Dec 2020 18:51:09 +0000 (12:51 -0600)]
PCI/MSI: Move MSI/MSI-X flags updaters to msi.c

pci_msi_set_enable() and pci_msix_clear_and_set_ctrl() are only used from
msi.c, so move them from drivers/pci/pci.h to msi.c.  No functional change
intended.

Link: https://lore.kernel.org/r/20201203185110.1583077-3-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI/MSI: Move MSI/MSI-X init to msi.c
Bjorn Helgaas [Thu, 3 Dec 2020 18:51:08 +0000 (12:51 -0600)]
PCI/MSI: Move MSI/MSI-X init to msi.c

Move pci_msi_setup_pci_dev(), which disables MSI and MSI-X interrupts, from
probe.c to msi.c so it's with all the other MSI code and more consistent
with other capability initialization.  This means we must compile msi.c
always, even without CONFIG_PCI_MSI, so wrap the rest of msi.c in an #ifdef
and adjust the Makefile accordingly.  No functional change intended.

Link: https://lore.kernel.org/r/20201203185110.1583077-2-helgaas@kernel.org
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI/ERR: Clear AER status only when we control AER
Sean V Kelley [Tue, 24 Nov 2020 16:55:30 +0000 (10:55 -0600)]
PCI/ERR: Clear AER status only when we control AER

In some cases a bridge may not exist as the hardware controlling may be
handled only by firmware and so is not visible to the OS. This scenario is
also possible in future use cases involving non-native use of RCECs by
firmware. In this scenario, we expect the platform to retain control of the
bridge and to clear error status itself.

Clear error status only when the OS has native control of AER.

Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI/ERR: Add pci_walk_bridge() to pcie_do_recovery()
Sean V Kelley [Sat, 21 Nov 2020 00:10:30 +0000 (16:10 -0800)]
PCI/ERR: Add pci_walk_bridge() to pcie_do_recovery()

Consolidate subordinate bus checks with pci_walk_bus() into
pci_walk_bridge() for walking below potentially AER affected bridges.

Link: https://lore.kernel.org/r/20201121001036.8560-10-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI/ERR: Avoid negated conditional for clarity
Sean V Kelley [Sat, 21 Nov 2020 00:10:29 +0000 (16:10 -0800)]
PCI/ERR: Avoid negated conditional for clarity

Reverse the sense of the Root Port/Downstream Port conditional for clarity.
No functional change intended.

Link: https://lore.kernel.org/r/20201121001036.8560-9-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
4 months agoPCI/ERR: Use "bridge" for clarity in pcie_do_recovery()
Sean V Kelley [Sat, 21 Nov 2020 00:10:28 +0000 (16:10 -0800)]
PCI/ERR: Use "bridge" for clarity in pcie_do_recovery()

pcie_do_recovery() may be called with "dev" being either a bridge (Root
Port or Switch Downstream Port) or an Endpoint.  The bulk of the function
deals with the bridge, so if we start with an Endpoint, we reset "dev" to
be the bridge leading to it.

For clarity, replace "dev" in the body of the function with "bridge".  No
functional change intended.

Link: https://lore.kernel.org/r/20201121001036.8560-8-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
4 months agoPCI/ERR: Simplify by computing pci_pcie_type() once
Sean V Kelley [Sat, 21 Nov 2020 00:10:27 +0000 (16:10 -0800)]
PCI/ERR: Simplify by computing pci_pcie_type() once

Instead of calling pci_pcie_type(dev) twice, call it once and save the
result.  No functional change intended.

Link: https://lore.kernel.org/r/20201121001036.8560-7-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
4 months agoPCI/ERR: Simplify by using pci_upstream_bridge()
Sean V Kelley [Sat, 21 Nov 2020 00:10:26 +0000 (16:10 -0800)]
PCI/ERR: Simplify by using pci_upstream_bridge()

Use pci_upstream_bridge() in place of dev->bus->self.  No functional change
intended.

Link: https://lore.kernel.org/r/20201121001036.8560-6-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
4 months agoPCI/ERR: Rename reset_link() to reset_subordinates()
Sean V Kelley [Sat, 21 Nov 2020 00:10:25 +0000 (16:10 -0800)]
PCI/ERR: Rename reset_link() to reset_subordinates()

reset_link() appears to be misnamed.  The point is to reset any devices
below a given bridge, so rename it to reset_subordinates() to make it clear
that we are passing a bridge with the intent to reset the devices below it.

Link: https://lore.kernel.org/r/20201121001036.8560-5-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
4 months agoPCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities()
Sean V Kelley [Sat, 21 Nov 2020 00:10:24 +0000 (16:10 -0800)]
PCI/ERR: Cache RCEC EA Capability offset in pci_init_capabilities()

Extend support for Root Complex Event Collectors by decoding and caching
the RCEC Endpoint Association Extended Capabilities when enumerating. Use
that cached information for later error source reporting. See PCIe r5.0,
sec 7.9.10.

Co-developed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-4-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
4 months agoPCI/ERR: Bind RCEC devices to the Root Port driver
Qiuxu Zhuo [Sat, 21 Nov 2020 00:10:23 +0000 (16:10 -0800)]
PCI/ERR: Bind RCEC devices to the Root Port driver

If a Root Complex Integrated Endpoint (RCiEP) is implemented, it may signal
errors through a Root Complex Event Collector (RCEC).  Each RCiEP must be
associated with no more than one RCEC.

For an RCEC (which is technically not a Bridge), error messages "received"
from associated RCiEPs must be enabled for "transmission" in order to cause
a System Error via the Root Control register or (when the Advanced Error
Reporting Capability is present) reporting via the Root Error Command
register and logging in the Root Error Status register and Error Source
Identification register.

Given the commonality with Root Ports and the need to also support AER and
PME services for RCECs, extend the Root Port driver to support RCEC devices
by adding the RCEC Class ID to the driver structure.

Co-developed-by: Sean V Kelley <sean.v.kelley@intel.com>
Link: https://lore.kernel.org/r/20201121001036.8560-3-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@linux.intel.com>
4 months agoPCI/AER: Write AER Capability only when we control it
Sean V Kelley [Sat, 21 Nov 2020 00:10:22 +0000 (16:10 -0800)]
PCI/AER: Write AER Capability only when we control it

If an OS has not been granted AER control via _OSC, it should not make
changes to PCI_ERR_ROOT_COMMAND and PCI_ERR_ROOT_STATUS related registers.
Per section 4.5.1 of the System Firmware Intermediary (SFI) _OSC and DPC
Updates ECN [1], this bit also covers these aspects of the PCI Express
Advanced Error Reporting. Based on the above and earlier discussion [2],
make the following changes:

Add a check for the native case (i.e., AER control via _OSC)

Note that the previous "clear, reset, enable" order suggests that the reset
might cause errors that we should ignore. After this commit, those errors
(if any) will remain logged in the PCI_ERR_ROOT_STATUS register.

[1] System Firmware Intermediary (SFI) _OSC and DPC Updates ECN, Feb 24,
    2020, affecting PCI Firmware Specification, Rev. 3.2
    https://members.pcisig.com/wg/PCI-SIG/document/14076
[2] https://lore.kernel.org/linux-pci/20201020162820.GA370938@bjorn-Precision-5520/

Link: https://lore.kernel.org/r/20201121001036.8560-2-sean.v.kelley@intel.com
Tested-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> # non-native/no RCEC
Signed-off-by: Sean V Kelley <sean.v.kelley@intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: tegra: Read "dbi" base address to program in application logic
Vidya Sagar [Wed, 25 Nov 2020 19:25:54 +0000 (00:55 +0530)]
PCI: tegra: Read "dbi" base address to program in application logic

PCIe controller in Tegra194 requires the "dbi" region base address to be
programmed in one of the application logic registers to enable CPU access
to the "dbi" region. But, commit a0fd361db8e5 ("PCI: dwc: Move "dbi",
"dbi2", and "addr_space" resource setup into common code") moved the code
that reads the whereabouts of "dbi" region to the common code causing the
existing code in pcie-tegra194.c file to program NULL in the application
logic registers. This is causing null pointer dereference when the "dbi"
registers are accessed. This issue is fixed by explicitly reading the
"dbi" base address from DT node.

Link: https://lore.kernel.org/r/20201125192554.5401-1-vidyas@nvidia.com
Fixes: a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code")
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI: tegra: Move "dbi" accesses to post common DWC initialization
Vidya Sagar [Wed, 25 Nov 2020 19:22:34 +0000 (00:52 +0530)]
PCI: tegra: Move "dbi" accesses to post common DWC initialization

commit a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space"
resource setup into common code") moved the code that sets up dbi_base
to DWC common code thereby creating a requirement to not access the "dbi"
region before calling common DWC initialization code. But, Tegra194
already had some code that programs some of the "dbi" registers resulting
in system crash. This patch addresses that issue by refactoring the code
to have accesses to the "dbi" region only after common DWC initialization.

Link: https://lore.kernel.org/r/20201125192234.2270-1-vidyas@nvidia.com
Fixes: a0fd361db8e5 ("PCI: dwc: Move "dbi", "dbi2", and "addr_space" resource setup into common code")
Tested-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Thierry Reding <treding@nvidia.com>
4 months agoPCI: dwc: exynos: Rework the driver to support Exynos5433 variant
Jaehoon Chung [Fri, 13 Nov 2020 17:01:39 +0000 (18:01 +0100)]
PCI: dwc: exynos: Rework the driver to support Exynos5433 variant

Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support DWC PCIe
variant found in the Exynos5433 SoCs.

The main difference in Exynos5433 variant is lack of the MSI support
(the MSI interrupt is not even routed to the CPU).

[mszyprow: reworked the driver to support only Exynos5433 variant,
   simplified code, rebased onto current kernel code, added
   regulator support, converted to the regular platform driver,
   removed MSI related code, rewrote commit message, added help]

Link: https://lore.kernel.org/r/20201113170139.29956-6-m.szyprowski@samsung.com
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Jingoo Han <jingoohan1@gmail.com>
4 months agoPCI: iproc: Enhance PCIe Link information display
Srinath Mannam [Thu, 1 Oct 2020 06:00:54 +0000 (11:30 +0530)]
PCI: iproc: Enhance PCIe Link information display

Add logging code so that after successful linkup more comprehensive
information about PCIe link speed and link width will be displayed to
the console.

Link: https://lore.kernel.org/r/20201001060054.6616-4-srinath.mannam@broadcom.com
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
4 months agoPCI: iproc: Invalidate correct PAXB inbound windows
Roman Bacik [Thu, 1 Oct 2020 06:00:53 +0000 (11:30 +0530)]
PCI: iproc: Invalidate correct PAXB inbound windows

Second stage bootloaders prior to Linux boot may use all inbound windows
including IARR1/IMAP1. We need to ensure that all previous configuration
of inbound windows are invalidated during the initialization stage of
the Linux iProc PCIe driver so let's add a fix to define and invalidate
IARR1/IMAP1 because it is currently missing, fixing the issue.

Link: https://lore.kernel.org/r/20201001060054.6616-3-srinath.mannam@broadcom.com
Fixes: 9415743e4c8a ("PCI: iproc: Invalidate PAXB address mapping")
Signed-off-by: Roman Bacik <roman.bacik@broadcom.com>
Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
[lorenzo.pieralisi@arm.com: commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
4 months agoPCI: iproc: Fix out-of-bound array accesses
Bharat Gooty [Thu, 1 Oct 2020 06:00:52 +0000 (11:30 +0530)]
PCI: iproc: Fix out-of-bound array accesses

Declare the full size array for all revisions of PAX register sets
to avoid potentially out of bound access of the register array
when they are being initialized in iproc_pcie_rev_init().

Link: https://lore.kernel.org/r/20201001060054.6616-2-srinath.mannam@broadcom.com
Fixes: 06324ede76cdf ("PCI: iproc: Improve core register population")
Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
4 months agoPCI: Fix overflow in command-line resource alignment requests
Colin Ian King [Sat, 14 Nov 2020 21:48:04 +0000 (15:48 -0600)]
PCI: Fix overflow in command-line resource alignment requests

The shift of 1 by align_order is evaluated using 32 bit arithmetic and the
result is assigned to a resource_size_t type variable that is a 64 bit
unsigned integer on 64 bit platforms. Fix an overflow before widening issue
by making the 1 a ULL.

Addresses-Coverity: ("Unintentional integer overflow")
Fixes: 32a9a682bef2 ("PCI: allow assignment of memory resources with a specified alignment")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Logan Gunthorpe <logang@deltatee.com>
4 months agoPCI: Bounds-check command-line resource alignment requests
Bjorn Helgaas [Thu, 5 Nov 2020 20:51:36 +0000 (14:51 -0600)]
PCI: Bounds-check command-line resource alignment requests

32-bit BARs are limited to 2GB size (2^31).  By extension, I assume 64-bit
BARs are limited to 2^63 bytes.  Limit the alignment requested by the
"pci=resource_alignment=" command-line parameter to 2^63.

Link: https://lore.kernel.org/r/20201007123045.GS4282@kadam
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: Fix kernel-doc markup
Mauro Carvalho Chehab [Fri, 23 Oct 2020 16:33:10 +0000 (18:33 +0200)]
PCI: Fix kernel-doc markup

Update kernel-doc so the names in the doc match the prototypes.

Link: https://lore.kernel.org/r/f19caf7a68f8365c8b573a42b4ac89ec21925c73.1603469755.git.mchehab+huawei@kernel.org
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agophy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY
Jaehoon Chung [Fri, 13 Nov 2020 17:01:38 +0000 (18:01 +0100)]
phy: samsung: phy-exynos-pcie: rework driver to support Exynos5433 PCIe PHY

Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Rework this driver to support PCIe PHY
variant found in the Exynos5433 SoCs.

[mszyprow: reworked the driver to support only Exynos5433 variant, rebased
   onto current kernel code, rewrote commit message]

Acked-By: Vinod Koul <vkoul@kernel.org>
Link: https://lore.kernel.org/r/20201113170139.29956-5-m.szyprowski@samsung.com
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
4 months agodt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding
Marek Szyprowski [Fri, 13 Nov 2020 17:01:37 +0000 (18:01 +0100)]
dt-bindings: phy: exynos: add the samsung,exynos-pcie-phy binding

Add dt-bindings for the Samsung Exynos PCIe PHY controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.

Link: https://lore.kernel.org/r/20201113170139.29956-4-m.szyprowski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
4 months agodt-bindings: PCI: exynos: add the samsung,exynos-pcie binding
Marek Szyprowski [Fri, 13 Nov 2020 17:01:36 +0000 (18:01 +0100)]
dt-bindings: PCI: exynos: add the samsung,exynos-pcie binding

Add dt-bindings for the Samsung Exynos PCIe controller (Exynos5433
variant). Based on the text dt-binding posted by Jaehoon Chung.

Link: https://lore.kernel.org/r/20201113170139.29956-3-m.szyprowski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Rob Herring <robh@kernel.org>
4 months agodt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding
Marek Szyprowski [Fri, 13 Nov 2020 17:01:35 +0000 (18:01 +0100)]
dt-bindings: PCI: exynos: drop samsung,exynos5440-pcie binding

Exynos5440 SoC support has been dropped since commit 8c83315da1cf ("ARM:
dts: exynos: Remove Exynos5440"). Drop the obsolete bindings for
exynos5440-pcie.

Link: https://lore.kernel.org/r/20201113170139.29956-2-m.szyprowski@samsung.com
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: Jingoo Han <jingoohan1@gmail.com>
4 months agoPCI: vmd: Offset Client VMD MSI-X vectors
Jon Derrick [Mon, 2 Nov 2020 22:22:23 +0000 (15:22 -0700)]
PCI: vmd: Offset Client VMD MSI-X vectors

Client VMD platforms have a software-triggered MSI-X vector 0 that will
not forward hardware-remapped MSI from the sub-device domain. This
causes an issue with VMD platforms that use AHCI behind VMD and have a
single MSI-X vector remapped to VMD vector 0. Add a VMD MSI-X vector
offset for these platforms.

Link: https://lore.kernel.org/r/20201102222223.92978-1-jonathan.derrick@intel.com
Tested-by: Jian-Hong Pan <jhp@endlessos.org>
Signed-off-by: Jon Derrick <jonathan.derrick@intel.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
4 months agoPCI: Avoid duplicate IDs in driver dynamic IDs list
Zhenzhong Duan [Tue, 17 Nov 2020 05:44:09 +0000 (13:44 +0800)]
PCI: Avoid duplicate IDs in driver dynamic IDs list

When a device ID is written to /sys/bus/pci/drivers/.../new_id, we
previously only checked the driver's static ID table for duplicates.
Writing the same ID several times added it to the dynamic IDs list several
times.

This doesn't cause user-visible broken behavior, but remove_id_store() only
removes one of the duplicate IDs, so if we add an ID several times, we
would have to remove it the same number of times before it's completely
gone.

Fix it by calling pci_match_device(), which checks both dynamic and static
IDs to avoid inserting duplicate IDs in dynamic IDs list.

After fix, attempts to add an ID more than once cause an error:

  # echo "1af4 1041" > /sys/bus/pci/drivers/vfio-pci/new_id
  # echo "1af4 1041" > /sys/bus/pci/drivers/vfio-pci/new_id
  bash: echo: write error: File exists

Link: https://lore.kernel.org/r/20201117054409.3428-3-zhenzhong.duan@gmail.com
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: Move pci_match_device() ahead of new_id_store()
Zhenzhong Duan [Tue, 17 Nov 2020 05:44:08 +0000 (13:44 +0800)]
PCI: Move pci_match_device() ahead of new_id_store()

Move pci_match_device() and its dependencies (pci_match_id() and
pci_device_id_any) ahead of new_id_store().

This is preparation work for calling pci_match_device() in new_id_store().
No functional changes.

[bhelgaas: update function comments]
Link: https://lore.kernel.org/r/20201117054409.3428-2-zhenzhong.duan@gmail.com
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: Decode PCIe 64 GT/s link speed
Gustavo Pimentel [Wed, 18 Nov 2020 22:49:20 +0000 (23:49 +0100)]
PCI: Decode PCIe 64 GT/s link speed

PCIe r6.0, sec 7.5.3.18, defines a new 64.0 GT/s bit in the Supported Link
Speeds Vector of Link Capabilities 2.

This patch does not affect the speed of the link, which should be
negotiated automatically by the hardware; it only adds decoding when
showing the speed to the user.

Decode this new speed.  Previously, reading the speed of a link operating
at this speed showed "Unknown speed" instead of "64.0 GT/s".

Link: https://lore.kernel.org/r/aaaab33fe18975e123a84aebce2adb85f44e2bbe.1605739760.git.gustavo.pimentel@synopsys.com
Signed-off-by: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Krzysztof Wilczyński <kw@linux.com>
4 months agoPCI: cadence: Do not error if "cdns,max-outbound-regions" is not found
Kishon Vijay Abraham I [Fri, 6 Nov 2020 15:11:07 +0000 (20:41 +0530)]
PCI: cadence: Do not error if "cdns,max-outbound-regions" is not found

Now that "cdns,max-outbound-regions" is made an optional property, do
not error out if "cdns,max-outbound-regions" device tree property is
not found.

Link: http://lore.kernel.org/r/20201105165331.GA55814@bogus
Link: https://lore.kernel.org/r/20201106151107.3987-3-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
4 months agodt-bindings: PCI: Make "cdns,max-outbound-regions" optional property
Kishon Vijay Abraham I [Fri, 6 Nov 2020 15:11:06 +0000 (20:41 +0530)]
dt-bindings: PCI: Make "cdns,max-outbound-regions" optional property

Make "cdns,max-outbound-regions" optional property with the default
being 32.

Link: http://lore.kernel.org/r/20201105165331.GA55814@bogus
Link: https://lore.kernel.org/r/20201106151107.3987-2-kishon@ti.com
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
4 months agodt-bindings: PCI: rcar-pci-host: Document r8a774e1 bindings
Lad Prabhakar [Wed, 4 Nov 2020 01:58:16 +0000 (10:58 +0900)]
dt-bindings: PCI: rcar-pci-host: Document r8a774e1 bindings

Document the RZ/G2H (a.k.a. R8A774E1) SoC in the R-Car PCIe bingings.

[shimoda: minor change the subject and description]

Link: https://lore.kernel.org/r/1604455096-13923-4-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
4 months agodt-bindings: PCI: rcar-pci-host: Document r8a77965 bindings
Yoshihiro Shimoda [Wed, 4 Nov 2020 01:58:15 +0000 (10:58 +0900)]
dt-bindings: PCI: rcar-pci-host: Document r8a77965 bindings

Document the R-Car M3-N (R8A77965) SoC in the R-Car PCIe bindings.

Link: https://lore.kernel.org/r/1604455096-13923-3-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Rob Herring <robh@kernel.org>
4 months agodt-bindings: PCI: rcar-pci-host: Convert bindings to json-schema
Yoshihiro Shimoda [Wed, 4 Nov 2020 01:58:14 +0000 (10:58 +0900)]
dt-bindings: PCI: rcar-pci-host: Convert bindings to json-schema

Convert Renesas PCIe Host controller bindings documentation to
json-schema. Note that some compatible doesn't contain on
the original documentation so that incremental patches are required
for it.

Link: https://lore.kernel.org/r/1604455096-13923-2-git-send-email-yoshihiro.shimoda.uh@renesas.com
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
4 months agoPCI: ibmphp: Remove unneeded break
Bjorn Helgaas [Thu, 5 Nov 2020 14:52:30 +0000 (08:52 -0600)]
PCI: ibmphp: Remove unneeded break

A break is not needed if it is preceded by a return.

Based on Tom Rix's treewide patch; this instance extracted from Joe
Perches' list.

Link: https://lore.kernel.org/r/20201017160928.12698-1-trix@redhat.com
Link: https://lore.kernel.org/r/f530b7aeecbbf9654b4540cfa20023a4c2a11889.camel@perches
.com
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Tom Rix <trix@redhat.com>
Cc: Joe Perches <joe@perches.com>
4 months agoPCI/ASPM: Save/restore L1SS Capability for suspend/resume
Vidya Sagar [Sat, 24 Oct 2020 19:04:42 +0000 (00:34 +0530)]
PCI/ASPM: Save/restore L1SS Capability for suspend/resume

Previously ASPM L1 Substates control registers (CTL1 and CTL2) weren't
saved and restored during suspend/resume leading to L1 Substates
configuration being lost post-resume.

Save the L1 Substates control registers so that the configuration is
retained post-resume.

Link: https://lore.kernel.org/r/20201024190442.871-1-vidyas@nvidia.com
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
4 months agoPCI: brcmstb: Initialize "tmp" before use
Jim Quinlan [Mon, 2 Nov 2020 20:57:12 +0000 (15:57 -0500)]
PCI: brcmstb: Initialize "tmp" before use

The variable 'tmp' is used multiple times in the brcm_pcie_setup()
function.  One such usage did not initialize 'tmp' to the current value
of the target register.  By luck the mistake does not currently affect
behavior;  regardless 'tmp' is now initialized properly.

Suggested-by: Rafał Miłecki <zajec5@gmail.com>
Link: https://lore.kernel.org/r/20201102205712.23332-1-james.quinlan@broadcom.com
Fixes: c0452137034b ("PCI: brcmstb: Add Broadcom STB PCIe host controller driver")
Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
4 months agoPCI: rcar: Drop unused members from struct rcar_pcie_host
Lad Prabhakar [Fri, 23 Oct 2020 16:20:08 +0000 (17:20 +0100)]
PCI: rcar: Drop unused members from struct rcar_pcie_host

Drop unused members dev and base from struct rcar_pcie_host.

Link: https://lore.kernel.org/r/20201023162008.967-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 months agoPCI: Use predefined Pericom Vendor ID
Andy Shevchenko [Fri, 6 Nov 2020 10:05:26 +0000 (12:05 +0200)]
PCI: Use predefined Pericom Vendor ID

Pericom has predefined Vendor ID, use it instead of hard-coded value.

Link: https://lore.kernel.org/r/20201106100526.17726-2-andriy.shevchenko@linux.intel.com
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>