tools arch x86: Sync the msr-index.h copy with the kernel sources

To pick up the changes in:

  d6a162a41bfd x86/msr-index: Add bunch of MSRs for Arch LBR
  ed7bde7a6dab cpufreq: intel_pstate: Allow enable/disable energy efficiency
  99e40204e014 (tip/x86/cleanups) x86/msr: Move the F15h MSRs where they belong
  1068ed4547ad x86/msr: Lift AMD family 0x15 power-specific MSRs
  5cde265384ca (tag: perf-core-2020-06-01) perf/x86/rapl: Add AMD Fam17h RAPL support

Addressing these tools/perf build warnings:

That makes the beautification scripts to pick some new entries:

  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > before
  $ cp arch/x86/include/asm/msr-index.h tools/arch/x86/include/asm/msr-index.h
  $ tools/perf/trace/beauty/tracepoints/x86_msr.sh > after
  $ diff -u before after
  --- before	2020-08-07 08:45:18.801298854 -0300
  +++ after	2020-08-07 08:45:28.654456422 -0300
  @@ -271,6 +271,8 @@
   	[0xc0010062 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PERF_CTL",
   	[0xc0010063 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PERF_STATUS",
   	[0xc0010064 - x86_AMD_V_KVM_MSRs_offset] = "AMD_PSTATE_DEF_BASE",
  +	[0xc001007a - x86_AMD_V_KVM_MSRs_offset] = "F15H_CU_PWR_ACCUMULATOR",
  +	[0xc001007b - x86_AMD_V_KVM_MSRs_offset] = "F15H_CU_MAX_PWR_ACCUMULATOR",
   	[0xc0010112 - x86_AMD_V_KVM_MSRs_offset] = "K8_TSEG_ADDR",
   	[0xc0010113 - x86_AMD_V_KVM_MSRs_offset] = "K8_TSEG_MASK",
   	[0xc0010114 - x86_AMD_V_KVM_MSRs_offset] = "VM_CR",
  $

And this gets rebuilt:

  CC       /tmp/build/perf/trace/beauty/tracepoints/x86_msr.o
  INSTALL  trace_plugins
  LD       /tmp/build/perf/trace/beauty/tracepoints/perf-in.o
  LD       /tmp/build/perf/trace/beauty/perf-in.o
  LD       /tmp/build/perf/perf-in.o
  LINK     /tmp/build/perf/perf

Now one can trace systemwide asking to see backtraces to where those
MSRs are being read/written with:

  # perf trace -e msr:*_msr/max-stack=32/ --filter="msr==F15H_CU_PWR_ACCUMULATOR || msr==F15H_CU_MAX_PWR_ACCUMULATOR"
  ^C#
  #

If we use -v (verbose mode) we can see what it does behind the scenes:

  # perf trace -v -e msr:*_msr/max-stack=32/ --filter="msr==F15H_CU_PWR_ACCUMULATOR || msr==F15H_CU_MAX_PWR_ACCUMULATOR"
  Using CPUID GenuineIntel-6-8E-A
  0xc001007a
  0xc001007b
  New filter for msr:read_msr: (msr==0xc001007a || msr==0xc001007b) && (common_pid != 2448054 && common_pid != 2782)
  0xc001007a
  0xc001007b
  New filter for msr:write_msr: (msr==0xc001007a || msr==0xc001007b) && (common_pid != 2448054 && common_pid != 2782)
  mmap size 528384B
  ^C#

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: Ingo Molnar <mingo@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Kan Liang <kan.liang@linux.intel.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>
Cc: Stephane Eranian <eranian@google.com>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index e8370e6..2859ee4 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -149,6 +149,10 @@
 
 #define MSR_LBR_SELECT                 0x000001c8
 #define MSR_LBR_TOS                    0x000001c9
+
+#define MSR_IA32_POWER_CTL             0x000001fc
+#define MSR_IA32_POWER_CTL_BIT_EE      19
+
 #define MSR_LBR_NHM_FROM               0x00000680
 #define MSR_LBR_NHM_TO                 0x000006c0
 #define MSR_LBR_CORE_FROM              0x00000040
@@ -158,7 +162,23 @@
 #define LBR_INFO_MISPRED               BIT_ULL(63)
 #define LBR_INFO_IN_TX                 BIT_ULL(62)
 #define LBR_INFO_ABORT                 BIT_ULL(61)
+#define LBR_INFO_CYC_CNT_VALID         BIT_ULL(60)
 #define LBR_INFO_CYCLES                        0xffff
+#define LBR_INFO_BR_TYPE_OFFSET                56
+#define LBR_INFO_BR_TYPE               (0xfull << LBR_INFO_BR_TYPE_OFFSET)
+
+#define MSR_ARCH_LBR_CTL               0x000014ce
+#define ARCH_LBR_CTL_LBREN             BIT(0)
+#define ARCH_LBR_CTL_CPL_OFFSET                1
+#define ARCH_LBR_CTL_CPL               (0x3ull << ARCH_LBR_CTL_CPL_OFFSET)
+#define ARCH_LBR_CTL_STACK_OFFSET      3
+#define ARCH_LBR_CTL_STACK             (0x1ull << ARCH_LBR_CTL_STACK_OFFSET)
+#define ARCH_LBR_CTL_FILTER_OFFSET     16
+#define ARCH_LBR_CTL_FILTER            (0x7full << ARCH_LBR_CTL_FILTER_OFFSET)
+#define MSR_ARCH_LBR_DEPTH             0x000014cf
+#define MSR_ARCH_LBR_FROM_0            0x00001500
+#define MSR_ARCH_LBR_TO_0              0x00001600
+#define MSR_ARCH_LBR_INFO_0            0x00001200
 
 #define MSR_IA32_PEBS_ENABLE           0x000003f1
 #define MSR_PEBS_DATA_CFG              0x000003f2
@@ -253,8 +273,6 @@
 
 #define MSR_PEBS_FRONTEND              0x000003f7
 
-#define MSR_IA32_POWER_CTL             0x000001fc
-
 #define MSR_IA32_MC0_CTL               0x00000400
 #define MSR_IA32_MC0_STATUS            0x00000401
 #define MSR_IA32_MC0_ADDR              0x00000402
@@ -418,7 +436,6 @@
 #define MSR_AMD64_PATCH_LEVEL          0x0000008b
 #define MSR_AMD64_TSC_RATIO            0xc0000104
 #define MSR_AMD64_NB_CFG               0xc001001f
-#define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_PATCH_LOADER         0xc0010020
 #define MSR_AMD_PERF_CTL               0xc0010062
 #define MSR_AMD_PERF_STATUS            0xc0010063
@@ -427,6 +444,7 @@
 #define MSR_AMD64_OSVW_STATUS          0xc0010141
 #define MSR_AMD_PPIN_CTL               0xc00102f0
 #define MSR_AMD_PPIN                   0xc00102f1
+#define MSR_AMD64_CPUID_FN_1           0xc0011004
 #define MSR_AMD64_LS_CFG               0xc0011020
 #define MSR_AMD64_DC_CFG               0xc0011022
 #define MSR_AMD64_BU_CFG2              0xc001102a
@@ -466,6 +484,8 @@
 #define MSR_F16H_DR0_ADDR_MASK         0xc0011027
 
 /* Fam 15h MSRs */
+#define MSR_F15H_CU_PWR_ACCUMULATOR     0xc001007a
+#define MSR_F15H_CU_MAX_PWR_ACCUMULATOR 0xc001007b
 #define MSR_F15H_PERF_CTL              0xc0010200
 #define MSR_F15H_PERF_CTL0             MSR_F15H_PERF_CTL
 #define MSR_F15H_PERF_CTL1             (MSR_F15H_PERF_CTL + 2)