return -ENOMEM;
clk->shift = shift;
- clk->name = node->name;
+ clk->name = ti_dt_clk_name(node);
ret = ti_clk_get_reg_addr(node, 0, &clk->reg);
if (ret) {
kfree(clk);
struct dra7_atl_desc *clk_hw = NULL;
struct clk_init_data init = { NULL };
const char **parent_names = NULL;
+ const char *name;
struct clk *clk;
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
clk_hw->hw.init = &init;
clk_hw->divider = 1;
- init.name = node->name;
+ name = ti_dt_clk_name(node);
+ init.name = name;
init.ops = &atl_clk_ops;
init.flags = CLK_IGNORE_UNUSED;
init.num_parents = of_clk_get_parent_count(node);
init.parent_names = parent_names;
- clk = ti_clk_register(NULL, &clk_hw->hw, node->name);
+ clk = ti_clk_register(NULL, &clk_hw->hw, name);
if (!IS_ERR(clk)) {
of_clk_add_provider(node, of_clk_src_simple_get, clk);
struct component_clk *comp;
int num_parents = 0;
const char **parent_names = NULL;
+ const char *name;
int i;
int ret;
goto cleanup;
}
- clk = clk_register_composite(NULL, node->name,
+ name = ti_dt_clk_name(node);
+ clk = clk_register_composite(NULL, name,
parent_names, num_parents,
_get_hw(cclk, CLK_COMPONENT_TYPE_MUX),
&ti_clk_mux_ops,
&ti_composite_gate_ops, 0);
if (!IS_ERR(clk)) {
- ret = ti_clk_add_alias(NULL, clk, node->name);
+ ret = ti_clk_add_alias(NULL, clk, name);
if (ret) {
clk_unregister(clk);
goto cleanup;
struct clk *clk;
struct clk_init_data init;
const char *parent_name;
+ const char *name;
parent_name = of_clk_get_parent_name(node, 0);
- init.name = node->name;
+ name = ti_dt_clk_name(node);
+ init.name = name;
init.ops = &ti_clk_divider_ops;
init.flags = flags;
init.parent_names = (parent_name ? &parent_name : NULL);
div->hw.init = &init;
/* register the clock */
- clk = ti_clk_register(NULL, &div->hw, node->name);
+ clk = ti_clk_register(NULL, &div->hw, name);
if (IS_ERR(clk))
kfree(div);
static void __init of_ti_fixed_factor_clk_setup(struct device_node *node)
{
struct clk *clk;
- const char *clk_name = node->name;
+ const char *clk_name = ti_dt_clk_name(node);
const char *parent_name;
u32 div, mult;
u32 flags = 0;
struct clk *clk;
const char *parent_name;
struct clk_omap_reg reg;
+ const char *name;
u8 enable_bit = 0;
u32 val;
u32 flags = 0;
if (of_property_read_bool(node, "ti,set-bit-to-disable"))
clk_gate_flags |= INVERT_ENABLE;
- clk = _register_gate(NULL, node->name, parent_name, flags, ®,
+ name = ti_dt_clk_name(node);
+ clk = _register_gate(NULL, name, parent_name, flags, ®,
enable_bit, clk_gate_flags, ops, hw_ops);
if (!IS_ERR(clk))
const char *parent_name;
struct clk_omap_reg reg;
u8 enable_bit = 0;
+ const char *name;
u32 val;
if (ti_clk_get_reg_addr(node, 0, ®))
return;
}
- clk = _register_interface(NULL, node->name, parent_name, ®,
+ name = ti_dt_clk_name(node);
+ clk = _register_interface(NULL, name, parent_name, ®,
enable_bit, ops);
if (!IS_ERR(clk))
struct clk_omap_reg reg;
unsigned int num_parents;
const char **parent_names;
+ const char *name;
u8 clk_mux_flags = 0;
u32 mask = 0;
u32 shift = 0;
mask = (1 << fls(mask)) - 1;
- clk = _register_mux(NULL, node->name, parent_names, num_parents,
+ name = ti_dt_clk_name(node);
+ clk = _register_mux(NULL, name, parent_names, num_parents,
flags, ®, shift, mask, latch, clk_mux_flags,
NULL);