Merge tag 'dmaengine-5.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma

Pull dmaengine updates from Vinod Koul:
 "Core:
   - Some code cleanup and optimization in core by Andy

   - Debugfs support for displaying dmaengine channels by Peter

  Drivers:
   - New driver for uniphier-xdmac controller

   - Updates to stm32 dma, mdma and dmamux drivers and PM support

   - More updates to idxd drivers

   - Bunch of changes in tegra-apb driver and cleaning up of pm
     functions

   - Bunch of spelling fixes and Replace zero-length array patches

   - Shutdown hook for fsl-dpaa2-qdma driver

   - Support for interleaved transfers for ti-edma and virtualization
     support for k3-dma driver

   - Support for reset and updates in xilinx_dma driver

   - Improvements and locking updates in at_hdma driver"

* tag 'dmaengine-5.7-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (89 commits)
  dt-bindings: dma: renesas,usb-dmac: add r8a77961 support
  dmaengine: uniphier-xdmac: Remove redandant error log for platform_get_irq
  dmaengine: tegra-apb: Improve DMA synchronization
  dmaengine: tegra-apb: Don't save/restore IRQ flags in interrupt handler
  dmaengine: tegra-apb: mark PM functions as __maybe_unused
  dmaengine: fix spelling mistake "exceds" -> "exceeds"
  dmaengine: sprd: Set request pending flag when DMA controller is active
  dmaengine: ppc4xx: Use scnprintf() for avoiding potential buffer overflow
  dmaengine: idxd: remove global token limit check
  dmaengine: idxd: reflect shadow copy of traffic class programming
  dmaengine: idxd: Merge definition of dsa_batch_desc into dsa_hw_desc
  dmaengine: Create debug directories for DMA devices
  dmaengine: ti: k3-udma: Implement custom dbg_summary_show for debugfs
  dmaengine: Add basic debugfs support
  dmaengine: fsl-dpaa2-qdma: remove set but not used variable 'dpaa2_qdma'
  dmaengine: ti: edma: fix null dereference because of a typo in pointer name
  dmaengine: fsl-dpaa2-qdma: Adding shutdown hook
  dmaengine: uniphier-xdmac: Add UniPhier external DMA controller driver
  dt-bindings: dmaengine: Add UniPhier external DMA controller bindings
  dmaengine: ti: k3-udma: Implement support for atype (for virtualization)
  ...

diff --cc Documentation/devicetree/bindings/dma/ti/k3-udma.yaml
Simple merge

diff --cc drivers/dma/dmaengine.c
Simple merge

diff --cc drivers/dma/idxd/cdev.c
index 989b7a2,8f323e7..ff49847
--- 1/drivers/dma/idxd/cdev.c
--- 2/drivers/dma/idxd/cdev.c
+++ b/drivers/dma/idxd/cdev.c
@@@ -79,11 -78,10 +78,10 @@@ static int idxd_cdev_open(struct inode 
        wq = inode_wq(inode);
        idxd = wq->idxd;
        dev = &idxd->pdev->dev;
-       idxd_cdev = &wq->idxd_cdev;
  
 -      dev_dbg(dev, "%s called\n", __func__);
 +      dev_dbg(dev, "%s called: %d\n", __func__, idxd_wq_refcount(wq));
  
 -      if (idxd_wq_refcount(wq) > 1 && wq_dedicated(wq))
 +      if (idxd_wq_refcount(wq) > 0 && wq_dedicated(wq))
                return -EBUSY;
  
        ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);

diff --cc drivers/dma/idxd/sysfs.c
Simple merge

diff --cc drivers/dma/tegra20-apb-dma.c
Simple merge

diff --cc drivers/dma/ti/k3-udma-glue.c
Simple merge

diff --cc drivers/dma/ti/k3-udma.c
index 0536866,1e6aac8..a9c0251
--- 1/drivers/dma/ti/k3-udma.c
--- 2/drivers/dma/ti/k3-udma.c
+++ b/drivers/dma/ti/k3-udma.c
@@@ -149,8 -128,19 +149,9 @@@ struct udma_dev 
  
        struct udma_chan *channels;
        u32 psil_base;
+       u32 atype;
  };
  
 -struct udma_hwdesc {
 -      size_t cppi5_desc_size;
 -      void *cppi5_desc_vaddr;
 -      dma_addr_t cppi5_desc_paddr;
 -
 -      /* TR descriptor internal pointers */
 -      void *tr_req_base;
 -      struct cppi5_tr_resp_t *tr_resp_base;
 -};
 -
  struct udma_desc {
        struct virt_dma_desc vd;
  
@@@ -3381,98 -3276,66 +3409,158 @@@ static int udma_setup_resources(struct 
        return ch_count;
  }
  
 +static int udma_setup_rx_flush(struct udma_dev *ud)
 +{
 +      struct udma_rx_flush *rx_flush = &ud->rx_flush;
 +      struct cppi5_desc_hdr_t *tr_desc;
 +      struct cppi5_tr_type1_t *tr_req;
 +      struct cppi5_host_desc_t *desc;
 +      struct device *dev = ud->dev;
 +      struct udma_hwdesc *hwdesc;
 +      size_t tr_size;
 +
 +      /* Allocate 1K buffer for discarded data on RX channel teardown */
 +      rx_flush->buffer_size = SZ_1K;
 +      rx_flush->buffer_vaddr = devm_kzalloc(dev, rx_flush->buffer_size,
 +                                            GFP_KERNEL);
 +      if (!rx_flush->buffer_vaddr)
 +              return -ENOMEM;
 +
 +      rx_flush->buffer_paddr = dma_map_single(dev, rx_flush->buffer_vaddr,
 +                                              rx_flush->buffer_size,
 +                                              DMA_TO_DEVICE);
 +      if (dma_mapping_error(dev, rx_flush->buffer_paddr))
 +              return -ENOMEM;
 +
 +      /* Set up descriptor to be used for TR mode */
 +      hwdesc = &rx_flush->hwdescs[0];
 +      tr_size = sizeof(struct cppi5_tr_type1_t);
 +      hwdesc->cppi5_desc_size = cppi5_trdesc_calc_size(tr_size, 1);
 +      hwdesc->cppi5_desc_size = ALIGN(hwdesc->cppi5_desc_size,
 +                                      ud->desc_align);
 +
 +      hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
 +                                              GFP_KERNEL);
 +      if (!hwdesc->cppi5_desc_vaddr)
 +              return -ENOMEM;
 +
 +      hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
 +                                                hwdesc->cppi5_desc_size,
 +                                                DMA_TO_DEVICE);
 +      if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
 +              return -ENOMEM;
 +
 +      /* Start of the TR req records */
 +      hwdesc->tr_req_base = hwdesc->cppi5_desc_vaddr + tr_size;
 +      /* Start address of the TR response array */
 +      hwdesc->tr_resp_base = hwdesc->tr_req_base + tr_size;
 +
 +      tr_desc = hwdesc->cppi5_desc_vaddr;
 +      cppi5_trdesc_init(tr_desc, 1, tr_size, 0, 0);
 +      cppi5_desc_set_pktids(tr_desc, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
 +      cppi5_desc_set_retpolicy(tr_desc, 0, 0);
 +
 +      tr_req = hwdesc->tr_req_base;
 +      cppi5_tr_init(&tr_req->flags, CPPI5_TR_TYPE1, false, false,
 +                    CPPI5_TR_EVENT_SIZE_COMPLETION, 0);
 +      cppi5_tr_csf_set(&tr_req->flags, CPPI5_TR_CSF_SUPR_EVT);
 +
 +      tr_req->addr = rx_flush->buffer_paddr;
 +      tr_req->icnt0 = rx_flush->buffer_size;
 +      tr_req->icnt1 = 1;
 +
 +      /* Set up descriptor to be used for packet mode */
 +      hwdesc = &rx_flush->hwdescs[1];
 +      hwdesc->cppi5_desc_size = ALIGN(sizeof(struct cppi5_host_desc_t) +
 +                                      CPPI5_INFO0_HDESC_EPIB_SIZE +
 +                                      CPPI5_INFO0_HDESC_PSDATA_MAX_SIZE,
 +                                      ud->desc_align);
 +
 +      hwdesc->cppi5_desc_vaddr = devm_kzalloc(dev, hwdesc->cppi5_desc_size,
 +                                              GFP_KERNEL);
 +      if (!hwdesc->cppi5_desc_vaddr)
 +              return -ENOMEM;
 +
 +      hwdesc->cppi5_desc_paddr = dma_map_single(dev, hwdesc->cppi5_desc_vaddr,
 +                                                hwdesc->cppi5_desc_size,
 +                                                DMA_TO_DEVICE);
 +      if (dma_mapping_error(dev, hwdesc->cppi5_desc_paddr))
 +              return -ENOMEM;
 +
 +      desc = hwdesc->cppi5_desc_vaddr;
 +      cppi5_hdesc_init(desc, 0, 0);
 +      cppi5_desc_set_pktids(&desc->hdr, 0, CPPI5_INFO1_DESC_FLOWID_DEFAULT);
 +      cppi5_desc_set_retpolicy(&desc->hdr, 0, 0);
 +
 +      cppi5_hdesc_attach_buf(desc,
 +                             rx_flush->buffer_paddr, rx_flush->buffer_size,
 +                             rx_flush->buffer_paddr, rx_flush->buffer_size);
 +
 +      dma_sync_single_for_device(dev, hwdesc->cppi5_desc_paddr,
 +                                 hwdesc->cppi5_desc_size, DMA_TO_DEVICE);
 +      return 0;
 +}
 +
+ #ifdef CONFIG_DEBUG_FS
+ static void udma_dbg_summary_show_chan(struct seq_file *s,
+                                      struct dma_chan *chan)
+ {
+       struct udma_chan *uc = to_udma_chan(chan);
+       struct udma_chan_config *ucc = &uc->config;
+ 
+       seq_printf(s, " %-13s| %s", dma_chan_name(chan),
+                  chan->dbg_client_name ?: "in-use");
+       seq_printf(s, " (%s, ", dmaengine_get_direction_text(uc->config.dir));
+ 
+       switch (uc->config.dir) {
+       case DMA_MEM_TO_MEM:
+               seq_printf(s, "chan%d pair [0x%04x -> 0x%04x], ", uc->tchan->id,
+                          ucc->src_thread, ucc->dst_thread);
+               break;
+       case DMA_DEV_TO_MEM:
+               seq_printf(s, "rchan%d [0x%04x -> 0x%04x], ", uc->rchan->id,
+                          ucc->src_thread, ucc->dst_thread);
+               break;
+       case DMA_MEM_TO_DEV:
+               seq_printf(s, "tchan%d [0x%04x -> 0x%04x], ", uc->tchan->id,
+                          ucc->src_thread, ucc->dst_thread);
+               break;
+       default:
+               seq_printf(s, ")\n");
+               return;
+       }
+ 
+       if (ucc->ep_type == PSIL_EP_NATIVE) {
+               seq_printf(s, "PSI-L Native");
+               if (ucc->metadata_size) {
+                       seq_printf(s, "[%s", ucc->needs_epib ? " EPIB" : "");
+                       if (ucc->psd_size)
+                               seq_printf(s, " PSDsize:%u", ucc->psd_size);
+                       seq_printf(s, " ]");
+               }
+       } else {
+               seq_printf(s, "PDMA");
+               if (ucc->enable_acc32 || ucc->enable_burst)
+                       seq_printf(s, "[%s%s ]",
+                                  ucc->enable_acc32 ? " ACC32" : "",
+                                  ucc->enable_burst ? " BURST" : "");
+       }
+ 
+       seq_printf(s, ", %s)\n", ucc->pkt_mode ? "Packet mode" : "TR mode");
+ }
+ 
+ static void udma_dbg_summary_show(struct seq_file *s,
+                                 struct dma_device *dma_dev)
+ {
+       struct dma_chan *chan;
+ 
+       list_for_each_entry(chan, &dma_dev->channels, device_node) {
+               if (chan->client_count)
+                       udma_dbg_summary_show_chan(s, chan);
+       }
+ }
+ #endif /* CONFIG_DEBUG_FS */
+ 
  #define TI_UDMAC_BUSWIDTHS    (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
                                 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
                                 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \