clk: at91: clk-master: add 5th divisor for mck master

clk-master can have 5 divisors with a field width of 3 bits
on some products.

Change the mask and number of divisors accordingly.

Reported-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/1605800597-16720-5-git-send-email-claudiu.beznea@microchip.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/at91/clk-master.c b/drivers/clk/at91/clk-master.c
index bd0d8a6..aafd003 100644 (file)
--- a/drivers/clk/at91/clk-master.c
+++ b/drivers/clk/at91/clk-master.c
@@ -15,7 +15,7 @@
 #define MASTER_PRES_MASK       0x7
 #define MASTER_PRES_MAX                MASTER_PRES_MASK
 #define MASTER_DIV_SHIFT       8
-#define MASTER_DIV_MASK                0x3
+#define MASTER_DIV_MASK                0x7
 
 #define PMC_MCR                        0x30
 #define PMC_MCR_ID_MSK         GENMASK(3, 0)

diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 7b86aff..0a9364b 100644 (file)
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -48,7 +48,7 @@ extern const struct clk_master_layout at91sam9x5_master_layout;
 
 struct clk_master_characteristics {
        struct clk_range output;
-       u32 divisors[4];
+       u32 divisors[5];
        u8 have_div3_pres;
 };