Merge branch 'kvm-arm64/pmu-debug-fixes-5.11' into kvmarm-master/next

Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --cc arch/arm64/kvm/pmu-emul.c
Simple merge

diff --cc arch/arm64/kvm/sys_regs.c
index 7c4f795,d9ca200..4f2f1e3
--- 1/arch/arm64/kvm/sys_regs.c
--- 2/arch/arm64/kvm/sys_regs.c
+++ b/arch/arm64/kvm/sys_regs.c
@@@ -1025,39 -1023,45 +1032,44 @@@ static bool access_arch_timer(struct kv
  static u64 read_id_reg(const struct kvm_vcpu *vcpu,
                struct sys_reg_desc const *r, bool raz)
  {
 -      u32 id = sys_reg((u32)r->Op0, (u32)r->Op1,
 -                       (u32)r->CRn, (u32)r->CRm, (u32)r->Op2);
 +      u32 id = reg_to_encoding(r);
        u64 val = raz ? 0 : read_sanitised_ftr_reg(id);
  
-       if (id == SYS_ID_AA64PFR0_EL1) {
+       switch (id) {
+       case SYS_ID_AA64PFR0_EL1:
                if (!vcpu_has_sve(vcpu))
-                       val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
-               val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
-               val &= ~(0xfUL << ID_AA64PFR0_CSV2_SHIFT);
-               val |= ((u64)vcpu->kvm->arch.pfr0_csv2 << ID_AA64PFR0_CSV2_SHIFT);
-               val &= ~(0xfUL << ID_AA64PFR0_CSV3_SHIFT);
-               val |= ((u64)vcpu->kvm->arch.pfr0_csv3 << ID_AA64PFR0_CSV3_SHIFT);
-       } else if (id == SYS_ID_AA64PFR1_EL1) {
-               val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT);
-       } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) {
-               val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) |
-                        (0xfUL << ID_AA64ISAR1_API_SHIFT) |
-                        (0xfUL << ID_AA64ISAR1_GPA_SHIFT) |
-                        (0xfUL << ID_AA64ISAR1_GPI_SHIFT));
-       } else if (id == SYS_ID_AA64DFR0_EL1) {
-               u64 cap = 0;
- 
-               /* Limit guests to PMUv3 for ARMv8.1 */
-               if (kvm_vcpu_has_pmu(vcpu))
-                       cap = ID_AA64DFR0_PMUVER_8_1;
- 
+                       val &= ~FEATURE(ID_AA64PFR0_SVE);
+               val &= ~FEATURE(ID_AA64PFR0_AMU);
+               val &= ~FEATURE(ID_AA64PFR0_CSV2);
+               val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV2), (u64)vcpu->kvm->arch.pfr0_csv2);
+               val &= ~FEATURE(ID_AA64PFR0_CSV3);
+               val |= FIELD_PREP(FEATURE(ID_AA64PFR0_CSV3), (u64)vcpu->kvm->arch.pfr0_csv3);
+               break;
+       case SYS_ID_AA64PFR1_EL1:
+               val &= ~FEATURE(ID_AA64PFR1_MTE);
+               break;
+       case SYS_ID_AA64ISAR1_EL1:
+               if (!vcpu_has_ptrauth(vcpu))
+                       val &= ~(FEATURE(ID_AA64ISAR1_APA) |
+                                FEATURE(ID_AA64ISAR1_API) |
+                                FEATURE(ID_AA64ISAR1_GPA) |
+                                FEATURE(ID_AA64ISAR1_GPI));
+               break;
+       case SYS_ID_AA64DFR0_EL1:
+               /* Limit debug to ARMv8.0 */
+               val &= ~FEATURE(ID_AA64DFR0_DEBUGVER);
+               val |= FIELD_PREP(FEATURE(ID_AA64DFR0_DEBUGVER), 6);
+               /* Limit guests to PMUv3 for ARMv8.4 */
                val = cpuid_feature_cap_perfmon_field(val,
-                                               ID_AA64DFR0_PMUVER_SHIFT,
-                                               cap);
-       } else if (id == SYS_ID_DFR0_EL1) {
-               /* Limit guests to PMUv3 for ARMv8.1 */
+                                                     ID_AA64DFR0_PMUVER_SHIFT,
+                                                     kvm_vcpu_has_pmu(vcpu) ? ID_AA64DFR0_PMUVER_8_4 : 0);
+               break;
+       case SYS_ID_DFR0_EL1:
+               /* Limit guests to PMUv3 for ARMv8.4 */
                val = cpuid_feature_cap_perfmon_field(val,
-                                               ID_DFR0_PERFMON_SHIFT,
-                                               ID_DFR0_PERFMON_8_1);
+                                                     ID_DFR0_PERFMON_SHIFT,
+                                                     kvm_vcpu_has_pmu(vcpu) ? ID_DFR0_PERFMON_8_4 : 0);
+               break;
        }
  
        return val;
@@@ -1489,10 -1494,9 +1501,11 @@@ static const struct sys_reg_desc sys_re
        { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
        { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
  
 -      { SYS_DESC(SYS_PMINTENSET_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
 -      { SYS_DESC(SYS_PMINTENCLR_EL1), access_pminten, reset_unknown, PMINTENSET_EL1 },
 +      { PMU_SYS_REG(SYS_PMINTENSET_EL1),
 +        .access = access_pminten, .reg = PMINTENSET_EL1 },
 +      { PMU_SYS_REG(SYS_PMINTENCLR_EL1),
 +        .access = access_pminten, .reg = PMINTENSET_EL1 },
+       { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
  
        { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
        { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },