dt-bindings: Remove PicoXcell bindings
authorRob Herring <robh@kernel.org>
Thu, 10 Dec 2020 20:03:15 +0000 (14:03 -0600)
committerRob Herring <robh@kernel.org>
Mon, 14 Dec 2020 14:34:58 +0000 (08:34 -0600)
PicoXcell has had nothing but treewide cleanups for at least the last 8
years and no signs of activity. The most recent activity is a yocto vendor
kernel based on v3.0 in 2015.

Cc: linux-crypto@vger.kernel.org
Acked-by: Jamie Iles <jamie@jamieiles.com>
Link: https://lore.kernel.org/r/20201210200315.2965567-5-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Documentation/devicetree/bindings/arm/picoxcell.txt [deleted file]
Documentation/devicetree/bindings/crypto/picochip-spacc.txt [deleted file]
Documentation/devicetree/bindings/net/macb.txt
Documentation/devicetree/bindings/timer/snps,dw-apb-timer.yaml

diff --git a/Documentation/devicetree/bindings/arm/picoxcell.txt b/Documentation/devicetree/bindings/arm/picoxcell.txt
deleted file mode 100644 (file)
index e75c0ef..0000000
+++ /dev/null
@@ -1,24 +0,0 @@
-Picochip picoXcell device tree bindings.
-========================================
-
-Required root node properties:
-    - compatible:
-       - "picochip,pc7302-pc3x3" : PC7302 development board with PC3X3 device.
-       - "picochip,pc7302-pc3x2" : PC7302 development board with PC3X2 device.
-       - "picochip,pc3x3" : picoXcell PC3X3 device based board.
-       - "picochip,pc3x2" : picoXcell PC3X2 device based board.
-
-Timers required properties:
-    - compatible = "picochip,pc3x2-timer"
-    - interrupts : The single IRQ line for the timer.
-    - clock-freq : The frequency in HZ of the timer.
-    - reg : The register bank for the timer.
-
-Note: two timers are required - one for the scheduler clock and one for the
-event tick/NOHZ.
-
-VIC required properties:
-    - compatible = "arm,pl192-vic".
-    - interrupt-controller.
-    - reg : The register bank for the device.
-    - #interrupt-cells : Must be 1.
diff --git a/Documentation/devicetree/bindings/crypto/picochip-spacc.txt b/Documentation/devicetree/bindings/crypto/picochip-spacc.txt
deleted file mode 100644 (file)
index df1151f..0000000
+++ /dev/null
@@ -1,21 +0,0 @@
-Picochip picoXcell SPAcc (Security Protocol Accelerator) bindings
-
-Picochip picoXcell devices contain crypto offload engines that may be used for
-IPSEC and femtocell layer 2 ciphering.
-
-Required properties:
-  - compatible : "picochip,spacc-ipsec" for the IPSEC offload engine
-    "picochip,spacc-l2" for the femtocell layer 2 ciphering engine.
-  - reg : Offset and length of the register set for this device
-  - interrupts : The interrupt line from the SPAcc.
-  - ref-clock : The input clock that drives the SPAcc.
-
-Example SPAcc node:
-
-spacc@10000 {
-       compatible = "picochip,spacc-ipsec";
-       reg = <0x100000 0x10000>;
-       interrupt-parent = <&vic0>;
-       interrupts = <24>;
-       ref-clock = <&ipsec_clk>, "ref";
-};
index 0b61a90..46dc52c 100644 (file)
@@ -7,8 +7,6 @@ Required properties:
   Use "cdns,sam9x60-macb" for Microchip sam9x60 SoC.
   Use "cdns,np4-macb" for NP4 SoC devices.
   Use "cdns,at32ap7000-macb" for other 10/100 usage or use the generic form: "cdns,macb".
-  Use "cdns,pc302-gem" for Picochip picoXcell pc302 and later devices based on
-  the Cadence GEM, or the generic form: "cdns,gem".
   Use "atmel,sama5d2-gem" for the GEM IP (10/100) available on Atmel sama5d2 SoCs.
   Use "atmel,sama5d3-macb" for the 10/100Mbit IP available on Atmel sama5d3 SoCs.
   Use "atmel,sama5d3-gem" for the Gigabit IP available on Atmel sama5d3 SoCs.
index 2fc6173..d65faf2 100644 (file)
@@ -38,13 +38,6 @@ properties:
 
   clock-frequency: true
 
-  clock-freq:
-    $ref: "/schemas/types.yaml#/definitions/uint32"
-    description: |
-      Has the same meaning as the 'clock-frequency' property - timer clock
-      frequency in HZ, but is defined only for the backwards compatibility
-      with the picoxcell platform.
-
 additionalProperties: false
 
 required: