perf: riscv_pmu{,_sbi}: Miscallenous improvement & fixes

A series of mostly-independent fixes and cleanups for the RISC-V PMU
drivers.

Link: https://lore.kernel.org/lkml/CAAhSdy23vE8+HxU5Jxy2rBMjy3rBTrJt_4sriuROac_sEESSVw@mail.gmail.com/T/#m9de15aef1b65ae6155fa33ea1239578ef463c2a2
* palmer/riscv-pmu:
  RISC-V: Improve SBI definitions
  RISC-V: Move counter info definition to sbi header file
  RISC-V: Fix SBI PMU calls for RV32
  RISC-V: Update user page mapping only once during start
  RISC-V: Fix counter restart during overflow for RV32

diff --cc drivers/perf/riscv_pmu.c
Simple merge

diff --cc drivers/perf/riscv_pmu_sbi.c
index 79a3de5,2412454..6f6681b
--- 1/drivers/perf/riscv_pmu_sbi.c
--- 2/drivers/perf/riscv_pmu_sbi.c
+++ b/drivers/perf/riscv_pmu_sbi.c
@@@ -22,39 -21,6 +22,25 @@@
  #include <asm/sbi.h>
  #include <asm/hwcap.h>
  
- union sbi_pmu_ctr_info {
-       unsigned long value;
-       struct {
-               unsigned long csr:12;
-               unsigned long width:6;
- #if __riscv_xlen == 32
-               unsigned long reserved:13;
- #else
-               unsigned long reserved:45;
- #endif
-               unsigned long type:1;
-       };
- };
- 
 +PMU_FORMAT_ATTR(event, "config:0-47");
 +PMU_FORMAT_ATTR(firmware, "config:63");
 +
 +static struct attribute *riscv_arch_formats_attr[] = {
 +      &format_attr_event.attr,
 +      &format_attr_firmware.attr,
 +      NULL,
 +};
 +
 +static struct attribute_group riscv_pmu_format_group = {
 +      .name = "format",
 +      .attrs = riscv_arch_formats_attr,
 +};
 +
 +static const struct attribute_group *riscv_pmu_attr_groups[] = {
 +      &riscv_pmu_format_group,
 +      NULL,
 +};
 +
  /*
   * RISC-V doesn't have hetergenous harts yet. This need to be part of
   * per_cpu in case of harts with different pmu counters