MIPS: Loongson64: Fix wrong scache size when execute lscpu

As the user manual and code comment said, Loongson-3 has 4-scache banks,
while Loongson-2K has only 2 banks, so we should multiply the number of
scache banks, this multiply operation should be done by c->scache.sets
instead of scache_size, otherwise we will get the wrong scache size when
execute lscpu. For example, the scache size should be 8192K instead of
2048K on the Loongson 3A3000 and 3A4000 platform, we can see the related
info in the following boot message:

[loongson@linux ~]$ dmesg | grep "Unified secondary cache"
[    0.000000] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.061909] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.125629] Unified secondary cache 8192kB 16-way, linesize 64 bytes.
[    4.188379] Unified secondary cache 8192kB 16-way, linesize 64 bytes.

E.g. without this patch:

[loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size
2048K
2048K
2048K
2048K
[loongson@linux ~]$ lscpu | grep "L2 cache"
L2 cache:              2048K

With this patch:

[loongson@linux ~]$ cat /sys/devices/system/cpu/cpu*/cache/index2/size
8192K
8192K
8192K
8192K
[loongson@linux ~]$ lscpu | grep "L2 cache"
L2 cache:              8192K

Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 9cede7c..9952176 100644 (file)
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1623,15 +1623,13 @@ static void __init loongson3_sc_init(void)
        c->scache.sets = 64 << ((config2 >> 8) & 15);
        c->scache.ways = 1 + (config2 & 15);
 
-       scache_size = c->scache.sets *
-                                 c->scache.ways *
-                                 c->scache.linesz;
-
        /* Loongson-3 has 4-Scache banks, while Loongson-2K have only 2 banks */
        if ((c->processor_id & PRID_IMP_MASK) == PRID_IMP_LOONGSON_64R)
-               scache_size *= 2;
+               c->scache.sets *= 2;
        else
-               scache_size *= 4;
+               c->scache.sets *= 4;
+
+       scache_size = c->scache.sets * c->scache.ways * c->scache.linesz;
 
        c->scache.waybit = 0;
        c->scache.waysize = scache_size / c->scache.ways;