Merge tag 'amd-drm-next-5.11-2020-11-05' of git://people.freedesktop.org/~agd5f/linux...

amd-drm-next-5.11-2020-11-05:

amdgpu:
- Add initial support for Vangogh
- Add support for Green Sardine
- Add initial support for Dimgrey Cavefish
- Scatter/Gather display support for Renoir
- Updates for Sienna Cichlid
- Updates for Navy Flounder
- SMU7 power improvements
- Modifier support for gfx9+
- CI BACO fixes
- Arcturus SMU fixes
- Lots of code cleanups
- DC fixes
- Kernel doc fixes
- Add more GPU HW client information to page fault error logging
- MPO clock tuning for RV
- FP fixes for DCN3 on ARM and PPC

radeon:
- Expose voltage via hwmon on Sumo APUs

amdkfd:
- Fix unique id handling
- Misc fixes

From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20201105222749.201798-1-alexander.deucher@amd.com

diff --cc MAINTAINERS
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.h
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_display.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_drv.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_gem.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
index e1f64ef,b191701..c6c9723
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_object.c
@@@ -1507,3 -1528,77 +1508,77 @@@ uint32_t amdgpu_bo_get_preferred_pin_do
        }
        return domain;
  }
 -      pin_count = READ_ONCE(bo->pin_count);
+ 
+ #if defined(CONFIG_DEBUG_FS)
+ #define amdgpu_bo_print_flag(m, bo, flag)                     \
+       do {                                                    \
+               if (bo->flags & (AMDGPU_GEM_CREATE_ ## flag)) { \
+                       seq_printf((m), " " #flag);             \
+               }                                               \
+       } while (0)
+ 
+ /**
+  * amdgpu_debugfs_print_bo_info - print BO info in debugfs file
+  *
+  * @id: Index or Id of the BO
+  * @bo: Requested BO for printing info
+  * @m: debugfs file
+  *
+  * Print BO information in debugfs file
+  *
+  * Returns:
+  * Size of the BO in bytes.
+  */
+ u64 amdgpu_bo_print_info(int id, struct amdgpu_bo *bo, struct seq_file *m)
+ {
+       struct dma_buf_attachment *attachment;
+       struct dma_buf *dma_buf;
+       unsigned int domain;
+       const char *placement;
+       unsigned int pin_count;
+       u64 size;
+ 
+       domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
+       switch (domain) {
+       case AMDGPU_GEM_DOMAIN_VRAM:
+               placement = "VRAM";
+               break;
+       case AMDGPU_GEM_DOMAIN_GTT:
+               placement = " GTT";
+               break;
+       case AMDGPU_GEM_DOMAIN_CPU:
+       default:
+               placement = " CPU";
+               break;
+       }
+ 
+       size = amdgpu_bo_size(bo);
+       seq_printf(m, "\t\t0x%08x: %12lld byte %s",
+                       id, size, placement);
+ 
++      pin_count = READ_ONCE(bo->tbo.pin_count);
+       if (pin_count)
+               seq_printf(m, " pin count %d", pin_count);
+ 
+       dma_buf = READ_ONCE(bo->tbo.base.dma_buf);
+       attachment = READ_ONCE(bo->tbo.base.import_attach);
+ 
+       if (attachment)
+               seq_printf(m, " imported from %p", dma_buf);
+       else if (dma_buf)
+               seq_printf(m, " exported as %p", dma_buf);
+ 
+       amdgpu_bo_print_flag(m, bo, CPU_ACCESS_REQUIRED);
+       amdgpu_bo_print_flag(m, bo, NO_CPU_ACCESS);
+       amdgpu_bo_print_flag(m, bo, CPU_GTT_USWC);
+       amdgpu_bo_print_flag(m, bo, VRAM_CLEARED);
+       amdgpu_bo_print_flag(m, bo, SHADOW);
+       amdgpu_bo_print_flag(m, bo, VRAM_CONTIGUOUS);
+       amdgpu_bo_print_flag(m, bo, VM_ALWAYS_VALID);
+       amdgpu_bo_print_flag(m, bo, EXPLICIT_SYNC);
+ 
+       seq_puts(m, "\n");
+ 
+       return size;
+ }
+ #endif

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_object.h
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c01c060,69ebd07..12aa35a
--- 1/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
--- 2/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@@ -62,18 -63,13 +62,18 @@@
  
  #define AMDGPU_TTM_VRAM_MAX_DW_READ   (size_t)128
  
 +static int amdgpu_ttm_backend_bind(struct ttm_bo_device *bdev,
 +                                 struct ttm_tt *ttm,
 +                                 struct ttm_resource *bo_mem);
 +static void amdgpu_ttm_backend_unbind(struct ttm_bo_device *bdev,
 +                                    struct ttm_tt *ttm);
 +
  static int amdgpu_ttm_init_on_chip(struct amdgpu_device *adev,
                                    unsigned int type,
-                                   uint64_t size)
+                                   uint64_t size_in_page)
  {
        return ttm_range_man_init(&adev->mman.bdev, type,
-                                 false, size >> PAGE_SHIFT);
 -                                TTM_PL_FLAG_UNCACHED, TTM_PL_FLAG_UNCACHED,
+                                 false, size_in_page);
  }
  
  /**

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
Simple merge

diff --cc drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdkfd/cik_event_interrupt.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdkfd/kfd_device_queue_manager.c
Simple merge

diff --cc drivers/gpu/drm/amd/amdkfd/kfd_priv.h
Simple merge

diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 86fd442,b7442d6..2855bb9
--- 1/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
--- 2/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@@ -5514,19 -6003,19 +6003,21 @@@ static void dm_update_crtc_active_plane
  }
  
  static int dm_crtc_helper_atomic_check(struct drm_crtc *crtc,
 -                                     struct drm_crtc_state *state)
 +                                     struct drm_atomic_state *state)
  {
 +      struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
 +                                                                        crtc);
        struct amdgpu_device *adev = drm_to_adev(crtc->dev);
        struct dc *dc = adev->dm.dc;
 -      struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(state);
 +      struct dm_crtc_state *dm_crtc_state = to_dm_crtc_state(crtc_state);
        int ret = -EINVAL;
  
 -      trace_amdgpu_dm_crtc_atomic_check(state);
++      trace_amdgpu_dm_crtc_atomic_check(crtc_state);
+ 
 -      dm_update_crtc_active_planes(crtc, state);
 +      dm_update_crtc_active_planes(crtc, crtc_state);
  
        if (unlikely(!dm_crtc_state->stream &&
 -                   modeset_required(state, NULL, dm_crtc_state->stream))) {
 +                   modeset_required(crtc_state, NULL, dm_crtc_state->stream))) {
                WARN_ON(1);
                return ret;
        }
@@@ -7501,8 -7998,9 +8000,10 @@@ static void amdgpu_dm_atomic_commit_tai
        int crtc_disable_count = 0;
        bool mode_set_reset_required = false;
  
+       trace_amdgpu_dm_atomic_commit_tail_begin(state);
+ 
        drm_atomic_helper_update_legacy_modeset_state(dev, state);
 +      drm_atomic_helper_calc_timestamping_constants(state);
  
        dm_state = dm_atomic_get_new_state(state);
        if (dm_state && dm_state->context) {

diff --cc drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
Simple merge

diff --cc drivers/gpu/drm/radeon/radeon.h
Simple merge

diff --cc include/uapi/drm/drm_fourcc.h
Simple merge