tools headers UAPI: Sync linux/prctl.h with the kernel sources

To pick the changes in:

  433c38f40f6a81cf ("arm64: mte: change ASYNC and SYNC TCF settings into bitfields")
  e893bb1bb4d2eb63 ("x86, prctl: Hook L1D flushing in via prctl")

That don't result in any changes in tooling:

  $ tools/perf/trace/beauty/prctl_option.sh > before
  $ cp include/uapi/linux/prctl.h tools/include/uapi/linux/prctl.h
  $ tools/perf/trace/beauty/prctl_option.sh > after
  $ diff -u before after
  $

Just silences this perf tools build warning:

  Warning: Kernel ABI header at 'tools/include/uapi/linux/prctl.h' differs from latest version at 'include/uapi/linux/prctl.h'
  diff -u tools/include/uapi/linux/prctl.h include/uapi/linux/prctl.h

Cc: Balbir Singh <sblbir@amazon.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Peter Collingbourne <pcc@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>

diff --git a/tools/include/uapi/linux/prctl.h b/tools/include/uapi/linux/prctl.h
index 967d9c5..43bd7f7 100644 (file)
--- a/tools/include/uapi/linux/prctl.h
+++ b/tools/include/uapi/linux/prctl.h
@@ -213,6 +213,7 @@ struct prctl_mm_map {
 /* Speculation control variants */
 # define PR_SPEC_STORE_BYPASS          0
 # define PR_SPEC_INDIRECT_BRANCH       1
 /* Speculation control variants */
 # define PR_SPEC_STORE_BYPASS          0
 # define PR_SPEC_INDIRECT_BRANCH       1

+# define PR_SPEC_L1D_FLUSH             2

 /* Return and control values for PR_SET/GET_SPECULATION_CTRL */
 # define PR_SPEC_NOT_AFFECTED          0
 # define PR_SPEC_PRCTL                 (1UL << 0)
 /* Return and control values for PR_SET/GET_SPECULATION_CTRL */
 # define PR_SPEC_NOT_AFFECTED          0
 # define PR_SPEC_PRCTL                 (1UL << 0)


@@ -234,14 +235,15 @@ struct prctl_mm_map {
 #define PR_GET_TAGGED_ADDR_CTRL                56
 # define PR_TAGGED_ADDR_ENABLE         (1UL << 0)
 /* MTE tag check fault modes */
 #define PR_GET_TAGGED_ADDR_CTRL                56
 # define PR_TAGGED_ADDR_ENABLE         (1UL << 0)
 /* MTE tag check fault modes */

-# define PR_MTE_TCF_SHIFT              1
-# define PR_MTE_TCF_NONE               (0UL << PR_MTE_TCF_SHIFT)
-# define PR_MTE_TCF_SYNC               (1UL << PR_MTE_TCF_SHIFT)
-# define PR_MTE_TCF_ASYNC              (2UL << PR_MTE_TCF_SHIFT)
-# define PR_MTE_TCF_MASK               (3UL << PR_MTE_TCF_SHIFT)
+# define PR_MTE_TCF_NONE               0
+# define PR_MTE_TCF_SYNC               (1UL << 1)
+# define PR_MTE_TCF_ASYNC              (1UL << 2)
+# define PR_MTE_TCF_MASK               (PR_MTE_TCF_SYNC | PR_MTE_TCF_ASYNC)

 /* MTE tag inclusion mask */
 # define PR_MTE_TAG_SHIFT              3
 # define PR_MTE_TAG_MASK               (0xffffUL << PR_MTE_TAG_SHIFT)
 /* MTE tag inclusion mask */
 # define PR_MTE_TAG_SHIFT              3
 # define PR_MTE_TAG_MASK               (0xffffUL << PR_MTE_TAG_SHIFT)

+/* Unused; kept only for source compatibility */
+# define PR_MTE_TCF_SHIFT              1

 
 /* Control reclaim behavior when allocating memory */
 #define PR_SET_IO_FLUSHER              57
 
 /* Control reclaim behavior when allocating memory */
 #define PR_SET_IO_FLUSHER              57