drm/i915/gt: Add an insert_entry for gen8_ppgtt

In the next patch, we will want to write a PTE for an explicit
dma address, outside of the usual vma.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Matthew Auld <matthew.auld@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210617063018.92802-5-thomas.hellstrom@linux.intel.com

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 21c8b73..1b676d7 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -555,6 +555,24 @@ static void gen8_ppgtt_insert(struct i915_address_space *vm,
        }
 }
 
+static void gen8_ppgtt_insert_entry(struct i915_address_space *vm,
+                                   dma_addr_t addr,
+                                   u64 offset,
+                                   enum i915_cache_level level,
+                                   u32 flags)
+{
+       u64 idx = offset >> GEN8_PTE_SHIFT;
+       struct i915_page_directory * const pdp =
+               gen8_pdp_for_page_index(vm, idx);
+       struct i915_page_directory *pd =
+               i915_pd_entry(pdp, gen8_pd_index(idx, 2));
+       gen8_pte_t *vaddr;
+
+       vaddr = px_vaddr(i915_pt_entry(pd, gen8_pd_index(idx, 1)));
+       vaddr[gen8_pd_index(idx, 0)] = gen8_pte_encode(addr, level, flags);
+       clflush_cache_range(&vaddr[gen8_pd_index(idx, 0)], sizeof(*vaddr));
+}
+
 static int gen8_init_scratch(struct i915_address_space *vm)
 {
        u32 pte_flags;
@@ -734,6 +752,7 @@ struct i915_ppgtt *gen8_ppgtt_create(struct intel_gt *gt)
 
        ppgtt->vm.bind_async_flags = I915_VMA_LOCAL_BIND;
        ppgtt->vm.insert_entries = gen8_ppgtt_insert;
+       ppgtt->vm.insert_page = gen8_ppgtt_insert_entry;
        ppgtt->vm.allocate_va_range = gen8_ppgtt_alloc;
        ppgtt->vm.clear_range = gen8_ppgtt_clear;