dt-bindings: opp: qcom-nvmem: Support pstates provided by a power domain
authorNiklas Cassel <niklas.cassel@linaro.org>
Fri, 30 Aug 2019 10:29:15 +0000 (12:29 +0200)
committerViresh Kumar <viresh.kumar@linaro.org>
Tue, 3 Sep 2019 02:23:19 +0000 (07:53 +0530)
commitf6081a73091c0902efb45f47706d35284ebb4e9a
tree7024457217db3dcfb82379842f395f2c7e6ef5da
parenta409906003a2b5418e6e60ac2524948ea80819f2
dt-bindings: opp: qcom-nvmem: Support pstates provided by a power domain

Some Qualcomm SoCs have support for Core Power Reduction (CPR).
On these platforms, we need to attach to the power domain provider
providing the performance states, so that the leaky device (the CPU)
can configure the performance states (which represent different
CPU clock frequencies).

Signed-off-by: Niklas Cassel <niklas.cassel@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Documentation/devicetree/bindings/opp/qcom-nvmem-cpufreq.txt