PCI: cadence: Remove private bus number and range storage
authorRob Herring <robh@kernel.org>
Wed, 22 Jul 2020 02:25:08 +0000 (20:25 -0600)
committerLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Thu, 23 Jul 2020 16:13:13 +0000 (17:13 +0100)
commitec64e2795988322bf33aaf0f0935e0f1b4da0ed2
tree45ddf3878392a8c5addd5a2ac3eb4fba49b3fa44
parent06ff98fcc4a7588c7e45833f2092b3a14e66b575
PCI: cadence: Remove private bus number and range storage

There's no need to store the bus number or range resource as the driver
only needs the bus number which is already in the pci_host_bridge.

For endpoint mode, the bus number is always 0.

Link: https://lore.kernel.org/r/20200722022514.1283916-14-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Tom Joseph <tjoseph@cadence.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Bjorn Helgaas <bhelgaas@google.com>
drivers/pci/controller/cadence/pcie-cadence-ep.c
drivers/pci/controller/cadence/pcie-cadence-host.c
drivers/pci/controller/cadence/pcie-cadence.c
drivers/pci/controller/cadence/pcie-cadence.h