liquidio: Fix unintentional sign extension issue on left shift of u16
authorColin Ian King <colin.king@canonical.com>
Wed, 14 Jul 2021 15:23:43 +0000 (16:23 +0100)
committerDavid S. Miller <davem@davemloft.net>
Thu, 15 Jul 2021 17:27:33 +0000 (10:27 -0700)
commite7efc2ce3d0789cd7c21b70ff00cd7838d382639
treeab0d1fce592f6779850b47773f3dc98934bb4289
parent99bb2ebab953435852340cdb198c5abbf0bb5dd3
liquidio: Fix unintentional sign extension issue on left shift of u16

Shifting the u16 integer oct->pcie_port by CN23XX_PKT_INPUT_CTL_MAC_NUM_POS
(29) bits will be promoted to a 32 bit signed int and then sign-extended
to a u64. In the cases where oct->pcie_port where bit 2 is set (e.g. 3..7)
the shifted value will be sign extended and the top 32 bits of the result
will be set.

Fix this by casting the u16 values to a u64 before the 29 bit left shift.

Addresses-Coverity: ("Unintended sign extension")

Fixes: 3451b97cce2d ("liquidio: CN23XX register setup")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/cavium/liquidio/cn23xx_pf_device.c