Merge tag 'renesas-r9a07g044-dt-binding-defs-tag2' into renesas-clk-for-v5.15
authorGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 26 Jul 2021 12:14:50 +0000 (14:14 +0200)
committerGeert Uytterhoeven <geert+renesas@glider.be>
Mon, 26 Jul 2021 12:14:50 +0000 (14:14 +0200)
commit9800190881cd5bc9e98c69710f04be8ae120cd38
tree44eeca6e9eb04ccbbf931de0bb4d3c075349577e
parent1b87d5bba32c1f25a12ba0625546e5375e3f998d
parent0b256c403d4082bafc681143913442288010277c
Merge tag 'renesas-r9a07g044-dt-binding-defs-tag2' into renesas-clk-for-v5.15

Renesas RZ/G2L DT Binding Definitions Update

Missing definition for the P0_DIV2 core clock on the Renesas RZ/G2L
(R9A07G044) SoC, shared by driver and DT source files.