openrisc: Define memory barrier mb
authorPeter Zijlstra <peterz@infradead.org>
Wed, 14 Apr 2021 12:45:43 +0000 (14:45 +0200)
committerStafford Horne <shorne@gmail.com>
Sat, 15 May 2021 07:00:10 +0000 (16:00 +0900)
commit8b549c18ae81dbc36fb11e4aa08b8378c599ca95
treea639f8a9307a3649e56b39bd0f3adc6ec4d055c1
parent371dcaee1ade4b1eefd541ae6ee048b5ce15b37c
openrisc: Define memory barrier mb

This came up in the discussion of the requirements of qspinlock on an
architecture.  OpenRISC uses qspinlock, but it was noticed that the
memmory barrier was not defined.

Peter defined it in the mail thread writing:

    As near as I can tell this should do. The arch spec only lists
    this one instruction and the text makes it sound like a completion
    barrier.

This is correct so applying this patch.

Signed-off-by: Peter Zijlstra <peterz@infradead.org>
[shorne@gmail.com:Turned the mail into a patch]
Signed-off-by: Stafford Horne <shorne@gmail.com>
arch/openrisc/include/asm/barrier.h [new file with mode: 0644]