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riscv: dts: fu740: fix cache-controller interrupts
authorDavid Abdurachmanov <david.abdurachmanov@sifive.com>
Sun, 13 Jun 2021 00:43:57 +0000 (17:43 -0700)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Sat, 19 Jun 2021 07:11:53 +0000 (00:11 -0700)
commit7ede12b01b59dc67bef2e2035297dd2da5bfe427
treedcf04066281ea4fbbcc7db709bf462862fde2d69tree | snapshot
parent3a02764c372c50ff7917fde5c6961f6cdb81d9d5commit | diff
riscv: dts: fu740: fix cache-controller interrupts

The order of interrupt numbers is incorrect.

The order for FU740 is: DirError, DataError, DataFail, DirFail

From SiFive FU740-C000 Manual:
19 - L2 Cache DirError
20 - L2 Cache DirFail
21 - L2 Cache DataError
22 - L2 Cache DataFail

Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
arch/riscv/boot/dts/sifive/fu740-c000.dtsi diff | blob | history
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