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(parent: e7b146a) | patch
riscv: perf: RISCV_BASE_PMU should be independent
authorKefeng Wang <wangkefeng.wang@huawei.com>
Thu, 7 May 2020 15:04:45 +0000 (23:04 +0800)
committerPalmer Dabbelt <palmerdabbelt@google.com>
Tue, 12 May 2020 23:21:46 +0000 (16:21 -0700)
commit48084c3595cb7429f6ba734cfea1313573b9a7fa
tree305785d6b4ee85ea3d3c640e306a9cee466dc9bftree | snapshot
parente7b146a8bfba50e263745bbdefc11833c3766664commit | diff
riscv: perf: RISCV_BASE_PMU should be independent

Selecting PERF_EVENTS without selecting RISCV_BASE_PMU results in a build
error.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
[Palmer: commit text]
Fixes: 178e9fc47aae("perf: riscv: preliminary RISC-V support")
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
arch/riscv/include/asm/perf_event.h diff | blob | history
arch/riscv/kernel/Makefile diff | blob | history
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