projects / linux-2.6-microblaze.git / commit
? search:
summary | shortlog | log | commit | commitdiff | tree
(parent: bf952a2) | patch
RISC-V: Enable sstc extension parsing from DT
authorAtish Patra <atishp@rivosinc.com>
Fri, 22 Jul 2022 16:50:45 +0000 (09:50 -0700)
committerPalmer Dabbelt <palmer@rivosinc.com>
Thu, 11 Aug 2022 21:36:13 +0000 (14:36 -0700)
commit464b0187ff94fcc629fe7cd350e16a3b9e80ed9e
tree56b5a4be274df53a837dc3377d94cd21e30606c5tree | snapshot
parentbf952a290f7a9d818204b9b68e861655f8b15a65commit | diff
RISC-V: Enable sstc extension parsing from DT

The ISA extension framework now allows parsing any multi-letter
ISA extension.

Enable that for sstc extension.

Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
Link: https://lore.kernel.org/r/20220722165047.519994-3-atishp@rivosinc.com
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
arch/riscv/include/asm/hwcap.h diff | blob | history
arch/riscv/kernel/cpu.c diff | blob | history
arch/riscv/kernel/cpufeature.c diff | blob | history
MicroBlaze GIT Repository