Merge tag 'perf-tools-for-v5.18-2022-04-02' of git://git.kernel.org/pub/scm/linux...

[linux-2.6-microblaze.git] / tools / arch / x86 / include / asm / msr-index.h

diff --git a/tools/arch/x86/include/asm/msr-index.h b/tools/arch/x86/include/asm/msr-index.h
index 0e7f303..0eb90d2 100644 (file)
--- a/tools/arch/x86/include/asm/msr-index.h
+++ b/tools/arch/x86/include/asm/msr-index.h
@@ -205,6 +205,8 @@
 #define RTIT_CTL_DISRETC               BIT(11)
 #define RTIT_CTL_PTW_EN                        BIT(12)
 #define RTIT_CTL_BRANCH_EN             BIT(13)
+#define RTIT_CTL_EVENT_EN              BIT(31)
+#define RTIT_CTL_NOTNT                 BIT_ULL(55)
 #define RTIT_CTL_MTC_RANGE_OFFSET      14
 #define RTIT_CTL_MTC_RANGE             (0x0full << RTIT_CTL_MTC_RANGE_OFFSET)
 #define RTIT_CTL_CYC_THRESH_OFFSET     19
@@ -360,11 +362,29 @@
 #define MSR_ATOM_CORE_TURBO_RATIOS     0x0000066c
 #define MSR_ATOM_CORE_TURBO_VIDS       0x0000066d
 
-
 #define MSR_CORE_PERF_LIMIT_REASONS    0x00000690
 #define MSR_GFX_PERF_LIMIT_REASONS     0x000006B0
 #define MSR_RING_PERF_LIMIT_REASONS    0x000006B1
 
+/* Control-flow Enforcement Technology MSRs */
+#define MSR_IA32_U_CET                 0x000006a0 /* user mode cet */
+#define MSR_IA32_S_CET                 0x000006a2 /* kernel mode cet */
+#define CET_SHSTK_EN                   BIT_ULL(0)
+#define CET_WRSS_EN                    BIT_ULL(1)
+#define CET_ENDBR_EN                   BIT_ULL(2)
+#define CET_LEG_IW_EN                  BIT_ULL(3)
+#define CET_NO_TRACK_EN                        BIT_ULL(4)
+#define CET_SUPPRESS_DISABLE           BIT_ULL(5)
+#define CET_RESERVED                   (BIT_ULL(6) | BIT_ULL(7) | BIT_ULL(8) | BIT_ULL(9))
+#define CET_SUPPRESS                   BIT_ULL(10)
+#define CET_WAIT_ENDBR                 BIT_ULL(11)
+
+#define MSR_IA32_PL0_SSP               0x000006a4 /* ring-0 shadow stack pointer */
+#define MSR_IA32_PL1_SSP               0x000006a5 /* ring-1 shadow stack pointer */
+#define MSR_IA32_PL2_SSP               0x000006a6 /* ring-2 shadow stack pointer */
+#define MSR_IA32_PL3_SSP               0x000006a7 /* ring-3 shadow stack pointer */
+#define MSR_IA32_INT_SSP_TAB           0x000006a8 /* exception shadow stack table */
+
 /* Hardware P state interface */
 #define MSR_PPERF                      0x0000064e
 #define MSR_PERF_LIMIT_REASONS         0x0000064f