Merge tag 'sound-5.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tiwai...

[linux-2.6-microblaze.git] / drivers / soundwire / intel.c

diff --git a/drivers/soundwire/intel.c b/drivers/soundwire/intel.c
index f66fcbc..78037ff 100644 (file)
--- a/drivers/soundwire/intel.c
+++ b/drivers/soundwire/intel.c
@@ -41,80 +41,6 @@ static int md_flags;
 module_param_named(sdw_md_flags, md_flags, int, 0444);
 MODULE_PARM_DESC(sdw_md_flags, "SoundWire Intel Master device flags (0x0 all off)");
 
-/* Intel SHIM Registers Definition */
-#define SDW_SHIM_LCAP                  0x0
-#define SDW_SHIM_LCTL                  0x4
-#define SDW_SHIM_IPPTR                 0x8
-#define SDW_SHIM_SYNC                  0xC
-
-#define SDW_SHIM_CTLSCAP(x)            (0x010 + 0x60 * (x))
-#define SDW_SHIM_CTLS0CM(x)            (0x012 + 0x60 * (x))
-#define SDW_SHIM_CTLS1CM(x)            (0x014 + 0x60 * (x))
-#define SDW_SHIM_CTLS2CM(x)            (0x016 + 0x60 * (x))
-#define SDW_SHIM_CTLS3CM(x)            (0x018 + 0x60 * (x))
-#define SDW_SHIM_PCMSCAP(x)            (0x020 + 0x60 * (x))
-
-#define SDW_SHIM_PCMSYCHM(x, y)                (0x022 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PCMSYCHC(x, y)                (0x042 + (0x60 * (x)) + (0x2 * (y)))
-#define SDW_SHIM_PDMSCAP(x)            (0x062 + 0x60 * (x))
-#define SDW_SHIM_IOCTL(x)              (0x06C + 0x60 * (x))
-#define SDW_SHIM_CTMCTL(x)             (0x06E + 0x60 * (x))
-
-#define SDW_SHIM_WAKEEN                        0x190
-#define SDW_SHIM_WAKESTS               0x192
-
-#define SDW_SHIM_LCTL_SPA              BIT(0)
-#define SDW_SHIM_LCTL_SPA_MASK         GENMASK(3, 0)
-#define SDW_SHIM_LCTL_CPA              BIT(8)
-#define SDW_SHIM_LCTL_CPA_MASK         GENMASK(11, 8)
-
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_24   (24000 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD_VAL_38_4 (38400 / SDW_CADENCE_GSYNC_KHZ - 1)
-#define SDW_SHIM_SYNC_SYNCPRD          GENMASK(14, 0)
-#define SDW_SHIM_SYNC_SYNCCPU          BIT(15)
-#define SDW_SHIM_SYNC_CMDSYNC_MASK     GENMASK(19, 16)
-#define SDW_SHIM_SYNC_CMDSYNC          BIT(16)
-#define SDW_SHIM_SYNC_SYNCGO           BIT(24)
-
-#define SDW_SHIM_PCMSCAP_ISS           GENMASK(3, 0)
-#define SDW_SHIM_PCMSCAP_OSS           GENMASK(7, 4)
-#define SDW_SHIM_PCMSCAP_BSS           GENMASK(12, 8)
-
-#define SDW_SHIM_PCMSYCM_LCHN          GENMASK(3, 0)
-#define SDW_SHIM_PCMSYCM_HCHN          GENMASK(7, 4)
-#define SDW_SHIM_PCMSYCM_STREAM                GENMASK(13, 8)
-#define SDW_SHIM_PCMSYCM_DIR           BIT(15)
-
-#define SDW_SHIM_PDMSCAP_ISS           GENMASK(3, 0)
-#define SDW_SHIM_PDMSCAP_OSS           GENMASK(7, 4)
-#define SDW_SHIM_PDMSCAP_BSS           GENMASK(12, 8)
-#define SDW_SHIM_PDMSCAP_CPSS          GENMASK(15, 13)
-
-#define SDW_SHIM_IOCTL_MIF             BIT(0)
-#define SDW_SHIM_IOCTL_CO              BIT(1)
-#define SDW_SHIM_IOCTL_COE             BIT(2)
-#define SDW_SHIM_IOCTL_DO              BIT(3)
-#define SDW_SHIM_IOCTL_DOE             BIT(4)
-#define SDW_SHIM_IOCTL_BKE             BIT(5)
-#define SDW_SHIM_IOCTL_WPDD            BIT(6)
-#define SDW_SHIM_IOCTL_CIBD            BIT(8)
-#define SDW_SHIM_IOCTL_DIBD            BIT(9)
-
-#define SDW_SHIM_CTMCTL_DACTQE         BIT(0)
-#define SDW_SHIM_CTMCTL_DODS           BIT(1)
-#define SDW_SHIM_CTMCTL_DOAIS          GENMASK(4, 3)
-
-#define SDW_SHIM_WAKEEN_ENABLE         BIT(0)
-#define SDW_SHIM_WAKESTS_STATUS                BIT(0)
-
-/* Intel ALH Register definitions */
-#define SDW_ALH_STRMZCFG(x)            (0x000 + (0x4 * (x)))
-#define SDW_ALH_NUM_STREAMS            64
-
-#define SDW_ALH_STRMZCFG_DMAT_VAL      0x3
-#define SDW_ALH_STRMZCFG_DMAT          GENMASK(7, 0)
-#define SDW_ALH_STRMZCFG_CHN           GENMASK(19, 16)
-
 enum intel_pdi_type {
        INTEL_PDI_IN = 0,
        INTEL_PDI_OUT = 1,