raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
}
+static int amd_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+ u32 pin_reg;
+ unsigned long flags;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
+ struct amd_gpio *gpio_dev = gpiochip_get_data(gc);
+ u32 wake_mask = BIT(WAKE_CNTRL_OFF_S0I3) | BIT(WAKE_CNTRL_OFF_S3) |
+ BIT(WAKE_CNTRL_OFF_S4);
+
+ raw_spin_lock_irqsave(&gpio_dev->lock, flags);
+ pin_reg = readl(gpio_dev->base + (d->hwirq)*4);
+
+ if (on)
+ pin_reg |= wake_mask;
+ else
+ pin_reg &= ~wake_mask;
+
+ writel(pin_reg, gpio_dev->base + (d->hwirq)*4);
+ raw_spin_unlock_irqrestore(&gpio_dev->lock, flags);
+
+ return 0;
+}
+
static void amd_gpio_irq_eoi(struct irq_data *d)
{
u32 reg;
.irq_disable = amd_gpio_irq_disable,
.irq_mask = amd_gpio_irq_mask,
.irq_unmask = amd_gpio_irq_unmask,
+ .irq_set_wake = amd_gpio_irq_set_wake,
.irq_eoi = amd_gpio_irq_eoi,
.irq_set_type = amd_gpio_irq_set_type,
- .flags = IRQCHIP_SKIP_SET_WAKE,
+ /*
+ * We need to set IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND so that a wake event
+ * also generates an IRQ. We need the IRQ so the irq_handler can clear
+ * the wake event. Otherwise the wake event will never clear and
+ * prevent the system from suspending.
+ */
+ .flags = IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND,
};
#define PIN_IRQ_PENDING (BIT(INTERRUPT_STS_OFF) | BIT(WAKE_STS_OFF))