PCI: dwc/qcom: Use common PCI register definitions

[linux-2.6-microblaze.git] / drivers / pci / controller / dwc / pcie-qcom.c

diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c
index 17498e6..d8d1fb7 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-qcom.c
+++ b/drivers/pci/controller/dwc/pcie-qcom.c
@@ -40,11 +40,6 @@
 #define L23_CLK_RMV_DIS                                BIT(2)
 #define L1_CLK_RMV_DIS                         BIT(1)
 
-#define PCIE20_COMMAND_STATUS                  0x04
-#define CMD_BME_VAL                            0x4
-#define PCIE20_DEVICE_CONTROL2_STATUS2         0x98
-#define PCIE_CAP_CPL_TIMEOUT_DISABLE           0x10
-
 #define PCIE20_PARF_PHY_CTRL                   0x40
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK      GENMASK(20, 16)
 #define PHY_CTRL_PHY_TX0_TERM_OFFSET(x)                ((x) << 16)
@@ -72,10 +67,6 @@
 #define PCIE20_AXI_MSTR_RESP_COMP_CTRL1                0x81c
 #define CFG_BRIDGE_SB_INIT                     BIT(0)
 
-#define PCIE20_CAP                             0x70
-#define PCIE20_CAP_LINK_CAPABILITIES           (PCIE20_CAP + 0xC)
-#define PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT        (BIT(10) | BIT(11))
-#define PCIE20_CAP_LINK_1                      (PCIE20_CAP + 0x14)
 #define PCIE_CAP_LINK1_VAL                     0x2FD7F
 
 #define PCIE20_PARF_Q2A_FLUSH                  0x1AC
@@ -1022,6 +1013,7 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
        struct qcom_pcie_resources_2_3_3 *res = &pcie->res.v2_3_3;
        struct dw_pcie *pci = pcie->pci;
        struct device *dev = pci->dev;
+       u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
        int i, ret;
        u32 val;
 
@@ -1095,16 +1087,16 @@ static int qcom_pcie_init_2_3_3(struct qcom_pcie *pcie)
                pcie->parf + PCIE20_PARF_SYS_CTRL);
        writel(0, pcie->parf + PCIE20_PARF_Q2A_FLUSH);
 
-       writel(CMD_BME_VAL, pci->dbi_base + PCIE20_COMMAND_STATUS);
+       writel(PCI_COMMAND_MASTER, pci->dbi_base + PCI_COMMAND);
        writel(DBI_RO_WR_EN, pci->dbi_base + PCIE20_MISC_CONTROL_1_REG);
-       writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + PCIE20_CAP_LINK_1);
+       writel(PCIE_CAP_LINK1_VAL, pci->dbi_base + offset + PCI_EXP_SLTCAP);
 
-       val = readl(pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
-       val &= ~PCIE20_CAP_ACTIVE_STATE_LINK_PM_SUPPORT;
-       writel(val, pci->dbi_base + PCIE20_CAP_LINK_CAPABILITIES);
+       val = readl(pci->dbi_base + offset + PCI_EXP_LNKCAP);
+       val &= ~PCI_EXP_LNKCAP_ASPMS;
+       writel(val, pci->dbi_base + offset + PCI_EXP_LNKCAP);
 
-       writel(PCIE_CAP_CPL_TIMEOUT_DISABLE, pci->dbi_base +
-               PCIE20_DEVICE_CONTROL2_STATUS2);
+       writel(PCI_EXP_DEVCTL2_COMP_TMOUT_DIS, pci->dbi_base + offset +
+               PCI_EXP_DEVCTL2);
 
        return 0;
 
@@ -1257,7 +1249,8 @@ static void qcom_pcie_post_deinit_2_7_0(struct qcom_pcie *pcie)
 
 static int qcom_pcie_link_up(struct dw_pcie *pci)
 {
-       u16 val = readw(pci->dbi_base + PCIE20_CAP + PCI_EXP_LNKSTA);
+       u16 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
+       u16 val = readw(pci->dbi_base + offset + PCI_EXP_LNKSTA);
 
        return !!(val & PCI_EXP_LNKSTA_DLLLA);
 }
@@ -1285,9 +1278,7 @@ static int qcom_pcie_host_init(struct pcie_port *pp)
        }
 
        dw_pcie_setup_rc(pp);
-
-       if (IS_ENABLED(CONFIG_PCI_MSI))
-               dw_pcie_msi_init(pp);
+       dw_pcie_msi_init(pp);
 
        qcom_ep_reset_deassert(pcie);
 
@@ -1387,10 +1378,8 @@ static int qcom_pcie_probe(struct platform_device *pdev)
 
        pm_runtime_enable(dev);
        ret = pm_runtime_get_sync(dev);
-       if (ret < 0) {
-               pm_runtime_disable(dev);
-               return ret;
-       }
+       if (ret < 0)
+               goto err_pm_runtime_put;
 
        pci->dev = dev;
        pci->ops = &dw_pcie_ops;
@@ -1410,8 +1399,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
        if (pcie->gen < 0)
                pcie->gen = 2;
 
-       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf");
-       pcie->parf = devm_ioremap_resource(dev, res);
+       pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");
        if (IS_ERR(pcie->parf)) {
                ret = PTR_ERR(pcie->parf);
                goto err_pm_runtime_put;
@@ -1424,8 +1412,7 @@ static int qcom_pcie_probe(struct platform_device *pdev)
                goto err_pm_runtime_put;
        }
 
-       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi");
-       pcie->elbi = devm_ioremap_resource(dev, res);
+       pcie->elbi = devm_platform_ioremap_resource_byname(pdev, "elbi");
        if (IS_ERR(pcie->elbi)) {
                ret = PTR_ERR(pcie->elbi);
                goto err_pm_runtime_put;