PCI: dwc: Set PORT_LINK_DLL_LINK_EN in common setup code

[linux-2.6-microblaze.git] / drivers / pci / controller / dwc / pcie-intel-gw.c

diff --git a/drivers/pci/controller/dwc/pcie-intel-gw.c b/drivers/pci/controller/dwc/pcie-intel-gw.c
index 2d8dbb3..d15e49b 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-intel-gw.c
+++ b/drivers/pci/controller/dwc/pcie-intel-gw.c
@@ -67,8 +67,6 @@ struct intel_pcie_port {
        void __iomem            *app_base;
        struct gpio_desc        *reset_gpio;
        u32                     rst_intrvl;
-       u32                     max_speed;
-       u32                     link_gen;
        u32                     max_width;
        u32                     n_fts;
        struct clk              *core_clk;
@@ -137,7 +135,6 @@ static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
        u8 offset = lpp->pcie_cap_ofst;
 
        val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCAP);
-       lpp->max_speed = FIELD_GET(PCI_EXP_LNKCAP_SLS, val);
        lpp->max_width = FIELD_GET(PCI_EXP_LNKCAP_MLW, val);
 
        val = pcie_rc_cfg_rd(lpp, offset + PCI_EXP_LNKCTL);
@@ -149,8 +146,9 @@ static void intel_pcie_link_setup(struct intel_pcie_port *lpp)
 static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp)
 {
        u32 val, mask;
+       struct dw_pcie *pci = &lpp->pci;
 
-       switch (pcie_link_speed[lpp->max_speed]) {
+       switch (pcie_link_speed[pci->link_gen]) {
        case PCIE_SPEED_8_0GT:
                lpp->n_fts = PORT_AFR_N_FTS_GEN3;
                break;
@@ -166,10 +164,6 @@ static void intel_pcie_port_logic_setup(struct intel_pcie_port *lpp)
        val = FIELD_PREP(PORT_AFR_N_FTS_MASK, lpp->n_fts) |
               FIELD_PREP(PORT_AFR_CC_N_FTS_MASK, lpp->n_fts);
        pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_AFR, mask, val);
-
-       /* Port Link Control Register */
-       pcie_rc_cfg_wr_mask(lpp, PCIE_PORT_LINK_CONTROL, PORT_LINK_DLL_LINK_EN,
-                           PORT_LINK_DLL_LINK_EN);
 }
 
 static void intel_pcie_rc_setup(struct intel_pcie_port *lpp)
@@ -179,7 +173,6 @@ static void intel_pcie_rc_setup(struct intel_pcie_port *lpp)
        dw_pcie_setup_rc(&lpp->pci.pp);
        dw_pcie_upconfig_setup(&lpp->pci);
        intel_pcie_port_logic_setup(lpp);
-       dw_pcie_link_set_max_speed(&lpp->pci, lpp->link_gen);
        dw_pcie_link_set_n_fts(&lpp->pci, lpp->n_fts);
 }
 
@@ -253,11 +246,9 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
        struct intel_pcie_port *lpp = platform_get_drvdata(pdev);
        struct dw_pcie *pci = &lpp->pci;
        struct device *dev = pci->dev;
-       struct resource *res;
        int ret;
 
-       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dbi");
-       pci->dbi_base = devm_ioremap_resource(dev, res);
+       pci->dbi_base = devm_platform_ioremap_resource_byname(pdev, "dbi");
        if (IS_ERR(pci->dbi_base))
                return PTR_ERR(pci->dbi_base);
 
@@ -288,11 +279,7 @@ static int intel_pcie_get_resources(struct platform_device *pdev)
        if (ret)
                lpp->rst_intrvl = RESET_INTERVAL_MS;
 
-       ret = of_pci_get_max_link_speed(dev->of_node);
-       lpp->link_gen = ret < 0 ? 0 : ret;
-
-       res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "app");
-       lpp->app_base = devm_ioremap_resource(dev, res);
+       lpp->app_base = devm_platform_ioremap_resource_byname(pdev, "app");
        if (IS_ERR(lpp->app_base))
                return PTR_ERR(lpp->app_base);
 
@@ -316,8 +303,9 @@ static int intel_pcie_wait_l2(struct intel_pcie_port *lpp)
 {
        u32 value;
        int ret;
+       struct dw_pcie *pci = &lpp->pci;
 
-       if (pcie_link_speed[lpp->max_speed] < PCIE_SPEED_8_0GT)
+       if (pci->link_gen < 3)
                return 0;
 
        /* Send PME_TURN_OFF message */