}
}
- ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
- if (ret)
- pci->num_viewport = 2;
-
if (pci->link_gen < 1)
pci->link_gen = of_pci_get_max_link_speed(np);
dw_chained_msi_isr,
pp);
+ ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
+ if (ret)
+ dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
+
pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
sizeof(pp->msi_msg),
DMA_FROM_DEVICE,
goto err_free_msi;
}
+ dw_pcie_setup_rc(pp);
dw_pcie_msi_init(pp);
if (!dw_pcie_link_up(pci) && pci->ops->start_link) {
dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
/* Ensure all outbound windows are disabled so there are multiple matches */
- for (i = 0; i < pci->num_viewport; i++)
+ for (i = 0; i < pci->num_ob_windows; i++)
dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
/*
if (resource_type(entry->res) != IORESOURCE_MEM)
continue;
- if (pci->num_viewport <= ++atu_idx)
+ if (pci->num_ob_windows <= ++atu_idx)
break;
dw_pcie_prog_outbound_atu(pci, atu_idx,
}
if (pp->io_size) {
- if (pci->num_viewport > ++atu_idx)
+ if (pci->num_ob_windows > ++atu_idx)
dw_pcie_prog_outbound_atu(pci, atu_idx,
PCIE_ATU_TYPE_IO, pp->io_base,
pp->io_bus_addr, pp->io_size);
pci->io_cfg_atu_shared = true;
}
- if (pci->num_viewport <= atu_idx)
+ if (pci->num_ob_windows <= atu_idx)
dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
- pci->num_viewport);
+ pci->num_ob_windows);
}
dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);