PCI: dwc: Fix inverted condition of DMA mask setup warning

[linux-2.6-microblaze.git] / drivers / pci / controller / dwc / pcie-designware-host.c

diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pci/controller/dwc/pcie-designware-host.c
index cde45b2..8a84c00 100644 (file)
--- a/drivers/pci/controller/dwc/pcie-designware-host.c
+++ b/drivers/pci/controller/dwc/pcie-designware-host.c
@@ -256,7 +256,7 @@ int dw_pcie_allocate_domains(struct pcie_port *pp)
        return 0;
 }
 
-void dw_pcie_free_msi(struct pcie_port *pp)
+static void dw_pcie_free_msi(struct pcie_port *pp)
 {
        if (pp->msi_irq) {
                irq_set_chained_handler(pp->msi_irq, NULL);
@@ -275,19 +275,18 @@ void dw_pcie_free_msi(struct pcie_port *pp)
        }
 }
 
-void dw_pcie_msi_init(struct pcie_port *pp)
+static void dw_pcie_msi_init(struct pcie_port *pp)
 {
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
        u64 msi_target = (u64)pp->msi_data;
 
-       if (!IS_ENABLED(CONFIG_PCI_MSI))
+       if (!pci_msi_enabled() || !pp->has_msi_ctrl)
                return;
 
        /* Program the msi_data */
        dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_LO, lower_32_bits(msi_target));
        dw_pcie_writel_dbi(pci, PCIE_MSI_ADDR_HI, upper_32_bits(msi_target));
 }
-EXPORT_SYMBOL_GPL(dw_pcie_msi_init);
 
 int dw_pcie_host_init(struct pcie_port *pp)
 {
@@ -357,44 +356,50 @@ int dw_pcie_host_init(struct pcie_port *pp)
                }
        }
 
-       ret = of_property_read_u32(np, "num-viewport", &pci->num_viewport);
-       if (ret)
-               pci->num_viewport = 2;
-
        if (pci->link_gen < 1)
                pci->link_gen = of_pci_get_max_link_speed(np);
 
        if (pci_msi_enabled()) {
-               /*
-                * If a specific SoC driver needs to change the
-                * default number of vectors, it needs to implement
-                * the set_num_vectors callback.
-                */
-               if (!pp->ops->set_num_vectors) {
+               pp->has_msi_ctrl = !(pp->ops->msi_host_init ||
+                                    of_property_read_bool(np, "msi-parent") ||
+                                    of_property_read_bool(np, "msi-map"));
+
+               if (!pp->num_vectors) {
                        pp->num_vectors = MSI_DEF_NUM_VECTORS;
-               } else {
-                       pp->ops->set_num_vectors(pp);
-
-                       if (pp->num_vectors > MAX_MSI_IRQS ||
-                           pp->num_vectors == 0) {
-                               dev_err(dev,
-                                       "Invalid number of vectors\n");
-                               return -EINVAL;
-                       }
+               } else if (pp->num_vectors > MAX_MSI_IRQS) {
+                       dev_err(dev, "Invalid number of vectors\n");
+                       return -EINVAL;
                }
 
-               if (!pp->ops->msi_host_init) {
+               if (pp->ops->msi_host_init) {
+                       ret = pp->ops->msi_host_init(pp);
+                       if (ret < 0)
+                               return ret;
+               } else if (pp->has_msi_ctrl) {
+                       if (!pp->msi_irq) {
+                               pp->msi_irq = platform_get_irq_byname_optional(pdev, "msi");
+                               if (pp->msi_irq < 0) {
+                                       pp->msi_irq = platform_get_irq(pdev, 0);
+                                       if (pp->msi_irq < 0)
+                                               return pp->msi_irq;
+                               }
+                       }
+
                        pp->msi_irq_chip = &dw_pci_msi_bottom_irq_chip;
 
                        ret = dw_pcie_allocate_domains(pp);
                        if (ret)
                                return ret;
 
-                       if (pp->msi_irq)
+                       if (pp->msi_irq > 0)
                                irq_set_chained_handler_and_data(pp->msi_irq,
                                                            dw_chained_msi_isr,
                                                            pp);
 
+                       ret = dma_set_mask(pci->dev, DMA_BIT_MASK(32));
+                       if (ret)
+                               dev_warn(pci->dev, "Failed to set DMA mask to 32-bit. Devices with only 32-bit MSI support may not work properly\n");
+
                        pp->msi_data = dma_map_single_attrs(pci->dev, &pp->msi_msg,
                                                      sizeof(pp->msi_msg),
                                                      DMA_FROM_DEVICE,
@@ -404,10 +409,6 @@ int dw_pcie_host_init(struct pcie_port *pp)
                                pp->msi_data = 0;
                                goto err_free_msi;
                        }
-               } else {
-                       ret = pp->ops->msi_host_init(pp);
-                       if (ret < 0)
-                               return ret;
                }
        }
 
@@ -421,6 +422,18 @@ int dw_pcie_host_init(struct pcie_port *pp)
                        goto err_free_msi;
        }
 
+       dw_pcie_setup_rc(pp);
+       dw_pcie_msi_init(pp);
+
+       if (!dw_pcie_link_up(pci) && pci->ops->start_link) {
+               ret = pci->ops->start_link(pci);
+               if (ret)
+                       goto err_free_msi;
+       }
+
+       /* Ignore errors, the link may come up later */
+       dw_pcie_wait_for_link(pci);
+
        bridge->sysdata = pp;
 
        ret = pci_host_probe(bridge);
@@ -428,7 +441,7 @@ int dw_pcie_host_init(struct pcie_port *pp)
                return 0;
 
 err_free_msi:
-       if (pci_msi_enabled() && !pp->ops->msi_host_init)
+       if (pp->has_msi_ctrl)
                dw_pcie_free_msi(pp);
        return ret;
 }
@@ -438,7 +451,7 @@ void dw_pcie_host_deinit(struct pcie_port *pp)
 {
        pci_stop_root_bus(pp->bridge->bus);
        pci_remove_root_bus(pp->bridge->bus);
-       if (pci_msi_enabled() && !pp->ops->msi_host_init)
+       if (pp->has_msi_ctrl)
                dw_pcie_free_msi(pp);
 }
 EXPORT_SYMBOL_GPL(dw_pcie_host_deinit);
@@ -534,6 +547,7 @@ static struct pci_ops dw_pcie_ops = {
 
 void dw_pcie_setup_rc(struct pcie_port *pp)
 {
+       int i;
        u32 val, ctrl, num_ctrls;
        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 
@@ -545,7 +559,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
 
        dw_pcie_setup(pci);
 
-       if (pci_msi_enabled() && !pp->ops->msi_host_init) {
+       if (pp->has_msi_ctrl) {
                num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL;
 
                /* Initialize IRQ Status array */
@@ -583,6 +597,10 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
                PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
        dw_pcie_writel_dbi(pci, PCI_COMMAND, val);
 
+       /* Ensure all outbound windows are disabled so there are multiple matches */
+       for (i = 0; i < pci->num_ob_windows; i++)
+               dw_pcie_disable_atu(pci, i, DW_PCIE_REGION_OUTBOUND);
+
        /*
         * If the platform provides its own child bus config accesses, it means
         * the platform uses its own address translation component rather than
@@ -597,7 +615,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
                        if (resource_type(entry->res) != IORESOURCE_MEM)
                                continue;
 
-                       if (pci->num_viewport <= ++atu_idx)
+                       if (pci->num_ob_windows <= ++atu_idx)
                                break;
 
                        dw_pcie_prog_outbound_atu(pci, atu_idx,
@@ -607,7 +625,7 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
                }
 
                if (pp->io_size) {
-                       if (pci->num_viewport > ++atu_idx)
+                       if (pci->num_ob_windows > ++atu_idx)
                                dw_pcie_prog_outbound_atu(pci, atu_idx,
                                                          PCIE_ATU_TYPE_IO, pp->io_base,
                                                          pp->io_bus_addr, pp->io_size);
@@ -615,9 +633,9 @@ void dw_pcie_setup_rc(struct pcie_port *pp)
                                pci->io_cfg_atu_shared = true;
                }
 
-               if (pci->num_viewport <= atu_idx)
+               if (pci->num_ob_windows <= atu_idx)
                        dev_warn(pci->dev, "Resources exceed number of ATU entries (%d)",
-                                pci->num_viewport);
+                                pci->num_ob_windows);
        }
 
        dw_pcie_writel_dbi(pci, PCI_BASE_ADDRESS_0, 0);