Merge tag 'irq-core-2020-12-23' of git://git.kernel.org/pub/scm/linux/kernel/git...

[linux-2.6-microblaze.git] / drivers / net / ethernet / mellanox / mlx5 / core / en.h

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/en.h b/drivers/net/ethernet/mellanox/mlx5/core/en.h
index 45fd585..055baf3 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/en.h
+++ b/drivers/net/ethernet/mellanox/mlx5/core/en.h
@@ -227,6 +227,7 @@ enum mlx5e_priv_flag {
        MLX5E_PFLAG_RX_NO_CSUM_COMPLETE,
        MLX5E_PFLAG_XDP_TX_MPWQE,
        MLX5E_PFLAG_SKB_TX_MPWQE,
+       MLX5E_PFLAG_TX_PORT_TS,
        MLX5E_NUM_PFLAGS, /* Keep last */
 };
 
@@ -282,10 +283,12 @@ struct mlx5e_cq {
        u16                        event_ctr;
        struct napi_struct        *napi;
        struct mlx5_core_cq        mcq;
-       struct mlx5e_channel      *channel;
+       struct mlx5e_ch_stats     *ch_stats;
 
        /* control */
+       struct net_device         *netdev;
        struct mlx5_core_dev      *mdev;
+       struct mlx5e_priv         *priv;
        struct mlx5_wq_ctrl        wq_ctrl;
 } ____cacheline_aligned_in_smp;
 
@@ -329,6 +332,15 @@ struct mlx5e_tx_mpwqe {
        u8 inline_on;
 };
 
+struct mlx5e_skb_fifo {
+       struct sk_buff **fifo;
+       u16 *pc;
+       u16 *cc;
+       u16 mask;
+};
+
+struct mlx5e_ptpsq;
+
 struct mlx5e_txqsq {
        /* data path */
 
@@ -349,11 +361,10 @@ struct mlx5e_txqsq {
        /* read only */
        struct mlx5_wq_cyc         wq;
        u32                        dma_fifo_mask;
-       u16                        skb_fifo_mask;
        struct mlx5e_sq_stats     *stats;
        struct {
                struct mlx5e_sq_dma       *dma_fifo;
-               struct sk_buff           **skb_fifo;
+               struct mlx5e_skb_fifo      skb_fifo;
                struct mlx5e_tx_wqe_info  *wqe_info;
        } db;
        void __iomem              *uar_map;
@@ -367,14 +378,17 @@ struct mlx5e_txqsq {
        unsigned int               hw_mtu;
        struct hwtstamp_config    *tstamp;
        struct mlx5_clock         *clock;
+       struct net_device         *netdev;
+       struct mlx5_core_dev      *mdev;
+       struct mlx5e_priv         *priv;
 
        /* control path */
        struct mlx5_wq_ctrl        wq_ctrl;
-       struct mlx5e_channel      *channel;
        int                        ch_ix;
        int                        txq_ix;
        u32                        rate_limit;
        struct work_struct         recover_work;
+       struct mlx5e_ptpsq        *ptpsq;
 } ____cacheline_aligned_in_smp;
 
 struct mlx5e_dma_info {
@@ -593,7 +607,6 @@ struct mlx5e_rq {
                u8             map_dir;   /* dma map direction */
        } buff;
 
-       struct mlx5e_channel  *channel;
        struct device         *pdev;
        struct net_device     *netdev;
        struct mlx5e_rq_stats *stats;
@@ -602,6 +615,8 @@ struct mlx5e_rq {
        struct mlx5e_page_cache page_cache;
        struct hwtstamp_config *tstamp;
        struct mlx5_clock      *clock;
+       struct mlx5e_icosq    *icosq;
+       struct mlx5e_priv     *priv;
 
        mlx5e_fp_handle_rx_cqe handle_rx_cqe;
        mlx5e_fp_post_rx_wqes  post_wqes;
@@ -681,8 +696,11 @@ struct mlx5e_channel {
        int                        cpu;
 };
 
+struct mlx5e_port_ptp;
+
 struct mlx5e_channels {
        struct mlx5e_channel **c;
+       struct mlx5e_port_ptp  *port_ptp;
        unsigned int           num;
        struct mlx5e_params    params;
 };
@@ -697,6 +715,12 @@ struct mlx5e_channel_stats {
        struct mlx5e_xdpsq_stats xsksq;
 } ____cacheline_aligned_in_smp;
 
+struct mlx5e_port_ptp_stats {
+       struct mlx5e_ch_stats ch;
+       struct mlx5e_sq_stats sq[MLX5E_MAX_NUM_TC];
+       struct mlx5e_ptp_cq_stats cq[MLX5E_MAX_NUM_TC];
+} ____cacheline_aligned_in_smp;
+
 enum {
        MLX5E_STATE_OPENED,
        MLX5E_STATE_DESTROYING,
@@ -766,8 +790,10 @@ struct mlx5e_scratchpad {
 
 struct mlx5e_priv {
        /* priv data path fields - start */
-       struct mlx5e_txqsq *txq2sq[MLX5E_MAX_NUM_CHANNELS * MLX5E_MAX_NUM_TC];
+       /* +1 for port ptp ts */
+       struct mlx5e_txqsq *txq2sq[(MLX5E_MAX_NUM_CHANNELS + 1) * MLX5E_MAX_NUM_TC];
        int channel_tc2realtxq[MLX5E_MAX_NUM_CHANNELS][MLX5E_MAX_NUM_TC];
+       int port_ptp_tc2realtxq[MLX5E_MAX_NUM_TC];
 #ifdef CONFIG_MLX5_CORE_EN_DCB
        struct mlx5e_dcbx_dp       dcbx_dp;
 #endif
@@ -802,12 +828,15 @@ struct mlx5e_priv {
        struct net_device         *netdev;
        struct mlx5e_stats         stats;
        struct mlx5e_channel_stats channel_stats[MLX5E_MAX_NUM_CHANNELS];
+       struct mlx5e_port_ptp_stats port_ptp_stats;
        u16                        max_nch;
        u8                         max_opened_tc;
+       bool                       port_ptp_opened;
        struct hwtstamp_config     tstamp;
        u16                        q_counter;
        u16                        drop_rq_q_counter;
        struct notifier_block      events_nb;
+       int                        num_tc_x_num_ch;
 
        struct udp_tunnel_nic_info nic_info;
 #ifdef CONFIG_MLX5_CORE_EN_DCB
@@ -923,9 +952,17 @@ int mlx5e_open_xdpsq(struct mlx5e_channel *c, struct mlx5e_params *params,
                     struct mlx5e_xdpsq *sq, bool is_redirect);
 void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq);
 
+struct mlx5e_create_cq_param {
+       struct napi_struct *napi;
+       struct mlx5e_ch_stats *ch_stats;
+       int node;
+       int ix;
+};
+
 struct mlx5e_cq_param;
-int mlx5e_open_cq(struct mlx5e_channel *c, struct dim_cq_moder moder,
-                 struct mlx5e_cq_param *param, struct mlx5e_cq *cq);
+int mlx5e_open_cq(struct mlx5e_priv *priv, struct dim_cq_moder moder,
+                 struct mlx5e_cq_param *param, struct mlx5e_create_cq_param *ccp,
+                 struct mlx5e_cq *cq);
 void mlx5e_close_cq(struct mlx5e_cq *cq);
 
 int mlx5e_open_locked(struct net_device *netdev);
@@ -974,7 +1011,17 @@ void mlx5e_deactivate_icosq(struct mlx5e_icosq *icosq);
 int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
                    struct mlx5e_modify_sq_param *p);
 void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq);
+void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq);
+void mlx5e_free_txqsq(struct mlx5e_txqsq *sq);
 void mlx5e_tx_disable_queue(struct netdev_queue *txq);
+int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa);
+void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq);
+struct mlx5e_create_sq_param;
+int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
+                       struct mlx5e_sq_param *param,
+                       struct mlx5e_create_sq_param *csp,
+                       u32 *sqn);
+void mlx5e_tx_err_cqe_work(struct work_struct *recover_work);
 
 static inline bool mlx5_tx_swp_supported(struct mlx5_core_dev *mdev)
 {