Merge branch 'misc.namei' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs

[linux-2.6-microblaze.git] / drivers / net / ethernet / hisilicon / hns3 / hns3pf / hclge_cmd.c

diff --git a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
index 887297e..ac9b695 100644 (file)
--- a/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
+++ b/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
@@ -169,17 +169,19 @@ static bool hclge_is_special_opcode(u16 opcode)
        /* these commands have several descriptors,
         * and use the first one to save opcode and return value
         */
-       u16 spec_opcode[] = {HCLGE_OPC_STATS_64_BIT,
-                            HCLGE_OPC_STATS_32_BIT,
-                            HCLGE_OPC_STATS_MAC,
-                            HCLGE_OPC_STATS_MAC_ALL,
-                            HCLGE_OPC_QUERY_32_BIT_REG,
-                            HCLGE_OPC_QUERY_64_BIT_REG,
-                            HCLGE_QUERY_CLEAR_MPF_RAS_INT,
-                            HCLGE_QUERY_CLEAR_PF_RAS_INT,
-                            HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
-                            HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
-                            HCLGE_QUERY_ALL_ERR_INFO};
+       static const u16 spec_opcode[] = {
+               HCLGE_OPC_STATS_64_BIT,
+               HCLGE_OPC_STATS_32_BIT,
+               HCLGE_OPC_STATS_MAC,
+               HCLGE_OPC_STATS_MAC_ALL,
+               HCLGE_OPC_QUERY_32_BIT_REG,
+               HCLGE_OPC_QUERY_64_BIT_REG,
+               HCLGE_QUERY_CLEAR_MPF_RAS_INT,
+               HCLGE_QUERY_CLEAR_PF_RAS_INT,
+               HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT,
+               HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT,
+               HCLGE_QUERY_ALL_ERR_INFO
+       };
        int i;
 
        for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
@@ -360,41 +362,34 @@ static void hclge_set_default_capability(struct hclge_dev *hdev)
        }
 }
 
+static const struct hclge_caps_bit_map hclge_cmd_caps_bit_map0[] = {
+       {HCLGE_CAP_UDP_GSO_B, HNAE3_DEV_SUPPORT_UDP_GSO_B},
+       {HCLGE_CAP_PTP_B, HNAE3_DEV_SUPPORT_PTP_B},
+       {HCLGE_CAP_INT_QL_B, HNAE3_DEV_SUPPORT_INT_QL_B},
+       {HCLGE_CAP_TQP_TXRX_INDEP_B, HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B},
+       {HCLGE_CAP_HW_TX_CSUM_B, HNAE3_DEV_SUPPORT_HW_TX_CSUM_B},
+       {HCLGE_CAP_UDP_TUNNEL_CSUM_B, HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B},
+       {HCLGE_CAP_FD_FORWARD_TC_B, HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B},
+       {HCLGE_CAP_FEC_B, HNAE3_DEV_SUPPORT_FEC_B},
+       {HCLGE_CAP_PAUSE_B, HNAE3_DEV_SUPPORT_PAUSE_B},
+       {HCLGE_CAP_PHY_IMP_B, HNAE3_DEV_SUPPORT_PHY_IMP_B},
+       {HCLGE_CAP_RAS_IMP_B, HNAE3_DEV_SUPPORT_RAS_IMP_B},
+       {HCLGE_CAP_RXD_ADV_LAYOUT_B, HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B},
+       {HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B},
+       {HCLGE_CAP_PORT_VLAN_BYPASS_B, HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B},
+};
+
 static void hclge_parse_capability(struct hclge_dev *hdev,
                                   struct hclge_query_version_cmd *cmd)
 {
        struct hnae3_ae_dev *ae_dev = pci_get_drvdata(hdev->pdev);
-       u32 caps;
+       u32 caps, i;
 
        caps = __le32_to_cpu(cmd->caps[0]);
-       if (hnae3_get_bit(caps, HCLGE_CAP_UDP_GSO_B))
-               set_bit(HNAE3_DEV_SUPPORT_UDP_GSO_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PTP_B))
-               set_bit(HNAE3_DEV_SUPPORT_PTP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_INT_QL_B))
-               set_bit(HNAE3_DEV_SUPPORT_INT_QL_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_TQP_TXRX_INDEP_B))
-               set_bit(HNAE3_DEV_SUPPORT_TQP_TXRX_INDEP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_HW_TX_CSUM_B))
-               set_bit(HNAE3_DEV_SUPPORT_HW_TX_CSUM_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_UDP_TUNNEL_CSUM_B))
-               set_bit(HNAE3_DEV_SUPPORT_UDP_TUNNEL_CSUM_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_FD_FORWARD_TC_B))
-               set_bit(HNAE3_DEV_SUPPORT_FD_FORWARD_TC_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_FEC_B))
-               set_bit(HNAE3_DEV_SUPPORT_FEC_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PAUSE_B))
-               set_bit(HNAE3_DEV_SUPPORT_PAUSE_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PHY_IMP_B))
-               set_bit(HNAE3_DEV_SUPPORT_PHY_IMP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_RAS_IMP_B))
-               set_bit(HNAE3_DEV_SUPPORT_RAS_IMP_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_RXD_ADV_LAYOUT_B))
-               set_bit(HNAE3_DEV_SUPPORT_RXD_ADV_LAYOUT_B, ae_dev->caps);
-       if (hnae3_get_bit(caps, HCLGE_CAP_PORT_VLAN_BYPASS_B)) {
-               set_bit(HNAE3_DEV_SUPPORT_PORT_VLAN_BYPASS_B, ae_dev->caps);
-               set_bit(HNAE3_DEV_SUPPORT_VLAN_FLTR_MDF_B, ae_dev->caps);
-       }
+       for (i = 0; i < ARRAY_SIZE(hclge_cmd_caps_bit_map0); i++)
+               if (hnae3_get_bit(caps, hclge_cmd_caps_bit_map0[i].imp_bit))
+                       set_bit(hclge_cmd_caps_bit_map0[i].local_bit,
+                               ae_dev->caps);
 }
 
 static __le32 hclge_build_api_caps(void)
@@ -573,9 +568,13 @@ static void hclge_cmd_uninit_regs(struct hclge_hw *hw)
 
 void hclge_cmd_uninit(struct hclge_dev *hdev)
 {
+       set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
+       /* wait to ensure that the firmware completes the possible left
+        * over commands.
+        */
+       msleep(HCLGE_CMDQ_CLEAR_WAIT_TIME);
        spin_lock_bh(&hdev->hw.cmq.csq.lock);
        spin_lock(&hdev->hw.cmq.crq.lock);
-       set_bit(HCLGE_STATE_CMD_DISABLE, &hdev->state);
        hclge_cmd_uninit_regs(&hdev->hw);
        spin_unlock(&hdev->hw.cmq.crq.lock);
        spin_unlock_bh(&hdev->hw.cmq.csq.lock);